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2024-10-22 8ac6c7a54ed1b98d142dce24b11c6de6a1e239a5 
 kernel/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
....@@ -1,13 +1,15 @@
1
-// SPDX-License-Identifier: (GPL-2.0+ or MIT)
2
-/*
3
- * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
4
- */
1
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
+// Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
53 
64 #include <dt-bindings/interrupt-controller/arm-gic.h>
75 #include <dt-bindings/clock/sun50i-h6-ccu.h>
86 #include <dt-bindings/clock/sun50i-h6-r-ccu.h>
7
+#include <dt-bindings/clock/sun8i-de2.h>
8
+#include <dt-bindings/clock/sun8i-tcon-top.h>
99 #include <dt-bindings/reset/sun50i-h6-ccu.h>
1010 #include <dt-bindings/reset/sun50i-h6-r-ccu.h>
11
+#include <dt-bindings/reset/sun8i-de2.h>
12
+#include <dt-bindings/thermal/thermal.h>
1113 
1214 / {
1315 	interrupt-parent = <&gic>;
....@@ -19,40 +21,50 @@
1921 		#size-cells = <0>;
2022 
2123 		cpu0: cpu@0 {
22
-			compatible = "arm,cortex-a53", "arm,armv8";
24
+			compatible = "arm,cortex-a53";
2325 			device_type = "cpu";
2426 			reg = <0>;
2527 			enable-method = "psci";
28
+			clocks = <&ccu CLK_CPUX>;
29
+			clock-latency-ns = <244144>; /* 8 32k periods */
30
+			#cooling-cells = <2>;
2631 		};
2732 
2833 		cpu1: cpu@1 {
29
-			compatible = "arm,cortex-a53", "arm,armv8";
34
+			compatible = "arm,cortex-a53";
3035 			device_type = "cpu";
3136 			reg = <1>;
3237 			enable-method = "psci";
38
+			clocks = <&ccu CLK_CPUX>;
39
+			clock-latency-ns = <244144>; /* 8 32k periods */
40
+			#cooling-cells = <2>;
3341 		};
3442 
3543 		cpu2: cpu@2 {
36
-			compatible = "arm,cortex-a53", "arm,armv8";
44
+			compatible = "arm,cortex-a53";
3745 			device_type = "cpu";
3846 			reg = <2>;
3947 			enable-method = "psci";
48
+			clocks = <&ccu CLK_CPUX>;
49
+			clock-latency-ns = <244144>; /* 8 32k periods */
50
+			#cooling-cells = <2>;
4051 		};
4152 
4253 		cpu3: cpu@3 {
43
-			compatible = "arm,cortex-a53", "arm,armv8";
54
+			compatible = "arm,cortex-a53";
4455 			device_type = "cpu";
4556 			reg = <3>;
4657 			enable-method = "psci";
58
+			clocks = <&ccu CLK_CPUX>;
59
+			clock-latency-ns = <244144>; /* 8 32k periods */
60
+			#cooling-cells = <2>;
4761 		};
4862 	};
4963 
50
-	iosc: internal-osc-clk {
51
-		#clock-cells = <0>;
52
-		compatible = "fixed-clock";
53
-		clock-frequency = <16000000>;
54
-		clock-accuracy = <300000000>;
55
-		clock-output-names = "iosc";
64
+	de: display-engine {
65
+		compatible = "allwinner,sun50i-h6-display-engine";
66
+		allwinner,pipelines = <&mixer0>;
67
+		status = "disabled";
5668 	};
5769 
5870 	osc24M: osc24M_clk {
....@@ -60,13 +72,6 @@
6072 		compatible = "fixed-clock";
6173 		clock-frequency = <24000000>;
6274 		clock-output-names = "osc24M";
63
-	};
64
-
65
-	osc32k: osc32k_clk {
66
-		#clock-cells = <0>;
67
-		compatible = "fixed-clock";
68
-		clock-frequency = <32768>;
69
-		clock-output-names = "osc32k";
7075 	};
7176 
7277 	pmu {
....@@ -85,6 +90,7 @@
8590 
8691 	timer {
8792 		compatible = "arm,armv8-timer";
93
+		arm,no-tick-in-suspend;
8894 		interrupts = <GIC_PPI 13
8995 			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
9096 			     <GIC_PPI 14
....@@ -101,13 +107,188 @@
101107 		#size-cells = <1>;
102108 		ranges;
103109 
110
+		bus@1000000 {
111
+			compatible = "allwinner,sun50i-h6-de3",
112
+				     "allwinner,sun50i-a64-de2";
113
+			reg = <0x1000000 0x400000>;
114
+			allwinner,sram = <&de2_sram 1>;
115
+			#address-cells = <1>;
116
+			#size-cells = <1>;
117
+			ranges = <0 0x1000000 0x400000>;
118
+
119
+			display_clocks: clock@0 {
120
+				compatible = "allwinner,sun50i-h6-de3-clk";
121
+				reg = <0x0 0x10000>;
122
+				clocks = <&ccu CLK_DE>,
123
+					 <&ccu CLK_BUS_DE>;
124
+				clock-names = "mod",
125
+					      "bus";
126
+				resets = <&ccu RST_BUS_DE>;
127
+				#clock-cells = <1>;
128
+				#reset-cells = <1>;
129
+			};
130
+
131
+			mixer0: mixer@100000 {
132
+				compatible = "allwinner,sun50i-h6-de3-mixer-0";
133
+				reg = <0x100000 0x100000>;
134
+				clocks = <&display_clocks CLK_BUS_MIXER0>,
135
+					 <&display_clocks CLK_MIXER0>;
136
+				clock-names = "bus",
137
+					      "mod";
138
+				resets = <&display_clocks RST_MIXER0>;
139
+				iommus = <&iommu 0>;
140
+
141
+				ports {
142
+					#address-cells = <1>;
143
+					#size-cells = <0>;
144
+
145
+					mixer0_out: port@1 {
146
+						reg = <1>;
147
+
148
+						mixer0_out_tcon_top_mixer0: endpoint {
149
+							remote-endpoint = <&tcon_top_mixer0_in_mixer0>;
150
+						};
151
+					};
152
+				};
153
+			};
154
+		};
155
+
156
+		video-codec@1c0e000 {
157
+			compatible = "allwinner,sun50i-h6-video-engine";
158
+			reg = <0x01c0e000 0x2000>;
159
+			clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
160
+				 <&ccu CLK_MBUS_VE>;
161
+			clock-names = "ahb", "mod", "ram";
162
+			resets = <&ccu RST_BUS_VE>;
163
+			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
164
+			allwinner,sram = <&ve_sram 1>;
165
+			iommus = <&iommu 3>;
166
+		};
167
+
168
+		gpu: gpu@1800000 {
169
+			compatible = "allwinner,sun50i-h6-mali",
170
+				     "arm,mali-t720";
171
+			reg = <0x01800000 0x4000>;
172
+			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
173
+				     <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
174
+				     <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
175
+			interrupt-names = "job", "mmu", "gpu";
176
+			clocks = <&ccu CLK_GPU>, <&ccu CLK_BUS_GPU>;
177
+			clock-names = "core", "bus";
178
+			resets = <&ccu RST_BUS_GPU>;
179
+			status = "disabled";
180
+		};
181
+
182
+		crypto: crypto@1904000 {
183
+			compatible = "allwinner,sun50i-h6-crypto";
184
+			reg = <0x01904000 0x1000>;
185
+			interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
186
+			clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>, <&ccu CLK_MBUS_CE>;
187
+			clock-names = "bus", "mod", "ram";
188
+			resets = <&ccu RST_BUS_CE>;
189
+		};
190
+
191
+		syscon: syscon@3000000 {
192
+			compatible = "allwinner,sun50i-h6-system-control",
193
+				     "allwinner,sun50i-a64-system-control";
194
+			reg = <0x03000000 0x1000>;
195
+			#address-cells = <1>;
196
+			#size-cells = <1>;
197
+			ranges;
198
+
199
+			sram_c: sram@28000 {
200
+				compatible = "mmio-sram";
201
+				reg = <0x00028000 0x1e000>;
202
+				#address-cells = <1>;
203
+				#size-cells = <1>;
204
+				ranges = <0 0x00028000 0x1e000>;
205
+
206
+				de2_sram: sram-section@0 {
207
+					compatible = "allwinner,sun50i-h6-sram-c",
208
+						     "allwinner,sun50i-a64-sram-c";
209
+					reg = <0x0000 0x1e000>;
210
+				};
211
+			};
212
+
213
+			sram_c1: sram@1a00000 {
214
+				compatible = "mmio-sram";
215
+				reg = <0x01a00000 0x200000>;
216
+				#address-cells = <1>;
217
+				#size-cells = <1>;
218
+				ranges = <0 0x01a00000 0x200000>;
219
+
220
+				ve_sram: sram-section@0 {
221
+					compatible = "allwinner,sun50i-h6-sram-c1",
222
+						     "allwinner,sun4i-a10-sram-c1";
223
+					reg = <0x000000 0x200000>;
224
+				};
225
+			};
226
+		};
227
+
104228 		ccu: clock@3001000 {
105229 			compatible = "allwinner,sun50i-h6-ccu";
106230 			reg = <0x03001000 0x1000>;
107
-			clocks = <&osc24M>, <&osc32k>, <&iosc>;
231
+			clocks = <&osc24M>, <&rtc 0>, <&rtc 2>;
108232 			clock-names = "hosc", "losc", "iosc";
109233 			#clock-cells = <1>;
110234 			#reset-cells = <1>;
235
+		};
236
+
237
+		dma: dma-controller@3002000 {
238
+			compatible = "allwinner,sun50i-h6-dma";
239
+			reg = <0x03002000 0x1000>;
240
+			interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
241
+			clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>;
242
+			clock-names = "bus", "mbus";
243
+			dma-channels = <16>;
244
+			dma-requests = <46>;
245
+			resets = <&ccu RST_BUS_DMA>;
246
+			#dma-cells = <1>;
247
+		};
248
+
249
+		msgbox: mailbox@3003000 {
250
+			compatible = "allwinner,sun50i-h6-msgbox",
251
+				     "allwinner,sun6i-a31-msgbox";
252
+			reg = <0x03003000 0x1000>;
253
+			clocks = <&ccu CLK_BUS_MSGBOX>;
254
+			resets = <&ccu RST_BUS_MSGBOX>;
255
+			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
256
+			#mbox-cells = <1>;
257
+		};
258
+
259
+		sid: efuse@3006000 {
260
+			compatible = "allwinner,sun50i-h6-sid";
261
+			reg = <0x03006000 0x400>;
262
+			#address-cells = <1>;
263
+			#size-cells = <1>;
264
+
265
+			ths_calibration: thermal-sensor-calibration@14 {
266
+				reg = <0x14 0x8>;
267
+			};
268
+
269
+			cpu_speed_grade: cpu-speed-grade@1c {
270
+				reg = <0x1c 0x4>;
271
+			};
272
+		};
273
+
274
+		watchdog: watchdog@30090a0 {
275
+			compatible = "allwinner,sun50i-h6-wdt",
276
+				     "allwinner,sun6i-a31-wdt";
277
+			reg = <0x030090a0 0x20>;
278
+			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
279
+			clocks = <&osc24M>;
280
+			/* Broken on some H6 boards */
281
+			status = "disabled";
282
+		};
283
+
284
+		pwm: pwm@300a000 {
285
+			compatible = "allwinner,sun50i-h6-pwm";
286
+			reg = <0x0300a000 0x400>;
287
+			clocks = <&osc24M>, <&ccu CLK_BUS_PWM>;
288
+			clock-names = "mod", "bus";
289
+			resets = <&ccu RST_BUS_PWM>;
290
+			#pwm-cells = <3>;
291
+			status = "disabled";
111292 		};
112293 
113294 		pio: pinctrl@300b000 {
....@@ -117,17 +298,54 @@
117298 				     <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
118299 				     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
119300 				     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
120
-			clocks = <&ccu CLK_APB1>, <&osc24M>, <&osc32k>;
301
+			clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc 0>;
121302 			clock-names = "apb", "hosc", "losc";
122303 			gpio-controller;
123304 			#gpio-cells = <3>;
124305 			interrupt-controller;
125306 			#interrupt-cells = <3>;
126307 
308
+			ext_rgmii_pins: rgmii-pins {
309
+				pins = "PD0", "PD1", "PD2", "PD3", "PD4",
310
+				       "PD5", "PD7", "PD8", "PD9", "PD10",
311
+				       "PD11", "PD12", "PD13", "PD19", "PD20";
312
+				function = "emac";
313
+				drive-strength = <40>;
314
+			};
315
+
316
+			hdmi_pins: hdmi-pins {
317
+				pins = "PH8", "PH9", "PH10";
318
+				function = "hdmi";
319
+			};
320
+
321
+			i2c0_pins: i2c0-pins {
322
+				pins = "PD25", "PD26";
323
+				function = "i2c0";
324
+			};
325
+
326
+			i2c1_pins: i2c1-pins {
327
+				pins = "PH5", "PH6";
328
+				function = "i2c1";
329
+			};
330
+
331
+			i2c2_pins: i2c2-pins {
332
+				pins = "PD23", "PD24";
333
+				function = "i2c2";
334
+			};
335
+
127336 			mmc0_pins: mmc0-pins {
128337 				pins = "PF0", "PF1", "PF2", "PF3",
129338 				       "PF4", "PF5";
130339 				function = "mmc0";
340
+				drive-strength = <30>;
341
+				bias-pull-up;
342
+			};
343
+
344
+			/omit-if-no-ref/
345
+			mmc1_pins: mmc1-pins {
346
+				pins = "PG0", "PG1", "PG2", "PG3",
347
+				       "PG4", "PG5";
348
+				function = "mmc1";
131349 				drive-strength = <30>;
132350 				bias-pull-up;
133351 			};
....@@ -141,9 +359,49 @@
141359 				bias-pull-up;
142360 			};
143361 
144
-			uart0_ph_pins: uart0-ph {
362
+			/omit-if-no-ref/
363
+			spi0_pins: spi0-pins {
364
+				pins = "PC0", "PC2", "PC3";
365
+				function = "spi0";
366
+			};
367
+
368
+			/* pin shared with MMC2-CMD (eMMC) */
369
+			/omit-if-no-ref/
370
+			spi0_cs_pin: spi0-cs-pin {
371
+				pins = "PC5";
372
+				function = "spi0";
373
+			};
374
+
375
+			/omit-if-no-ref/
376
+			spi1_pins: spi1-pins {
377
+				pins = "PH4", "PH5", "PH6";
378
+				function = "spi1";
379
+			};
380
+
381
+			/omit-if-no-ref/
382
+			spi1_cs_pin: spi1-cs-pin {
383
+				pins = "PH3";
384
+				function = "spi1";
385
+			};
386
+
387
+			spdif_tx_pin: spdif-tx-pin {
388
+				pins = "PH7";
389
+				function = "spdif";
390
+			};
391
+
392
+			uart0_ph_pins: uart0-ph-pins {
145393 				pins = "PH0", "PH1";
146394 				function = "uart0";
395
+			};
396
+
397
+			uart1_pins: uart1-pins {
398
+				pins = "PG6", "PG7";
399
+				function = "uart1";
400
+			};
401
+
402
+			uart1_rts_cts_pins: uart1-rts-cts-pins {
403
+				pins = "PG8", "PG9";
404
+				function = "uart1";
147405 			};
148406 		};
149407 
....@@ -158,6 +416,15 @@
158416 			#interrupt-cells = <3>;
159417 		};
160418 
419
+		iommu: iommu@30f0000 {
420
+			compatible = "allwinner,sun50i-h6-iommu";
421
+			reg = <0x030f0000 0x10000>;
422
+			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
423
+			clocks = <&ccu CLK_BUS_IOMMU>;
424
+			resets = <&ccu RST_BUS_IOMMU>;
425
+			#iommu-cells = <1>;
426
+		};
427
+
161428 		mmc0: mmc@4020000 {
162429 			compatible = "allwinner,sun50i-h6-mmc",
163430 				     "allwinner,sun50i-a64-mmc";
....@@ -167,6 +434,9 @@
167434 			resets = <&ccu RST_BUS_MMC0>;
168435 			reset-names = "ahb";
169436 			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
437
+			pinctrl-names = "default";
438
+			pinctrl-0 = <&mmc0_pins>;
439
+			max-frequency = <150000000>;
170440 			status = "disabled";
171441 			#address-cells = <1>;
172442 			#size-cells = <0>;
....@@ -181,6 +451,9 @@
181451 			resets = <&ccu RST_BUS_MMC1>;
182452 			reset-names = "ahb";
183453 			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
454
+			pinctrl-names = "default";
455
+			pinctrl-0 = <&mmc1_pins>;
456
+			max-frequency = <150000000>;
184457 			status = "disabled";
185458 			#address-cells = <1>;
186459 			#size-cells = <0>;
....@@ -195,6 +468,9 @@
195468 			resets = <&ccu RST_BUS_MMC2>;
196469 			reset-names = "ahb";
197470 			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
471
+			pinctrl-names = "default";
472
+			pinctrl-0 = <&mmc2_pins>;
473
+			max-frequency = <150000000>;
198474 			status = "disabled";
199475 			#address-cells = <1>;
200476 			#size-cells = <0>;
....@@ -244,14 +520,397 @@
244520 			status = "disabled";
245521 		};
246522 
523
+		i2c0: i2c@5002000 {
524
+			compatible = "allwinner,sun50i-h6-i2c",
525
+				     "allwinner,sun6i-a31-i2c";
526
+			reg = <0x05002000 0x400>;
527
+			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
528
+			clocks = <&ccu CLK_BUS_I2C0>;
529
+			resets = <&ccu RST_BUS_I2C0>;
530
+			pinctrl-names = "default";
531
+			pinctrl-0 = <&i2c0_pins>;
532
+			status = "disabled";
533
+			#address-cells = <1>;
534
+			#size-cells = <0>;
535
+		};
536
+
537
+		i2c1: i2c@5002400 {
538
+			compatible = "allwinner,sun50i-h6-i2c",
539
+				     "allwinner,sun6i-a31-i2c";
540
+			reg = <0x05002400 0x400>;
541
+			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
542
+			clocks = <&ccu CLK_BUS_I2C1>;
543
+			resets = <&ccu RST_BUS_I2C1>;
544
+			pinctrl-names = "default";
545
+			pinctrl-0 = <&i2c1_pins>;
546
+			status = "disabled";
547
+			#address-cells = <1>;
548
+			#size-cells = <0>;
549
+		};
550
+
551
+		i2c2: i2c@5002800 {
552
+			compatible = "allwinner,sun50i-h6-i2c",
553
+				     "allwinner,sun6i-a31-i2c";
554
+			reg = <0x05002800 0x400>;
555
+			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
556
+			clocks = <&ccu CLK_BUS_I2C2>;
557
+			resets = <&ccu RST_BUS_I2C2>;
558
+			pinctrl-names = "default";
559
+			pinctrl-0 = <&i2c2_pins>;
560
+			status = "disabled";
561
+			#address-cells = <1>;
562
+			#size-cells = <0>;
563
+		};
564
+
565
+		spi0: spi@5010000 {
566
+			compatible = "allwinner,sun50i-h6-spi",
567
+				     "allwinner,sun8i-h3-spi";
568
+			reg = <0x05010000 0x1000>;
569
+			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
570
+			clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
571
+			clock-names = "ahb", "mod";
572
+			dmas = <&dma 22>, <&dma 22>;
573
+			dma-names = "rx", "tx";
574
+			resets = <&ccu RST_BUS_SPI0>;
575
+			status = "disabled";
576
+			#address-cells = <1>;
577
+			#size-cells = <0>;
578
+		};
579
+
580
+		spi1: spi@5011000 {
581
+			compatible = "allwinner,sun50i-h6-spi",
582
+				     "allwinner,sun8i-h3-spi";
583
+			reg = <0x05011000 0x1000>;
584
+			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
585
+			clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
586
+			clock-names = "ahb", "mod";
587
+			dmas = <&dma 23>, <&dma 23>;
588
+			dma-names = "rx", "tx";
589
+			resets = <&ccu RST_BUS_SPI1>;
590
+			status = "disabled";
591
+			#address-cells = <1>;
592
+			#size-cells = <0>;
593
+		};
594
+
595
+		emac: ethernet@5020000 {
596
+			compatible = "allwinner,sun50i-h6-emac",
597
+				     "allwinner,sun50i-a64-emac";
598
+			syscon = <&syscon>;
599
+			reg = <0x05020000 0x10000>;
600
+			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
601
+			interrupt-names = "macirq";
602
+			resets = <&ccu RST_BUS_EMAC>;
603
+			reset-names = "stmmaceth";
604
+			clocks = <&ccu CLK_BUS_EMAC>;
605
+			clock-names = "stmmaceth";
606
+			status = "disabled";
607
+
608
+			mdio: mdio {
609
+				compatible = "snps,dwmac-mdio";
610
+				#address-cells = <1>;
611
+				#size-cells = <0>;
612
+			};
613
+		};
614
+
615
+		spdif: spdif@5093000 {
616
+			#sound-dai-cells = <0>;
617
+			compatible = "allwinner,sun50i-h6-spdif";
618
+			reg = <0x05093000 0x400>;
619
+			interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
620
+			clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
621
+			clock-names = "apb", "spdif";
622
+			resets = <&ccu RST_BUS_SPDIF>;
623
+			dmas = <&dma 2>;
624
+			dma-names = "tx";
625
+			pinctrl-names = "default";
626
+			pinctrl-0 = <&spdif_tx_pin>;
627
+			status = "disabled";
628
+		};
629
+
630
+		usb2otg: usb@5100000 {
631
+			compatible = "allwinner,sun50i-h6-musb",
632
+				     "allwinner,sun8i-a33-musb";
633
+			reg = <0x05100000 0x0400>;
634
+			clocks = <&ccu CLK_BUS_OTG>;
635
+			resets = <&ccu RST_BUS_OTG>;
636
+			interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
637
+			interrupt-names = "mc";
638
+			phys = <&usb2phy 0>;
639
+			phy-names = "usb";
640
+			extcon = <&usb2phy 0>;
641
+			status = "disabled";
642
+		};
643
+
644
+		usb2phy: phy@5100400 {
645
+			compatible = "allwinner,sun50i-h6-usb-phy";
646
+			reg = <0x05100400 0x24>,
647
+			      <0x05101800 0x4>,
648
+			      <0x05311800 0x4>;
649
+			reg-names = "phy_ctrl",
650
+				    "pmu0",
651
+				    "pmu3";
652
+			clocks = <&ccu CLK_USB_PHY0>,
653
+				 <&ccu CLK_USB_PHY3>;
654
+			clock-names = "usb0_phy",
655
+				      "usb3_phy";
656
+			resets = <&ccu RST_USB_PHY0>,
657
+				 <&ccu RST_USB_PHY3>;
658
+			reset-names = "usb0_reset",
659
+				      "usb3_reset";
660
+			status = "disabled";
661
+			#phy-cells = <1>;
662
+		};
663
+
664
+		ehci0: usb@5101000 {
665
+			compatible = "allwinner,sun50i-h6-ehci", "generic-ehci";
666
+			reg = <0x05101000 0x100>;
667
+			interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
668
+			clocks = <&ccu CLK_BUS_OHCI0>,
669
+				 <&ccu CLK_BUS_EHCI0>,
670
+				 <&ccu CLK_USB_OHCI0>;
671
+			resets = <&ccu RST_BUS_OHCI0>,
672
+				 <&ccu RST_BUS_EHCI0>;
673
+			phys = <&usb2phy 0>;
674
+			phy-names = "usb";
675
+			status = "disabled";
676
+		};
677
+
678
+		ohci0: usb@5101400 {
679
+			compatible = "allwinner,sun50i-h6-ohci", "generic-ohci";
680
+			reg = <0x05101400 0x100>;
681
+			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
682
+			clocks = <&ccu CLK_BUS_OHCI0>,
683
+				 <&ccu CLK_USB_OHCI0>;
684
+			resets = <&ccu RST_BUS_OHCI0>;
685
+			phys = <&usb2phy 0>;
686
+			phy-names = "usb";
687
+			status = "disabled";
688
+		};
689
+
690
+		dwc3: dwc3@5200000 {
691
+			compatible = "snps,dwc3";
692
+			reg = <0x05200000 0x10000>;
693
+			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
694
+			clocks = <&ccu CLK_BUS_XHCI>,
695
+				 <&ccu CLK_BUS_XHCI>,
696
+				 <&rtc 0>;
697
+			clock-names = "ref", "bus_early", "suspend";
698
+			resets = <&ccu RST_BUS_XHCI>;
699
+			/*
700
+			 * The datasheet of the chip doesn't declare the
701
+			 * peripheral function, and there's no boards known
702
+			 * to have a USB Type-B port routed to the port.
703
+			 * In addition, no one has tested the peripheral
704
+			 * function yet.
705
+			 * So set the dr_mode to "host" in the DTSI file.
706
+			 */
707
+			dr_mode = "host";
708
+			phys = <&usb3phy>;
709
+			phy-names = "usb3-phy";
710
+			status = "disabled";
711
+		};
712
+
713
+		usb3phy: phy@5210000 {
714
+			compatible = "allwinner,sun50i-h6-usb3-phy";
715
+			reg = <0x5210000 0x10000>;
716
+			clocks = <&ccu CLK_USB_PHY1>;
717
+			resets = <&ccu RST_USB_PHY1>;
718
+			#phy-cells = <0>;
719
+			status = "disabled";
720
+		};
721
+
722
+		ehci3: usb@5311000 {
723
+			compatible = "allwinner,sun50i-h6-ehci", "generic-ehci";
724
+			reg = <0x05311000 0x100>;
725
+			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
726
+			clocks = <&ccu CLK_BUS_OHCI3>,
727
+				 <&ccu CLK_BUS_EHCI3>,
728
+				 <&ccu CLK_USB_OHCI3>;
729
+			resets = <&ccu RST_BUS_OHCI3>,
730
+				 <&ccu RST_BUS_EHCI3>;
731
+			phys = <&usb2phy 3>;
732
+			phy-names = "usb";
733
+			status = "disabled";
734
+		};
735
+
736
+		ohci3: usb@5311400 {
737
+			compatible = "allwinner,sun50i-h6-ohci", "generic-ohci";
738
+			reg = <0x05311400 0x100>;
739
+			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
740
+			clocks = <&ccu CLK_BUS_OHCI3>,
741
+				 <&ccu CLK_USB_OHCI3>;
742
+			resets = <&ccu RST_BUS_OHCI3>;
743
+			phys = <&usb2phy 3>;
744
+			phy-names = "usb";
745
+			status = "disabled";
746
+		};
747
+
748
+		hdmi: hdmi@6000000 {
749
+			compatible = "allwinner,sun50i-h6-dw-hdmi";
750
+			reg = <0x06000000 0x10000>;
751
+			reg-io-width = <1>;
752
+			interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
753
+			clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>,
754
+				 <&ccu CLK_HDMI>, <&ccu CLK_HDMI_CEC>,
755
+				 <&ccu CLK_HDCP>, <&ccu CLK_BUS_HDCP>;
756
+			clock-names = "iahb", "isfr", "tmds", "cec", "hdcp",
757
+				      "hdcp-bus";
758
+			resets = <&ccu RST_BUS_HDMI_SUB>, <&ccu RST_BUS_HDCP>;
759
+			reset-names = "ctrl", "hdcp";
760
+			phys = <&hdmi_phy>;
761
+			phy-names = "phy";
762
+			pinctrl-names = "default";
763
+			pinctrl-0 = <&hdmi_pins>;
764
+			status = "disabled";
765
+
766
+			ports {
767
+				#address-cells = <1>;
768
+				#size-cells = <0>;
769
+
770
+				hdmi_in: port@0 {
771
+					reg = <0>;
772
+
773
+					hdmi_in_tcon_top: endpoint {
774
+						remote-endpoint = <&tcon_top_hdmi_out_hdmi>;
775
+					};
776
+				};
777
+
778
+				hdmi_out: port@1 {
779
+					reg = <1>;
780
+				};
781
+			};
782
+		};
783
+
784
+		hdmi_phy: hdmi-phy@6010000 {
785
+			compatible = "allwinner,sun50i-h6-hdmi-phy";
786
+			reg = <0x06010000 0x10000>;
787
+			clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>;
788
+			clock-names = "bus", "mod";
789
+			resets = <&ccu RST_BUS_HDMI>;
790
+			reset-names = "phy";
791
+			#phy-cells = <0>;
792
+		};
793
+
794
+		tcon_top: tcon-top@6510000 {
795
+			compatible = "allwinner,sun50i-h6-tcon-top";
796
+			reg = <0x06510000 0x1000>;
797
+			clocks = <&ccu CLK_BUS_TCON_TOP>,
798
+				 <&ccu CLK_TCON_TV0>;
799
+			clock-names = "bus",
800
+				      "tcon-tv0";
801
+			clock-output-names = "tcon-top-tv0";
802
+			resets = <&ccu RST_BUS_TCON_TOP>;
803
+			#clock-cells = <1>;
804
+
805
+			ports {
806
+				#address-cells = <1>;
807
+				#size-cells = <0>;
808
+
809
+				tcon_top_mixer0_in: port@0 {
810
+					#address-cells = <1>;
811
+					#size-cells = <0>;
812
+					reg = <0>;
813
+
814
+					tcon_top_mixer0_in_mixer0: endpoint@0 {
815
+						reg = <0>;
816
+						remote-endpoint = <&mixer0_out_tcon_top_mixer0>;
817
+					};
818
+				};
819
+
820
+				tcon_top_mixer0_out: port@1 {
821
+					#address-cells = <1>;
822
+					#size-cells = <0>;
823
+					reg = <1>;
824
+
825
+					tcon_top_mixer0_out_tcon_tv: endpoint@2 {
826
+						reg = <2>;
827
+						remote-endpoint = <&tcon_tv_in_tcon_top_mixer0>;
828
+					};
829
+				};
830
+
831
+				tcon_top_hdmi_in: port@4 {
832
+					#address-cells = <1>;
833
+					#size-cells = <0>;
834
+					reg = <4>;
835
+
836
+					tcon_top_hdmi_in_tcon_tv: endpoint@0 {
837
+						reg = <0>;
838
+						remote-endpoint = <&tcon_tv_out_tcon_top>;
839
+					};
840
+				};
841
+
842
+				tcon_top_hdmi_out: port@5 {
843
+					reg = <5>;
844
+
845
+					tcon_top_hdmi_out_hdmi: endpoint {
846
+						remote-endpoint = <&hdmi_in_tcon_top>;
847
+					};
848
+				};
849
+			};
850
+		};
851
+
852
+		tcon_tv: lcd-controller@6515000 {
853
+			compatible = "allwinner,sun50i-h6-tcon-tv",
854
+				     "allwinner,sun8i-r40-tcon-tv";
855
+			reg = <0x06515000 0x1000>;
856
+			interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
857
+			clocks = <&ccu CLK_BUS_TCON_TV0>,
858
+				 <&tcon_top CLK_TCON_TOP_TV0>;
859
+			clock-names = "ahb",
860
+				      "tcon-ch1";
861
+			resets = <&ccu RST_BUS_TCON_TV0>;
862
+			reset-names = "lcd";
863
+
864
+			ports {
865
+				#address-cells = <1>;
866
+				#size-cells = <0>;
867
+
868
+				tcon_tv_in: port@0 {
869
+					reg = <0>;
870
+
871
+					tcon_tv_in_tcon_top_mixer0: endpoint {
872
+						remote-endpoint = <&tcon_top_mixer0_out_tcon_tv>;
873
+					};
874
+				};
875
+
876
+				tcon_tv_out: port@1 {
877
+					#address-cells = <1>;
878
+					#size-cells = <0>;
879
+					reg = <1>;
880
+
881
+					tcon_tv_out_tcon_top: endpoint@1 {
882
+						reg = <1>;
883
+						remote-endpoint = <&tcon_top_hdmi_in_tcon_tv>;
884
+					};
885
+				};
886
+			};
887
+		};
888
+
889
+		rtc: rtc@7000000 {
890
+			compatible = "allwinner,sun50i-h6-rtc";
891
+			reg = <0x07000000 0x400>;
892
+			interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
893
+				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
894
+			clock-output-names = "osc32k", "osc32k-out", "iosc";
895
+			#clock-cells = <1>;
896
+		};
897
+
247898 		r_ccu: clock@7010000 {
248899 			compatible = "allwinner,sun50i-h6-r-ccu";
249900 			reg = <0x07010000 0x400>;
250
-			clocks = <&osc24M>, <&osc32k>, <&iosc>,
901
+			clocks = <&osc24M>, <&rtc 0>, <&rtc 2>,
251902 				 <&ccu CLK_PLL_PERIPH0>;
252903 			clock-names = "hosc", "losc", "iosc", "pll-periph";
253904 			#clock-cells = <1>;
254905 			#reset-cells = <1>;
906
+		};
907
+
908
+		r_watchdog: watchdog@7020400 {
909
+			compatible = "allwinner,sun50i-h6-wdt",
910
+				     "allwinner,sun6i-a31-wdt";
911
+			reg = <0x07020400 0x20>;
912
+			interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
913
+			clocks = <&osc24M>;
255914 		};
256915 
257916 		r_intc: interrupt-controller@7021000 {
....@@ -268,21 +927,41 @@
268927 			reg = <0x07022000 0x400>;
269928 			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
270929 				     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
271
-			clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, <&osc32k>;
930
+			clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, <&rtc 0>;
272931 			clock-names = "apb", "hosc", "losc";
273932 			gpio-controller;
274933 			#gpio-cells = <3>;
275934 			interrupt-controller;
276935 			#interrupt-cells = <3>;
277936 
278
-			r_i2c_pins: r-i2c {
937
+			r_i2c_pins: r-i2c-pins {
279938 				pins = "PL0", "PL1";
280939 				function = "s_i2c";
281940 			};
941
+
942
+			r_ir_rx_pin: r-ir-rx-pin {
943
+				pins = "PL9";
944
+				function = "s_cir_rx";
945
+			};
946
+		};
947
+
948
+		r_ir: ir@7040000 {
949
+				compatible = "allwinner,sun50i-h6-ir",
950
+					     "allwinner,sun6i-a31-ir";
951
+				reg = <0x07040000 0x400>;
952
+				interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
953
+				clocks = <&r_ccu CLK_R_APB1_IR>,
954
+					 <&r_ccu CLK_IR>;
955
+				clock-names = "apb", "ir";
956
+				resets = <&r_ccu RST_R_APB1_IR>;
957
+				pinctrl-names = "default";
958
+				pinctrl-0 = <&r_ir_rx_pin>;
959
+				status = "disabled";
282960 		};
283961 
284962 		r_i2c: i2c@7081400 {
285
-			compatible = "allwinner,sun6i-a31-i2c";
963
+			compatible = "allwinner,sun50i-h6-i2c",
964
+				     "allwinner,sun6i-a31-i2c";
286965 			reg = <0x07081400 0x400>;
287966 			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
288967 			clocks = <&r_ccu CLK_R_APB2_I2C>;
....@@ -293,5 +972,55 @@
293972 			#address-cells = <1>;
294973 			#size-cells = <0>;
295974 		};
975
+
976
+		ths: thermal-sensor@5070400 {
977
+			compatible = "allwinner,sun50i-h6-ths";
978
+			reg = <0x05070400 0x100>;
979
+			interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
980
+			clocks = <&ccu CLK_BUS_THS>;
981
+			clock-names = "bus";
982
+			resets = <&ccu RST_BUS_THS>;
983
+			nvmem-cells = <&ths_calibration>;
984
+			nvmem-cell-names = "calibration";
985
+			#thermal-sensor-cells = <1>;
986
+		};
987
+	};
988
+
989
+	thermal-zones {
990
+		cpu-thermal {
991
+			polling-delay-passive = <0>;
992
+			polling-delay = <0>;
993
+			thermal-sensors = <&ths 0>;
994
+
995
+			trips {
996
+				cpu_alert: cpu-alert {
997
+					temperature = <85000>;
998
+					hysteresis = <2000>;
999
+					type = "passive";
1000
+				};
1001
+
1002
+				cpu-crit {
1003
+					temperature = <100000>;
1004
+					hysteresis = <0>;
1005
+					type = "critical";
1006
+				};
1007
+			};
1008
+
1009
+			cooling-maps {
1010
+				map0 {
1011
+					trip = <&cpu_alert>;
1012
+					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1013
+							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1014
+							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1015
+							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1016
+				};
1017
+			};
1018
+		};
1019
+
1020
+		gpu-thermal {
1021
+			polling-delay-passive = <0>;
1022
+			polling-delay = <0>;
1023
+			thermal-sensors = <&ths 1>;
1024
+		};
2961025 	};
2971026 };