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2024-10-22 8ac6c7a54ed1b98d142dce24b11c6de6a1e239a5 
 kernel/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
....@@ -1,46 +1,9 @@
1
-/*
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- * Copyright (C) 2016 ARM Ltd.
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- *
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- * This file is dual-licensed: you can use it either under the terms
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- * of the GPL or the X11 license, at your option. Note that this dual
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- * licensing only applies to this file, and not this project as a
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- * whole.
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- *
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- *  a) This file is free software; you can redistribute it and/or
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- *     modify it under the terms of the GNU General Public License as
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- *     published by the Free Software Foundation; either version 2 of the
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- *     License, or (at your option) any later version.
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- *
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- *     This file is distributed in the hope that it will be useful,
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- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
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- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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- *     GNU General Public License for more details.
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- *
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- * Or, alternatively,
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- *
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- *  b) Permission is hereby granted, free of charge, to any person
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- *     obtaining a copy of this software and associated documentation
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- *     files (the "Software"), to deal in the Software without
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- *     restriction, including without limitation the rights to use,
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- *     copy, modify, merge, publish, distribute, sublicense, and/or
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- *     sell copies of the Software, and to permit persons to whom the
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- *     Software is furnished to do so, subject to the following
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- *     conditions:
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- *
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- *     The above copyright notice and this permission notice shall be
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- *     included in all copies or substantial portions of the Software.
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- *
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- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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- *     OTHER DEALINGS IN THE SOFTWARE.
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- */
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+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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+// Copyright (C) 2016 ARM Ltd.
423 
434 #include <arm/sunxi-h3-h5.dtsi>
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+
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+#include <dt-bindings/thermal/thermal.h>
447 
458 / {
469 	cpus {
....@@ -48,32 +11,53 @@
4811 		#size-cells = <0>;
4912 
5013 		cpu0: cpu@0 {
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-			compatible = "arm,cortex-a53", "arm,armv8";
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+			compatible = "arm,cortex-a53";
5215 			device_type = "cpu";
5316 			reg = <0>;
5417 			enable-method = "psci";
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+			clocks = <&ccu CLK_CPUX>;
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+			clock-latency-ns = <244144>; /* 8 32k periods */
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+			#cooling-cells = <2>;
5521 		};
5622 
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-		cpu@1 {
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-			compatible = "arm,cortex-a53", "arm,armv8";
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+		cpu1: cpu@1 {
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+			compatible = "arm,cortex-a53";
5925 			device_type = "cpu";
6026 			reg = <1>;
6127 			enable-method = "psci";
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+			clocks = <&ccu CLK_CPUX>;
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+			clock-latency-ns = <244144>; /* 8 32k periods */
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+			#cooling-cells = <2>;
6231 		};
6332 
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-		cpu@2 {
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-			compatible = "arm,cortex-a53", "arm,armv8";
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+		cpu2: cpu@2 {
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+			compatible = "arm,cortex-a53";
6635 			device_type = "cpu";
6736 			reg = <2>;
6837 			enable-method = "psci";
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+			clocks = <&ccu CLK_CPUX>;
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+			clock-latency-ns = <244144>; /* 8 32k periods */
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+			#cooling-cells = <2>;
6941 		};
7042 
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-		cpu@3 {
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-			compatible = "arm,cortex-a53", "arm,armv8";
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+		cpu3: cpu@3 {
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+			compatible = "arm,cortex-a53";
7345 			device_type = "cpu";
7446 			reg = <3>;
7547 			enable-method = "psci";
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+			clocks = <&ccu CLK_CPUX>;
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+			clock-latency-ns = <244144>; /* 8 32k periods */
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+			#cooling-cells = <2>;
7651 		};
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+	};
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+
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+	pmu {
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+		compatible = "arm,cortex-a53-pmu";
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+		interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
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+			     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
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+			     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
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+			     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
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+		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
7761 	};
7862 
7963 	psci {
....@@ -83,6 +67,7 @@
8367 
8468 	timer {
8569 		compatible = "arm,armv8-timer";
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+		arm,no-tick-in-suspend;
8671 		interrupts = <GIC_PPI 13
8772 				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
8873 			     <GIC_PPI 14
....@@ -91,6 +76,139 @@
9176 				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
9277 			     <GIC_PPI 10
9378 				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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+	};
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+
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+	soc {
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+		syscon: system-control@1c00000 {
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+			compatible = "allwinner,sun50i-h5-system-control";
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+			reg = <0x01c00000 0x1000>;
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+			#address-cells = <1>;
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+			#size-cells = <1>;
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+			ranges;
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+
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+			sram_c1: sram@18000 {
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+				compatible = "mmio-sram";
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+				reg = <0x00018000 0x1c000>;
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+				#address-cells = <1>;
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+				#size-cells = <1>;
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+				ranges = <0 0x00018000 0x1c000>;
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+
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+				ve_sram: sram-section@0 {
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+					compatible = "allwinner,sun50i-h5-sram-c1",
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+						     "allwinner,sun4i-a10-sram-c1";
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+					reg = <0x000000 0x1c000>;
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+				};
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+			};
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+		};
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+
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+		video-codec@1c0e000 {
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+			compatible = "allwinner,sun50i-h5-video-engine";
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+			reg = <0x01c0e000 0x1000>;
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+			clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
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+				 <&ccu CLK_DRAM_VE>;
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+			clock-names = "ahb", "mod", "ram";
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+			resets = <&ccu RST_BUS_VE>;
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+			interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
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+			allwinner,sram = <&ve_sram 1>;
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+		};
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+
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+		crypto: crypto@1c15000 {
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+			compatible = "allwinner,sun50i-h5-crypto";
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+			reg = <0x01c15000 0x1000>;
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+			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
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+			clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
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+			clock-names = "bus", "mod";
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+			resets = <&ccu RST_BUS_CE>;
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+		};
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+
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+		mali: gpu@1e80000 {
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+			compatible = "allwinner,sun50i-h5-mali", "arm,mali-450";
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+			reg = <0x01e80000 0x30000>;
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+			/*
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+			 * While the datasheet lists an interrupt for the
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+			 * PMU, the actual silicon does not have the PMU
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+			 * block. Reads all return zero, and writes are
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+			 * ignored.
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+			 */
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+			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
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+				     <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
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+				     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
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+				     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
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+				     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
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+				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
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+				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
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+				     <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
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+				     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
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+				     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
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+				     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
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+			interrupt-names = "gp",
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+					  "gpmmu",
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+					  "pp",
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+					  "pp0",
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+					  "ppmmu0",
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+					  "pp1",
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+					  "ppmmu1",
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+					  "pp2",
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+					  "ppmmu2",
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+					  "pp3",
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+					  "ppmmu3";
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+			clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
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+			clock-names = "bus", "core";
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+			resets = <&ccu RST_BUS_GPU>;
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+
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+			assigned-clocks = <&ccu CLK_GPU>;
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+			assigned-clock-rates = <384000000>;
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+		};
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+
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+		ths: thermal-sensor@1c25000 {
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+			compatible = "allwinner,sun50i-h5-ths";
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+			reg = <0x01c25000 0x400>;
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+			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
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+			resets = <&ccu RST_BUS_THS>;
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+			clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
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+			clock-names = "bus", "mod";
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+			nvmem-cells = <&ths_calibration>;
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+			nvmem-cell-names = "calibration";
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+			#thermal-sensor-cells = <1>;
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+		};
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+	};
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+
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+	thermal-zones {
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+		cpu_thermal: cpu-thermal {
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+			polling-delay-passive = <0>;
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+			polling-delay = <0>;
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+			thermal-sensors = <&ths 0>;
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+
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+			trips {
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+				cpu_hot_trip: cpu-hot {
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+					temperature = <80000>;
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+					hysteresis = <2000>;
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+					type = "passive";
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+				};
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+
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+				cpu_very_hot_trip: cpu-very-hot {
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+					temperature = <100000>;
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+					hysteresis = <0>;
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+					type = "critical";
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+				};
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+			};
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+
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+			cooling-maps {
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+				cpu-hot-limit {
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+					trip = <&cpu_hot_trip>;
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+					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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+							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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+							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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+							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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+				};
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+			};
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+		};
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+
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+		gpu-thermal {
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+			polling-delay-passive = <0>;
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+			polling-delay = <0>;
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+			thermal-sensors = <&ths 1>;
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+		};
94212 	};
95213 };
96214 
....@@ -129,3 +247,11 @@
129247 		     <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
130248 	compatible = "allwinner,sun50i-h5-pinctrl";
131249 };
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+
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+&rtc {
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+	compatible = "allwinner,sun50i-h5-rtc";
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+};
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+
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+&sid {
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+	compatible = "allwinner,sun50i-h5-sid";
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+};