~hc/RK356X_SDK_RELEASE.git

..	..	@@ -1,46 +1,7 @@
1		-/*
2		- * Copyright (C) 2016 ARM Ltd.
3		- * based on the Allwinner H3 dtsi:
4		- * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
5		- *
6		- * This file is dual-licensed: you can use it either under the terms
7		- * of the GPL or the X11 license, at your option. Note that this dual
8		- * licensing only applies to this file, and not this project as a
9		- * whole.
10		- *
11		- * a) This file is free software; you can redistribute it and/or
12		- * modify it under the terms of the GNU General Public License as
13		- * published by the Free Software Foundation; either version 2 of the
14		- * License, or (at your option) any later version.
15		- *
16		- * This file is distributed in the hope that it will be useful,
17		- * but WITHOUT ANY WARRANTY; without even the implied warranty of
18		- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19		- * GNU General Public License for more details.
20		- *
21		- * Or, alternatively,
22		- *
23		- * b) Permission is hereby granted, free of charge, to any person
24		- * obtaining a copy of this software and associated documentation
25		- * files (the "Software"), to deal in the Software without
26		- * restriction, including without limitation the rights to use,
27		- * copy, modify, merge, publish, distribute, sublicense, and/or
28		- * sell copies of the Software, and to permit persons to whom the
29		- * Software is furnished to do so, subject to the following
30		- * conditions:
31		- *
32		- * The above copyright notice and this permission notice shall be
33		- * included in all copies or substantial portions of the Software.
34		- *
35		- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36		- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37		- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38		- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39		- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40		- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41		- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42		- * OTHER DEALINGS IN THE SOFTWARE.
43		- */
	1	+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	2	+// Copyright (C) 2016 ARM Ltd.
	3	+// based on the Allwinner H3 dtsi:
	4	+// Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
44	5
45	6	#include <dt-bindings/clock/sun50i-a64-ccu.h>
46	7	#include <dt-bindings/clock/sun8i-de2.h>
..	..	@@ -49,6 +10,7 @@
49	10	#include <dt-bindings/reset/sun50i-a64-ccu.h>
50	11	#include <dt-bindings/reset/sun8i-de2.h>
51	12	#include <dt-bindings/reset/sun8i-r-ccu.h>
	13	+#include <dt-bindings/thermal/thermal.h>
52	14
53	15	/ {
54	16	interrupt-parent = <&gic>;
..	..	@@ -84,32 +46,60 @@
84	46	#size-cells = <0>;
85	47
86	48	cpu0: cpu@0 {
87		- compatible = "arm,cortex-a53", "arm,armv8";
	49	+ compatible = "arm,cortex-a53";
88	50	device_type = "cpu";
89	51	reg = <0>;
90	52	enable-method = "psci";
	53	+ next-level-cache = <&L2>;
	54	+ clocks = <&ccu CLK_CPUX>;
	55	+ clock-names = "cpu";
	56	+ #cooling-cells = <2>;
91	57	};
92	58
93	59	cpu1: cpu@1 {
94		- compatible = "arm,cortex-a53", "arm,armv8";
	60	+ compatible = "arm,cortex-a53";
95	61	device_type = "cpu";
96	62	reg = <1>;
97	63	enable-method = "psci";
	64	+ next-level-cache = <&L2>;
	65	+ clocks = <&ccu CLK_CPUX>;
	66	+ clock-names = "cpu";
	67	+ #cooling-cells = <2>;
98	68	};
99	69
100	70	cpu2: cpu@2 {
101		- compatible = "arm,cortex-a53", "arm,armv8";
	71	+ compatible = "arm,cortex-a53";
102	72	device_type = "cpu";
103	73	reg = <2>;
104	74	enable-method = "psci";
	75	+ next-level-cache = <&L2>;
	76	+ clocks = <&ccu CLK_CPUX>;
	77	+ clock-names = "cpu";
	78	+ #cooling-cells = <2>;
105	79	};
106	80
107	81	cpu3: cpu@3 {
108		- compatible = "arm,cortex-a53", "arm,armv8";
	82	+ compatible = "arm,cortex-a53";
109	83	device_type = "cpu";
110	84	reg = <3>;
111	85	enable-method = "psci";
	86	+ next-level-cache = <&L2>;
	87	+ clocks = <&ccu CLK_CPUX>;
	88	+ clock-names = "cpu";
	89	+ #cooling-cells = <2>;
112	90	};
	91	+
	92	+ L2: l2-cache {
	93	+ compatible = "cache";
	94	+ cache-level = <2>;
	95	+ };
	96	+ };
	97	+
	98	+ de: display-engine {
	99	+ compatible = "allwinner,sun50i-a64-display-engine";
	100	+ allwinner,pipelines = <&mixer0>,
	101	+ <&mixer1>;
	102	+ status = "disabled";
113	103	};
114	104
115	105	osc24M: osc24M_clk {
..	..	@@ -123,15 +113,16 @@
123	113	#clock-cells = <0>;
124	114	compatible = "fixed-clock";
125	115	clock-frequency = <32768>;
126		- clock-output-names = "osc32k";
	116	+ clock-output-names = "ext-osc32k";
127	117	};
128	118
129		- iosc: internal-osc-clk {
130		- #clock-cells = <0>;
131		- compatible = "fixed-clock";
132		- clock-frequency = <16000000>;
133		- clock-accuracy = <300000000>;
134		- clock-output-names = "iosc";
	119	+ pmu {
	120	+ compatible = "arm,cortex-a53-pmu";
	121	+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
	122	+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
	123	+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
	124	+ <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
	125	+ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
135	126	};
136	127
137	128	psci {
..	..	@@ -139,26 +130,34 @@
139	130	method = "smc";
140	131	};
141	132
142		- sound_spdif {
	133	+ sound: sound {
143	134	compatible = "simple-audio-card";
144		- simple-audio-card,name = "On-board SPDIF";
	135	+ simple-audio-card,name = "sun50i-a64-audio";
	136	+ simple-audio-card,format = "i2s";
	137	+ simple-audio-card,frame-master = <&cpudai>;
	138	+ simple-audio-card,bitclock-master = <&cpudai>;
	139	+ simple-audio-card,mclk-fs = <128>;
	140	+ simple-audio-card,aux-devs = <&codec_analog>;
	141	+ simple-audio-card,routing =
	142	+ "Left DAC", "DACL",
	143	+ "Right DAC", "DACR",
	144	+ "ADCL", "Left ADC",
	145	+ "ADCR", "Right ADC";
	146	+ status = "disabled";
145	147
146		- simple-audio-card,cpu {
147		- sound-dai = <&spdif>;
	148	+ cpudai: simple-audio-card,cpu {
	149	+ sound-dai = <&dai>;
148	150	};
149	151
150		- simple-audio-card,codec {
151		- sound-dai = <&spdif_out>;
	152	+ link_codec: simple-audio-card,codec {
	153	+ sound-dai = <&codec>;
152	154	};
153		- };
154		-
155		- spdif_out: spdif-out {
156		- #sound-dai-cells = <0>;
157		- compatible = "linux,spdif-dit";
158	155	};
159	156
160	157	timer {
161	158	compatible = "arm,armv8-timer";
	159	+ allwinner,erratum-unknown1;
	160	+ arm,no-tick-in-suspend;
162	161	interrupts = <GIC_PPI 13
163	162	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>,
164	163	<GIC_PPI 14
..	..	@@ -169,13 +168,76 @@
169	168	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>;
170	169	};
171	170
	171	+ thermal-zones {
	172	+ cpu_thermal: cpu0-thermal {
	173	+ /* milliseconds */
	174	+ polling-delay-passive = <0>;
	175	+ polling-delay = <0>;
	176	+ thermal-sensors = <&ths 0>;
	177	+
	178	+ cooling-maps {
	179	+ map0 {
	180	+ trip = <&cpu_alert0>;
	181	+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	182	+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	183	+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	184	+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	185	+ };
	186	+ map1 {
	187	+ trip = <&cpu_alert1>;
	188	+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	189	+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	190	+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	191	+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	192	+ };
	193	+ };
	194	+
	195	+ trips {
	196	+ cpu_alert0: cpu_alert0 {
	197	+ /* milliCelsius */
	198	+ temperature = <75000>;
	199	+ hysteresis = <2000>;
	200	+ type = "passive";
	201	+ };
	202	+
	203	+ cpu_alert1: cpu_alert1 {
	204	+ /* milliCelsius */
	205	+ temperature = <90000>;
	206	+ hysteresis = <2000>;
	207	+ type = "hot";
	208	+ };
	209	+
	210	+ cpu_crit: cpu_crit {
	211	+ /* milliCelsius */
	212	+ temperature = <110000>;
	213	+ hysteresis = <2000>;
	214	+ type = "critical";
	215	+ };
	216	+ };
	217	+ };
	218	+
	219	+ gpu0_thermal: gpu0-thermal {
	220	+ /* milliseconds */
	221	+ polling-delay-passive = <0>;
	222	+ polling-delay = <0>;
	223	+ thermal-sensors = <&ths 1>;
	224	+ };
	225	+
	226	+ gpu1_thermal: gpu1-thermal {
	227	+ /* milliseconds */
	228	+ polling-delay-passive = <0>;
	229	+ polling-delay = <0>;
	230	+ thermal-sensors = <&ths 2>;
	231	+ };
	232	+ };
	233	+
172	234	soc {
173	235	compatible = "simple-bus";
174	236	#address-cells = <1>;
175	237	#size-cells = <1>;
176	238	ranges;
177	239
178		- de2@1000000 {
	240	+ bus@1000000 {
179	241	compatible = "allwinner,sun50i-a64-de2";
180	242	reg = <0x1000000 0x400000>;
181	243	allwinner,sram = <&de2_sram 1>;
..	..	@@ -185,14 +247,88 @@
185	247
186	248	display_clocks: clock@0 {
187	249	compatible = "allwinner,sun50i-a64-de2-clk";
188		- reg = <0x0 0x100000>;
189		- clocks = <&ccu CLK_DE>,
190		- <&ccu CLK_BUS_DE>;
191		- clock-names = "mod",
192		- "bus";
	250	+ reg = <0x0 0x10000>;
	251	+ clocks = <&ccu CLK_BUS_DE>,
	252	+ <&ccu CLK_DE>;
	253	+ clock-names = "bus",
	254	+ "mod";
193	255	resets = <&ccu RST_BUS_DE>;
194	256	#clock-cells = <1>;
195	257	#reset-cells = <1>;
	258	+ };
	259	+
	260	+ rotate: rotate@20000 {
	261	+ compatible = "allwinner,sun50i-a64-de2-rotate",
	262	+ "allwinner,sun8i-a83t-de2-rotate";
	263	+ reg = <0x20000 0x10000>;
	264	+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
	265	+ clocks = <&display_clocks CLK_BUS_ROT>,
	266	+ <&display_clocks CLK_ROT>;
	267	+ clock-names = "bus",
	268	+ "mod";
	269	+ resets = <&display_clocks RST_ROT>;
	270	+ };
	271	+
	272	+ mixer0: mixer@100000 {
	273	+ compatible = "allwinner,sun50i-a64-de2-mixer-0";
	274	+ reg = <0x100000 0x100000>;
	275	+ clocks = <&display_clocks CLK_BUS_MIXER0>,
	276	+ <&display_clocks CLK_MIXER0>;
	277	+ clock-names = "bus",
	278	+ "mod";
	279	+ resets = <&display_clocks RST_MIXER0>;
	280	+
	281	+ ports {
	282	+ #address-cells = <1>;
	283	+ #size-cells = <0>;
	284	+
	285	+ mixer0_out: port@1 {
	286	+ #address-cells = <1>;
	287	+ #size-cells = <0>;
	288	+ reg = <1>;
	289	+
	290	+ mixer0_out_tcon0: endpoint@0 {
	291	+ reg = <0>;
	292	+ remote-endpoint = <&tcon0_in_mixer0>;
	293	+ };
	294	+
	295	+ mixer0_out_tcon1: endpoint@1 {
	296	+ reg = <1>;
	297	+ remote-endpoint = <&tcon1_in_mixer0>;
	298	+ };
	299	+ };
	300	+ };
	301	+ };
	302	+
	303	+ mixer1: mixer@200000 {
	304	+ compatible = "allwinner,sun50i-a64-de2-mixer-1";
	305	+ reg = <0x200000 0x100000>;
	306	+ clocks = <&display_clocks CLK_BUS_MIXER1>,
	307	+ <&display_clocks CLK_MIXER1>;
	308	+ clock-names = "bus",
	309	+ "mod";
	310	+ resets = <&display_clocks RST_MIXER1>;
	311	+
	312	+ ports {
	313	+ #address-cells = <1>;
	314	+ #size-cells = <0>;
	315	+
	316	+ mixer1_out: port@1 {
	317	+ #address-cells = <1>;
	318	+ #size-cells = <0>;
	319	+ reg = <1>;
	320	+
	321	+ mixer1_out_tcon0: endpoint@0 {
	322	+ reg = <0>;
	323	+ remote-endpoint = <&tcon0_in_mixer1>;
	324	+ };
	325	+
	326	+ mixer1_out_tcon1: endpoint@1 {
	327	+ reg = <1>;
	328	+ remote-endpoint = <&tcon1_in_mixer1>;
	329	+ };
	330	+ };
	331	+ };
196	332	};
197	333	};
198	334
..	..	@@ -215,6 +351,20 @@
215	351	reg = <0x0000 0x28000>;
216	352	};
217	353	};
	354	+
	355	+ sram_c1: sram@1d00000 {
	356	+ compatible = "mmio-sram";
	357	+ reg = <0x01d00000 0x40000>;
	358	+ #address-cells = <1>;
	359	+ #size-cells = <1>;
	360	+ ranges = <0 0x01d00000 0x40000>;
	361	+
	362	+ ve_sram: sram-section@0 {
	363	+ compatible = "allwinner,sun50i-a64-sram-c1",
	364	+ "allwinner,sun4i-a10-sram-c1";
	365	+ reg = <0x000000 0x40000>;
	366	+ };
	367	+ };
218	368	};
219	369
220	370	dma: dma-controller@1c02000 {
..	..	@@ -226,6 +376,106 @@
226	376	dma-requests = <27>;
227	377	resets = <&ccu RST_BUS_DMA>;
228	378	#dma-cells = <1>;
	379	+ };
	380	+
	381	+ tcon0: lcd-controller@1c0c000 {
	382	+ compatible = "allwinner,sun50i-a64-tcon-lcd",
	383	+ "allwinner,sun8i-a83t-tcon-lcd";
	384	+ reg = <0x01c0c000 0x1000>;
	385	+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
	386	+ clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>;
	387	+ clock-names = "ahb", "tcon-ch0";
	388	+ clock-output-names = "tcon-pixel-clock";
	389	+ #clock-cells = <0>;
	390	+ resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>;
	391	+ reset-names = "lcd", "lvds";
	392	+
	393	+ ports {
	394	+ #address-cells = <1>;
	395	+ #size-cells = <0>;
	396	+
	397	+ tcon0_in: port@0 {
	398	+ #address-cells = <1>;
	399	+ #size-cells = <0>;
	400	+ reg = <0>;
	401	+
	402	+ tcon0_in_mixer0: endpoint@0 {
	403	+ reg = <0>;
	404	+ remote-endpoint = <&mixer0_out_tcon0>;
	405	+ };
	406	+
	407	+ tcon0_in_mixer1: endpoint@1 {
	408	+ reg = <1>;
	409	+ remote-endpoint = <&mixer1_out_tcon0>;
	410	+ };
	411	+ };
	412	+
	413	+ tcon0_out: port@1 {
	414	+ #address-cells = <1>;
	415	+ #size-cells = <0>;
	416	+ reg = <1>;
	417	+
	418	+ tcon0_out_dsi: endpoint@1 {
	419	+ reg = <1>;
	420	+ remote-endpoint = <&dsi_in_tcon0>;
	421	+ allwinner,tcon-channel = <1>;
	422	+ };
	423	+ };
	424	+ };
	425	+ };
	426	+
	427	+ tcon1: lcd-controller@1c0d000 {
	428	+ compatible = "allwinner,sun50i-a64-tcon-tv",
	429	+ "allwinner,sun8i-a83t-tcon-tv";
	430	+ reg = <0x01c0d000 0x1000>;
	431	+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
	432	+ clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>;
	433	+ clock-names = "ahb", "tcon-ch1";
	434	+ resets = <&ccu RST_BUS_TCON1>;
	435	+ reset-names = "lcd";
	436	+
	437	+ ports {
	438	+ #address-cells = <1>;
	439	+ #size-cells = <0>;
	440	+
	441	+ tcon1_in: port@0 {
	442	+ #address-cells = <1>;
	443	+ #size-cells = <0>;
	444	+ reg = <0>;
	445	+
	446	+ tcon1_in_mixer0: endpoint@0 {
	447	+ reg = <0>;
	448	+ remote-endpoint = <&mixer0_out_tcon1>;
	449	+ };
	450	+
	451	+ tcon1_in_mixer1: endpoint@1 {
	452	+ reg = <1>;
	453	+ remote-endpoint = <&mixer1_out_tcon1>;
	454	+ };
	455	+ };
	456	+
	457	+ tcon1_out: port@1 {
	458	+ #address-cells = <1>;
	459	+ #size-cells = <0>;
	460	+ reg = <1>;
	461	+
	462	+ tcon1_out_hdmi: endpoint@1 {
	463	+ reg = <1>;
	464	+ remote-endpoint = <&hdmi_in_tcon1>;
	465	+ };
	466	+ };
	467	+ };
	468	+ };
	469	+
	470	+ video-codec@1c0e000 {
	471	+ compatible = "allwinner,sun50i-a64-video-engine";
	472	+ reg = <0x01c0e000 0x1000>;
	473	+ clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
	474	+ <&ccu CLK_DRAM_VE>;
	475	+ clock-names = "ahb", "mod", "ram";
	476	+ resets = <&ccu RST_BUS_VE>;
	477	+ interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
	478	+ allwinner,sram = <&ve_sram 1>;
229	479	};
230	480
231	481	mmc0: mmc@1c0f000 {
..	..	@@ -270,6 +520,36 @@
270	520	#size-cells = <0>;
271	521	};
272	522
	523	+ sid: eeprom@1c14000 {
	524	+ compatible = "allwinner,sun50i-a64-sid";
	525	+ reg = <0x1c14000 0x400>;
	526	+ #address-cells = <1>;
	527	+ #size-cells = <1>;
	528	+
	529	+ ths_calibration: thermal-sensor-calibration@34 {
	530	+ reg = <0x34 0x8>;
	531	+ };
	532	+ };
	533	+
	534	+ crypto: crypto@1c15000 {
	535	+ compatible = "allwinner,sun50i-a64-crypto";
	536	+ reg = <0x01c15000 0x1000>;
	537	+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
	538	+ clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
	539	+ clock-names = "bus", "mod";
	540	+ resets = <&ccu RST_BUS_CE>;
	541	+ };
	542	+
	543	+ msgbox: mailbox@1c17000 {
	544	+ compatible = "allwinner,sun50i-a64-msgbox",
	545	+ "allwinner,sun6i-a31-msgbox";
	546	+ reg = <0x01c17000 0x1000>;
	547	+ clocks = <&ccu CLK_BUS_MSGBOX>;
	548	+ resets = <&ccu RST_BUS_MSGBOX>;
	549	+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
	550	+ #mbox-cells = <1>;
	551	+ };
	552	+
273	553	usb_otg: usb@1c19000 {
274	554	compatible = "allwinner,sun8i-a33-musb";
275	555	reg = <0x01c19000 0x0400>;
..	..	@@ -280,6 +560,7 @@
280	560	phys = <&usbphy 0>;
281	561	phy-names = "usb";
282	562	extcon = <&usbphy 0>;
	563	+ dr_mode = "otg";
283	564	status = "disabled";
284	565	};
285	566
..	..	@@ -358,7 +639,7 @@
358	639	ccu: clock@1c20000 {
359	640	compatible = "allwinner,sun50i-a64-ccu";
360	641	reg = <0x01c20000 0x400>;
361		- clocks = <&osc24M>, <&osc32k>;
	642	+ clocks = <&osc24M>, <&rtc 0>;
362	643	clock-names = "hosc", "losc";
363	644	#clock-cells = <1>;
364	645	#reset-cells = <1>;
..	..	@@ -370,21 +651,48 @@
370	651	interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
371	652	<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
372	653	<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
373		- clocks = <&ccu 58>, <&osc24M>, <&rtc 0>;
	654	+ clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
374	655	clock-names = "apb", "hosc", "losc";
375	656	gpio-controller;
376	657	#gpio-cells = <3>;
377	658	interrupt-controller;
378	659	#interrupt-cells = <3>;
379	660
380		- i2c0_pins: i2c0_pins {
	661	+ csi_pins: csi-pins {
	662	+ pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6",
	663	+ "PE7", "PE8", "PE9", "PE10", "PE11";
	664	+ function = "csi";
	665	+ };
	666	+
	667	+ /omit-if-no-ref/
	668	+ csi_mclk_pin: csi-mclk-pin {
	669	+ pins = "PE1";
	670	+ function = "csi";
	671	+ };
	672	+
	673	+ i2c0_pins: i2c0-pins {
381	674	pins = "PH0", "PH1";
382	675	function = "i2c0";
383	676	};
384	677
385		- i2c1_pins: i2c1_pins {
	678	+ i2c1_pins: i2c1-pins {
386	679	pins = "PH2", "PH3";
387	680	function = "i2c1";
	681	+ };
	682	+
	683	+ i2c2_pins: i2c2-pins {
	684	+ pins = "PE14", "PE15";
	685	+ function = "i2c2";
	686	+ };
	687	+
	688	+ /omit-if-no-ref/
	689	+ lcd_rgb666_pins: lcd-rgb666-pins {
	690	+ pins = "PD0", "PD1", "PD2", "PD3", "PD4",
	691	+ "PD5", "PD6", "PD7", "PD8", "PD9",
	692	+ "PD10", "PD11", "PD12", "PD13",
	693	+ "PD14", "PD15", "PD16", "PD17",
	694	+ "PD18", "PD19", "PD20", "PD21";
	695	+ function = "lcd0";
388	696	};
389	697
390	698	mmc0_pins: mmc0-pins {
..	..	@@ -404,7 +712,7 @@
404	712	};
405	713
406	714	mmc2_pins: mmc2-pins {
407		- pins = "PC1", "PC5", "PC6", "PC8", "PC9",
	715	+ pins = "PC5", "PC6", "PC8", "PC9",
408	716	"PC10","PC11", "PC12", "PC13",
409	717	"PC14", "PC15", "PC16";
410	718	function = "mmc2";
..	..	@@ -412,19 +720,26 @@
412	720	bias-pull-up;
413	721	};
414	722
415		- pwm_pin: pwm_pin {
	723	+ mmc2_ds_pin: mmc2-ds-pin {
	724	+ pins = "PC1";
	725	+ function = "mmc2";
	726	+ drive-strength = <30>;
	727	+ bias-pull-up;
	728	+ };
	729	+
	730	+ pwm_pin: pwm-pin {
416	731	pins = "PD22";
417	732	function = "pwm";
418	733	};
419	734
420		- rmii_pins: rmii_pins {
	735	+ rmii_pins: rmii-pins {
421	736	pins = "PD10", "PD11", "PD13", "PD14", "PD17",
422	737	"PD18", "PD19", "PD20", "PD22", "PD23";
423	738	function = "emac";
424	739	drive-strength = <40>;
425	740	};
426	741
427		- rgmii_pins: rgmii_pins {
	742	+ rgmii_pins: rgmii-pins {
428	743	pins = "PD8", "PD9", "PD10", "PD11", "PD12",
429	744	"PD13", "PD15", "PD16", "PD17", "PD18",
430	745	"PD19", "PD20", "PD21", "PD22", "PD23";
..	..	@@ -432,32 +747,32 @@
432	747	drive-strength = <40>;
433	748	};
434	749
435		- spdif_tx_pin: spdif {
	750	+ spdif_tx_pin: spdif-tx-pin {
436	751	pins = "PH8";
437	752	function = "spdif";
438	753	};
439	754
440		- spi0_pins: spi0 {
	755	+ spi0_pins: spi0-pins {
441	756	pins = "PC0", "PC1", "PC2", "PC3";
442	757	function = "spi0";
443	758	};
444	759
445		- spi1_pins: spi1 {
	760	+ spi1_pins: spi1-pins {
446	761	pins = "PD0", "PD1", "PD2", "PD3";
447	762	function = "spi1";
448	763	};
449	764
450		- uart0_pins_a: uart0 {
	765	+ uart0_pb_pins: uart0-pb-pins {
451	766	pins = "PB8", "PB9";
452	767	function = "uart0";
453	768	};
454	769
455		- uart1_pins: uart1_pins {
	770	+ uart1_pins: uart1-pins {
456	771	pins = "PG6", "PG7";
457	772	function = "uart1";
458	773	};
459	774
460		- uart1_rts_cts_pins: uart1_rts_cts_pins {
	775	+ uart1_rts_cts_pins: uart1-rts-cts-pins {
461	776	pins = "PG8", "PG9";
462	777	function = "uart1";
463	778	};
..	..	@@ -499,6 +814,14 @@
499	814	status = "disabled";
500	815	};
501	816
	817	+ lradc: lradc@1c21800 {
	818	+ compatible = "allwinner,sun50i-a64-lradc",
	819	+ "allwinner,sun8i-a83t-r-lradc";
	820	+ reg = <0x01c21800 0x400>;
	821	+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
	822	+ status = "disabled";
	823	+ };
	824	+
502	825	i2s0: i2s@1c22000 {
503	826	#sound-dai-cells = <0>;
504	827	compatible = "allwinner,sun50i-a64-i2s",
..	..	@@ -525,6 +848,42 @@
525	848	dma-names = "rx", "tx";
526	849	dmas = <&dma 4>, <&dma 4>;
527	850	status = "disabled";
	851	+ };
	852	+
	853	+ dai: dai@1c22c00 {
	854	+ #sound-dai-cells = <0>;
	855	+ compatible = "allwinner,sun50i-a64-codec-i2s";
	856	+ reg = <0x01c22c00 0x200>;
	857	+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
	858	+ clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
	859	+ clock-names = "apb", "mod";
	860	+ resets = <&ccu RST_BUS_CODEC>;
	861	+ dmas = <&dma 15>, <&dma 15>;
	862	+ dma-names = "rx", "tx";
	863	+ status = "disabled";
	864	+ };
	865	+
	866	+ codec: codec@1c22e00 {
	867	+ #sound-dai-cells = <0>;
	868	+ compatible = "allwinner,sun50i-a64-codec",
	869	+ "allwinner,sun8i-a33-codec";
	870	+ reg = <0x01c22e00 0x600>;
	871	+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
	872	+ clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
	873	+ clock-names = "bus", "mod";
	874	+ status = "disabled";
	875	+ };
	876	+
	877	+ ths: thermal-sensor@1c25000 {
	878	+ compatible = "allwinner,sun50i-a64-ths";
	879	+ reg = <0x01c25000 0x100>;
	880	+ clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
	881	+ clock-names = "bus", "mod";
	882	+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
	883	+ resets = <&ccu RST_BUS_THS>;
	884	+ nvmem-cells = <&ths_calibration>;
	885	+ nvmem-cell-names = "calibration";
	886	+ #thermal-sensor-cells = <1>;
528	887	};
529	888
530	889	uart0: serial@1c28000 {
..	..	@@ -588,6 +947,8 @@
588	947	interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
589	948	clocks = <&ccu CLK_BUS_I2C0>;
590	949	resets = <&ccu RST_BUS_I2C0>;
	950	+ pinctrl-names = "default";
	951	+ pinctrl-0 = <&i2c0_pins>;
591	952	status = "disabled";
592	953	#address-cells = <1>;
593	954	#size-cells = <0>;
..	..	@@ -599,6 +960,8 @@
599	960	interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
600	961	clocks = <&ccu CLK_BUS_I2C1>;
601	962	resets = <&ccu RST_BUS_I2C1>;
	963	+ pinctrl-names = "default";
	964	+ pinctrl-0 = <&i2c1_pins>;
602	965	status = "disabled";
603	966	#address-cells = <1>;
604	967	#size-cells = <0>;
..	..	@@ -610,11 +973,12 @@
610	973	interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
611	974	clocks = <&ccu CLK_BUS_I2C2>;
612	975	resets = <&ccu RST_BUS_I2C2>;
	976	+ pinctrl-names = "default";
	977	+ pinctrl-0 = <&i2c2_pins>;
613	978	status = "disabled";
614	979	#address-cells = <1>;
615	980	#size-cells = <0>;
616	981	};
617		-
618	982
619	983	spi0: spi@1c68000 {
620	984	compatible = "allwinner,sun8i-h3-spi";
..	..	@@ -669,6 +1033,28 @@
669	1033	};
670	1034	};
671	1035
	1036	+ mali: gpu@1c40000 {
	1037	+ compatible = "allwinner,sun50i-a64-mali", "arm,mali-400";
	1038	+ reg = <0x01c40000 0x10000>;
	1039	+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
	1040	+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
	1041	+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
	1042	+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
	1043	+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
	1044	+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
	1045	+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
	1046	+ interrupt-names = "gp",
	1047	+ "gpmmu",
	1048	+ "pp0",
	1049	+ "ppmmu0",
	1050	+ "pp1",
	1051	+ "ppmmu1",
	1052	+ "pmu";
	1053	+ clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
	1054	+ clock-names = "bus", "core";
	1055	+ resets = <&ccu RST_BUS_GPU>;
	1056	+ };
	1057	+
672	1058	gic: interrupt-controller@1c81000 {
673	1059	compatible = "arm,gic-400";
674	1060	reg = <0x01c81000 0x1000>,
..	..	@@ -691,12 +1077,126 @@
691	1077	status = "disabled";
692	1078	};
693	1079
	1080	+ mbus: dram-controller@1c62000 {
	1081	+ compatible = "allwinner,sun50i-a64-mbus";
	1082	+ reg = <0x01c62000 0x1000>;
	1083	+ clocks = <&ccu 112>;
	1084	+ #address-cells = <1>;
	1085	+ #size-cells = <1>;
	1086	+ dma-ranges = <0x00000000 0x40000000 0xc0000000>;
	1087	+ #interconnect-cells = <1>;
	1088	+ };
	1089	+
	1090	+ csi: csi@1cb0000 {
	1091	+ compatible = "allwinner,sun50i-a64-csi";
	1092	+ reg = <0x01cb0000 0x1000>;
	1093	+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
	1094	+ clocks = <&ccu CLK_BUS_CSI>,
	1095	+ <&ccu CLK_CSI_SCLK>,
	1096	+ <&ccu CLK_DRAM_CSI>;
	1097	+ clock-names = "bus", "mod", "ram";
	1098	+ resets = <&ccu RST_BUS_CSI>;
	1099	+ pinctrl-names = "default";
	1100	+ pinctrl-0 = <&csi_pins>;
	1101	+ status = "disabled";
	1102	+ };
	1103	+
	1104	+ dsi: dsi@1ca0000 {
	1105	+ compatible = "allwinner,sun50i-a64-mipi-dsi";
	1106	+ reg = <0x01ca0000 0x1000>;
	1107	+ interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
	1108	+ clocks = <&ccu CLK_BUS_MIPI_DSI>;
	1109	+ resets = <&ccu RST_BUS_MIPI_DSI>;
	1110	+ phys = <&dphy>;
	1111	+ phy-names = "dphy";
	1112	+ status = "disabled";
	1113	+ #address-cells = <1>;
	1114	+ #size-cells = <0>;
	1115	+
	1116	+ port {
	1117	+ dsi_in_tcon0: endpoint {
	1118	+ remote-endpoint = <&tcon0_out_dsi>;
	1119	+ };
	1120	+ };
	1121	+ };
	1122	+
	1123	+ dphy: d-phy@1ca1000 {
	1124	+ compatible = "allwinner,sun50i-a64-mipi-dphy",
	1125	+ "allwinner,sun6i-a31-mipi-dphy";
	1126	+ reg = <0x01ca1000 0x1000>;
	1127	+ clocks = <&ccu CLK_BUS_MIPI_DSI>,
	1128	+ <&ccu CLK_DSI_DPHY>;
	1129	+ clock-names = "bus", "mod";
	1130	+ resets = <&ccu RST_BUS_MIPI_DSI>;
	1131	+ status = "disabled";
	1132	+ #phy-cells = <0>;
	1133	+ };
	1134	+
	1135	+ deinterlace: deinterlace@1e00000 {
	1136	+ compatible = "allwinner,sun50i-a64-deinterlace",
	1137	+ "allwinner,sun8i-h3-deinterlace";
	1138	+ reg = <0x01e00000 0x20000>;
	1139	+ clocks = <&ccu CLK_BUS_DEINTERLACE>,
	1140	+ <&ccu CLK_DEINTERLACE>,
	1141	+ <&ccu CLK_DRAM_DEINTERLACE>;
	1142	+ clock-names = "bus", "mod", "ram";
	1143	+ resets = <&ccu RST_BUS_DEINTERLACE>;
	1144	+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
	1145	+ interconnects = <&mbus 9>;
	1146	+ interconnect-names = "dma-mem";
	1147	+ };
	1148	+
	1149	+ hdmi: hdmi@1ee0000 {
	1150	+ compatible = "allwinner,sun50i-a64-dw-hdmi",
	1151	+ "allwinner,sun8i-a83t-dw-hdmi";
	1152	+ reg = <0x01ee0000 0x10000>;
	1153	+ reg-io-width = <1>;
	1154	+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
	1155	+ clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
	1156	+ <&ccu CLK_HDMI>;
	1157	+ clock-names = "iahb", "isfr", "tmds";
	1158	+ resets = <&ccu RST_BUS_HDMI1>;
	1159	+ reset-names = "ctrl";
	1160	+ phys = <&hdmi_phy>;
	1161	+ phy-names = "phy";
	1162	+ status = "disabled";
	1163	+
	1164	+ ports {
	1165	+ #address-cells = <1>;
	1166	+ #size-cells = <0>;
	1167	+
	1168	+ hdmi_in: port@0 {
	1169	+ reg = <0>;
	1170	+
	1171	+ hdmi_in_tcon1: endpoint {
	1172	+ remote-endpoint = <&tcon1_out_hdmi>;
	1173	+ };
	1174	+ };
	1175	+
	1176	+ hdmi_out: port@1 {
	1177	+ reg = <1>;
	1178	+ };
	1179	+ };
	1180	+ };
	1181	+
	1182	+ hdmi_phy: hdmi-phy@1ef0000 {
	1183	+ compatible = "allwinner,sun50i-a64-hdmi-phy";
	1184	+ reg = <0x01ef0000 0x10000>;
	1185	+ clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
	1186	+ <&ccu CLK_PLL_VIDEO0>;
	1187	+ clock-names = "bus", "mod", "pll-0";
	1188	+ resets = <&ccu RST_BUS_HDMI0>;
	1189	+ reset-names = "phy";
	1190	+ #phy-cells = <0>;
	1191	+ };
	1192	+
694	1193	rtc: rtc@1f00000 {
695		- compatible = "allwinner,sun6i-a31-rtc";
696		- reg = <0x01f00000 0x54>;
	1194	+ compatible = "allwinner,sun50i-a64-rtc",
	1195	+ "allwinner,sun8i-h3-rtc";
	1196	+ reg = <0x01f00000 0x400>;
697	1197	interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
698	1198	<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
699		- clock-output-names = "rtc-osc32k", "rtc-osc32k-out";
	1199	+ clock-output-names = "osc32k", "osc32k-out", "iosc";
700	1200	clocks = <&osc32k>;
701	1201	#clock-cells = <1>;
702	1202	};
..	..	@@ -713,11 +1213,17 @@
713	1213	r_ccu: clock@1f01400 {
714	1214	compatible = "allwinner,sun50i-a64-r-ccu";
715	1215	reg = <0x01f01400 0x100>;
716		- clocks = <&osc24M>, <&osc32k>, <&iosc>,
717		- <&ccu 11>;
	1216	+ clocks = <&osc24M>, <&rtc 0>, <&rtc 2>,
	1217	+ <&ccu CLK_PLL_PERIPH0>;
718	1218	clock-names = "hosc", "losc", "iosc", "pll-periph";
719	1219	#clock-cells = <1>;
720	1220	#reset-cells = <1>;
	1221	+ };
	1222	+
	1223	+ codec_analog: codec-analog@1f015c0 {
	1224	+ compatible = "allwinner,sun50i-a64-codec-analog";
	1225	+ reg = <0x01f015c0 0x4>;
	1226	+ status = "disabled";
721	1227	};
722	1228
723	1229	r_i2c: i2c@1f02400 {
..	..	@@ -730,6 +1236,19 @@
730	1236	status = "disabled";
731	1237	#address-cells = <1>;
732	1238	#size-cells = <0>;
	1239	+ };
	1240	+
	1241	+ r_ir: ir@1f02000 {
	1242	+ compatible = "allwinner,sun50i-a64-ir",
	1243	+ "allwinner,sun6i-a31-ir";
	1244	+ reg = <0x01f02000 0x400>;
	1245	+ clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>;
	1246	+ clock-names = "apb", "ir";
	1247	+ resets = <&r_ccu RST_APB0_IR>;
	1248	+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
	1249	+ pinctrl-names = "default";
	1250	+ pinctrl-0 = <&r_ir_rx_pin>;
	1251	+ status = "disabled";
733	1252	};
734	1253
735	1254	r_pwm: pwm@1f03800 {
..	..	@@ -754,17 +1273,22 @@
754	1273	interrupt-controller;
755	1274	#interrupt-cells = <3>;
756	1275
757		- r_i2c_pins_a: i2c-a {
	1276	+ r_i2c_pl89_pins: r-i2c-pl89-pins {
758	1277	pins = "PL8", "PL9";
759	1278	function = "s_i2c";
760	1279	};
761	1280
762		- r_pwm_pin: pwm {
	1281	+ r_ir_rx_pin: r-ir-rx-pin {
	1282	+ pins = "PL11";
	1283	+ function = "s_cir_rx";
	1284	+ };
	1285	+
	1286	+ r_pwm_pin: r-pwm-pin {
763	1287	pins = "PL10";
764	1288	function = "s_pwm";
765	1289	};
766	1290
767		- r_rsb_pins: rsb {
	1291	+ r_rsb_pins: r-rsb-pins {
768	1292	pins = "PL0", "PL1";
769	1293	function = "s_rsb";
770	1294	};
..	..	@@ -789,6 +1313,7 @@
789	1313	"allwinner,sun6i-a31-wdt";
790	1314	reg = <0x01c20ca0 0x20>;
791	1315	interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
	1316	+ clocks = <&osc24M>;
792	1317	};
793	1318	};
794	1319	};