forked from ~ljy/RK356X_SDK_RELEASE

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2024-10-22 8ac6c7a54ed1b98d142dce24b11c6de6a1e239a5 
 kernel/arch/arm/boot/dts/sun5i.dtsi
....@@ -42,14 +42,14 @@
4242  *     OTHER DEALINGS IN THE SOFTWARE.
4343  */
4444 
45
-#include "skeleton.dtsi"
46
-
4745 #include <dt-bindings/clock/sun5i-ccu.h>
4846 #include <dt-bindings/dma/sun4i-a10.h>
4947 #include <dt-bindings/reset/sun5i-ccu.h>
5048 
5149 / {
5250 	interrupt-parent = <&intc>;
51
+	#address-cells = <1>;
52
+	#size-cells = <1>;
5353 
5454 	cpus {
5555 		#address-cells = <1>;
....@@ -68,7 +68,7 @@
6868 		#size-cells = <1>;
6969 		ranges;
7070 
71
-		framebuffer@0 {
71
+		framebuffer-lcd0 {
7272 			compatible = "allwinner,simple-framebuffer",
7373 				     "simple-framebuffer";
7474 			allwinner,pipeline = "de_be0-lcd0";
....@@ -77,7 +77,7 @@
7777 			status = "disabled";
7878 		};
7979 
80
-		framebuffer@1 {
80
+		framebuffer-lcd0-tve0 {
8181 			compatible = "allwinner,simple-framebuffer",
8282 				     "simple-framebuffer";
8383 			allwinner,pipeline = "de_be0-lcd0-tve0";
....@@ -93,14 +93,14 @@
9393 		#size-cells = <1>;
9494 		ranges;
9595 
96
-		osc24M: clk@1c20050 {
96
+		osc24M: clk-24M {
9797 			#clock-cells = <0>;
9898 			compatible = "fixed-clock";
9999 			clock-frequency = <24000000>;
100100 			clock-output-names = "osc24M";
101101 		};
102102 
103
-		osc32k: clk@0 {
103
+		osc32k: clk-32k {
104104 			#clock-cells = <0>;
105105 			compatible = "fixed-clock";
106106 			clock-frequency = <32768>;
....@@ -108,10 +108,26 @@
108108 		};
109109 	};
110110 
111
-	soc@1c00000 {
111
+	reserved-memory {
112
+		#address-cells = <1>;
113
+		#size-cells = <1>;
114
+		ranges;
115
+
116
+		/* Address must be kept in the lower 256 MiBs of DRAM for VE. */
117
+		default-pool {
118
+			compatible = "shared-dma-pool";
119
+			size = <0x6000000>;
120
+			alloc-ranges = <0x40000000 0x10000000>;
121
+			reusable;
122
+			linux,cma-default;
123
+		};
124
+	};
125
+
126
+	soc {
112127 		compatible = "simple-bus";
113128 		#address-cells = <1>;
114129 		#size-cells = <1>;
130
+		dma-ranges;
115131 		ranges;
116132 
117133 		system-control@1c00000 {
....@@ -166,6 +182,16 @@
166182 			};
167183 		};
168184 
185
+		mbus: dram-controller@1c01000 {
186
+			compatible = "allwinner,sun5i-a13-mbus";
187
+			reg = <0x01c01000 0x1000>;
188
+			clocks = <&ccu CLK_MBUS>;
189
+			#address-cells = <1>;
190
+			#size-cells = <1>;
191
+			dma-ranges = <0x00000000 0x40000000 0x20000000>;
192
+			#interconnect-cells = <1>;
193
+		};
194
+
169195 		dma: dma-controller@1c02000 {
170196 			compatible = "allwinner,sun4i-a10-dma";
171197 			reg = <0x01c02000 0x1000>;
....@@ -174,7 +200,7 @@
174200 			#dma-cells = <2>;
175201 		};
176202 
177
-		nfc: nand@1c03000 {
203
+		nfc: nand-controller@1c03000 {
178204 			compatible = "allwinner,sun4i-a10-nand";
179205 			reg = <0x01c03000 0x1000>;
180206 			interrupts = <37>;
....@@ -223,11 +249,8 @@
223249 			status = "disabled";
224250 
225251 			port {
226
-				#address-cells = <1>;
227
-				#size-cells = <0>;
228252 
229
-				tve0_in_tcon0: endpoint@0 {
230
-					reg = <0>;
253
+				tve0_in_tcon0: endpoint {
231254 					remote-endpoint = <&tcon0_out_tve0>;
232255 				};
233256 			};
....@@ -254,6 +277,7 @@
254277 			compatible = "allwinner,sun5i-a13-tcon";
255278 			reg = <0x01c0c000 0x1000>;
256279 			interrupts = <44>;
280
+			dmas = <&dma SUN4I_DMA_DEDICATED 14>;
257281 			resets = <&ccu RST_LCD>;
258282 			reset-names = "lcd";
259283 			clocks = <&ccu CLK_AHB_LCD>,
....@@ -263,6 +287,7 @@
263287 				      "tcon-ch0",
264288 				      "tcon-ch1";
265289 			clock-output-names = "tcon-pixel-clock";
290
+			#clock-cells = <0>;
266291 			status = "disabled";
267292 
268293 			ports {
....@@ -270,12 +295,9 @@
270295 				#size-cells = <0>;
271296 
272297 				tcon0_in: port@0 {
273
-					#address-cells = <1>;
274
-					#size-cells = <0>;
275298 					reg = <0>;
276299 
277
-					tcon0_in_be0: endpoint@0 {
278
-						reg = <0>;
300
+					tcon0_in_be0: endpoint {
279301 						remote-endpoint = <&be0_out_tcon0>;
280302 					};
281303 				};
....@@ -294,12 +316,25 @@
294316 			};
295317 		};
296318 
319
+		video-codec@1c0e000 {
320
+			compatible = "allwinner,sun5i-a13-video-engine";
321
+			reg = <0x01c0e000 0x1000>;
322
+			clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>,
323
+				 <&ccu CLK_DRAM_VE>;
324
+			clock-names = "ahb", "mod", "ram";
325
+			resets = <&ccu RST_VE>;
326
+			interrupts = <53>;
327
+			allwinner,sram = <&ve_sram 1>;
328
+		};
329
+
297330 		mmc0: mmc@1c0f000 {
298331 			compatible = "allwinner,sun5i-a13-mmc";
299332 			reg = <0x01c0f000 0x1000>;
300333 			clocks = <&ccu CLK_AHB_MMC0>, <&ccu CLK_MMC0>;
301334 			clock-names = "ahb", "mmc";
302335 			interrupts = <32>;
336
+			pinctrl-names = "default";
337
+			pinctrl-0 = <&mmc0_pins>;
303338 			status = "disabled";
304339 			#address-cells = <1>;
305340 			#size-cells = <0>;
....@@ -337,13 +372,14 @@
337372 			phy-names = "usb";
338373 			extcon = <&usbphy 0>;
339374 			allwinner,sram = <&otg_sram 1>;
375
+			dr_mode = "otg";
340376 			status = "disabled";
341377 		};
342378 
343379 		usbphy: phy@1c13400 {
344380 			#phy-cells = <1>;
345381 			compatible = "allwinner,sun5i-a13-usb-phy";
346
-			reg = <0x01c13400 0x10 0x01c14800 0x4>;
382
+			reg = <0x01c13400 0x10>, <0x01c14800 0x4>;
347383 			reg-names = "phy_ctrl", "pmu1";
348384 			clocks = <&ccu CLK_USB_PHY0>;
349385 			clock-names = "usb_phy";
....@@ -420,7 +456,7 @@
420456 			#interrupt-cells = <3>;
421457 			#gpio-cells = <3>;
422458 
423
-			emac_pins_a: emac0@0 {
459
+			emac_pd_pins: emac-pd-pins {
424460 				pins = "PD6", "PD7", "PD10",
425461 				       "PD11", "PD12", "PD13", "PD14",
426462 				       "PD15", "PD18", "PD19", "PD20",
....@@ -429,27 +465,27 @@
429465 				function = "emac";
430466 			};
431467 
432
-			i2c0_pins_a: i2c0@0 {
468
+			i2c0_pins: i2c0-pins {
433469 				pins = "PB0", "PB1";
434470 				function = "i2c0";
435471 			};
436472 
437
-			i2c1_pins_a: i2c1@0 {
473
+			i2c1_pins: i2c1-pins {
438474 				pins = "PB15", "PB16";
439475 				function = "i2c1";
440476 			};
441477 
442
-			i2c2_pins_a: i2c2@0 {
478
+			i2c2_pins: i2c2-pins {
443479 				pins = "PB17", "PB18";
444480 				function = "i2c2";
445481 			};
446482 
447
-			ir0_rx_pins_a: ir0@0 {
483
+			ir0_rx_pin: ir0-rx-pin {
448484 				pins = "PB4";
449485 				function = "ir0";
450486 			};
451487 
452
-			lcd_rgb565_pins: lcd_rgb565@0 {
488
+			lcd_rgb565_pins: lcd-rgb565-pins {
453489 				pins = "PD3", "PD4", "PD5", "PD6", "PD7",
454490 						 "PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
455491 						 "PD19", "PD20", "PD21", "PD22", "PD23",
....@@ -457,7 +493,7 @@
457493 				function = "lcd0";
458494 			};
459495 
460
-			lcd_rgb666_pins: lcd_rgb666@0 {
496
+			lcd_rgb666_pins: lcd-rgb666-pins {
461497 				pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
462498 				       "PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
463499 				       "PD18", "PD19", "PD20", "PD21", "PD22", "PD23",
....@@ -465,7 +501,7 @@
465501 				function = "lcd0";
466502 			};
467503 
468
-			mmc0_pins_a: mmc0@0 {
504
+			mmc0_pins: mmc0-pins {
469505 				pins = "PF0", "PF1", "PF2", "PF3",
470506 				       "PF4", "PF5";
471507 				function = "mmc0";
....@@ -473,7 +509,15 @@
473509 				bias-pull-up;
474510 			};
475511 
476
-			mmc2_pins_a: mmc2@0 {
512
+			mmc2_4bit_pc_pins: mmc2-4bit-pc-pins {
513
+				pins = "PC6", "PC7", "PC8", "PC9",
514
+				       "PC10", "PC11";
515
+				function = "mmc2";
516
+				drive-strength = <30>;
517
+				bias-pull-up;
518
+			};
519
+
520
+			mmc2_8bit_pins: mmc2-8bit-pins {
477521 				pins = "PC6", "PC7", "PC8", "PC9",
478522 				       "PC10", "PC11", "PC12", "PC13",
479523 				       "PC14", "PC15";
....@@ -482,15 +526,7 @@
482526 				bias-pull-up;
483527 			};
484528 
485
-			mmc2_4bit_pins_a: mmc2-4bit@0 {
486
-				pins = "PC6", "PC7", "PC8", "PC9",
487
-				       "PC10", "PC11";
488
-				function = "mmc2";
489
-				drive-strength = <30>;
490
-				bias-pull-up;
491
-			};
492
-
493
-			nand_pins_a: nand-base0@0 {
529
+			nand_pins: nand-pins {
494530 				pins = "PC0", "PC1", "PC2",
495531 				       "PC5", "PC8", "PC9", "PC10",
496532 				       "PC11", "PC12", "PC13", "PC14",
....@@ -498,72 +534,79 @@
498534 				function = "nand0";
499535 			};
500536 
501
-			nand_cs0_pins_a: nand-cs@0 {
537
+			nand_cs0_pin: nand-cs0-pin {
502538 				pins = "PC4";
503539 				function = "nand0";
504540 			};
505541 
506
-			nand_rb0_pins_a: nand-rb@0 {
542
+			nand_rb0_pin: nand-rb0-pin {
507543 				pins = "PC6";
508544 				function = "nand0";
509545 			};
510546 
511
-			spi2_pins_a: spi2@0 {
547
+			pwm0_pin: pwm0-pin {
548
+				pins = "PB2";
549
+				function = "pwm";
550
+			};
551
+
552
+			spi2_pe_pins: spi2-pe-pins {
512553 				pins = "PE1", "PE2", "PE3";
513554 				function = "spi2";
514555 			};
515556 
516
-			spi2_cs0_pins_a: spi2-cs0@0 {
557
+			spi2_cs0_pe_pin: spi2-cs0-pe-pin {
517558 				pins = "PE0";
518559 				function = "spi2";
519560 			};
520561 
521
-			uart1_pins_a: uart1@0 {
562
+			uart1_pe_pins: uart1-pe-pins {
522563 				pins = "PE10", "PE11";
523564 				function = "uart1";
524565 			};
525566 
526
-			uart1_pins_b: uart1@1 {
567
+			uart1_pg_pins: uart1-pg-pins {
527568 				pins = "PG3", "PG4";
528569 				function = "uart1";
529570 			};
530571 
531
-			uart2_pins_a: uart2@0 {
572
+			uart2_pd_pins: uart2-pd-pins {
532573 				pins = "PD2", "PD3";
533574 				function = "uart2";
534575 			};
535576 
536
-			uart2_cts_rts_pins_a: uart2-cts-rts@0 {
577
+			uart2_cts_rts_pd_pins: uart2-cts-rts-pd-pins {
537578 				pins = "PD4", "PD5";
538579 				function = "uart2";
539580 			};
540581 
541
-			uart3_pins_a: uart3@0 {
582
+			uart3_pg_pins: uart3-pg-pins {
542583 				pins = "PG9", "PG10";
543584 				function = "uart3";
544585 			};
545586 
546
-			uart3_cts_rts_pins_a: uart3-cts-rts@0 {
587
+			uart3_cts_rts_pg_pins: uart3-cts-rts-pg-pins {
547588 				pins = "PG11", "PG12";
548589 				function = "uart3";
549
-			};
550
-
551
-			pwm0_pins: pwm0 {
552
-				pins = "PB2";
553
-				function = "pwm";
554590 			};
555591 		};
556592 
557593 		timer@1c20c00 {
558594 			compatible = "allwinner,sun4i-a10-timer";
559595 			reg = <0x01c20c00 0x90>;
560
-			interrupts = <22>;
596
+			interrupts = <22>,
597
+				     <23>,
598
+				     <24>,
599
+				     <25>,
600
+				     <67>,
601
+				     <68>;
561602 			clocks = <&ccu CLK_HOSC>;
562603 		};
563604 
564605 		wdt: watchdog@1c20c90 {
565606 			compatible = "allwinner,sun4i-a10-wdt";
566607 			reg = <0x01c20c90 0x10>;
608
+			interrupts = <24>;
609
+			clocks = <&osc24M>;
567610 		};
568611 
569612 		ir0: ir@1c21800 {
....@@ -652,6 +695,8 @@
652695 			reg = <0x01c2ac00 0x400>;
653696 			interrupts = <7>;
654697 			clocks = <&ccu CLK_APB1_I2C0>;
698
+			pinctrl-names = "default";
699
+			pinctrl-0 = <&i2c0_pins>;
655700 			status = "disabled";
656701 			#address-cells = <1>;
657702 			#size-cells = <0>;
....@@ -662,6 +707,8 @@
662707 			reg = <0x01c2b000 0x400>;
663708 			interrupts = <8>;
664709 			clocks = <&ccu CLK_APB1_I2C1>;
710
+			pinctrl-names = "default";
711
+			pinctrl-0 = <&i2c1_pins>;
665712 			status = "disabled";
666713 			#address-cells = <1>;
667714 			#size-cells = <0>;
....@@ -672,6 +719,8 @@
672719 			reg = <0x01c2b400 0x400>;
673720 			interrupts = <9>;
674721 			clocks = <&ccu CLK_APB1_I2C2>;
722
+			pinctrl-names = "default";
723
+			pinctrl-0 = <&i2c2_pins>;
675724 			status = "disabled";
676725 			#address-cells = <1>;
677726 			#size-cells = <0>;
....@@ -693,6 +742,8 @@
693742 			clock-names = "ahb", "mod",
694743 				      "ram";
695744 			resets = <&ccu RST_DE_FE>;
745
+			interconnects = <&mbus 19>;
746
+			interconnect-names = "dma-mem";
696747 			status = "disabled";
697748 
698749 			ports {
....@@ -700,12 +751,9 @@
700751 				#size-cells = <0>;
701752 
702753 				fe0_out: port@1 {
703
-					#address-cells = <1>;
704
-					#size-cells = <0>;
705754 					reg = <1>;
706755 
707
-					fe0_out_be0: endpoint@0 {
708
-						reg = <0>;
756
+					fe0_out_be0: endpoint {
709757 						remote-endpoint = <&be0_in_fe0>;
710758 					};
711759 				};
....@@ -721,33 +769,26 @@
721769 			clock-names = "ahb", "mod",
722770 				      "ram";
723771 			resets = <&ccu RST_DE_BE>;
772
+			interconnects = <&mbus 18>;
773
+			interconnect-names = "dma-mem";
724774 			status = "disabled";
725
-
726
-			assigned-clocks = <&ccu CLK_DE_BE>;
727
-			assigned-clock-rates = <300000000>;
728775 
729776 			ports {
730777 				#address-cells = <1>;
731778 				#size-cells = <0>;
732779 
733780 				be0_in: port@0 {
734
-					#address-cells = <1>;
735
-					#size-cells = <0>;
736781 					reg = <0>;
737782 
738
-					be0_in_fe0: endpoint@0 {
739
-						reg = <0>;
783
+					be0_in_fe0: endpoint {
740784 						remote-endpoint = <&fe0_out_be0>;
741785 					};
742786 				};
743787 
744788 				be0_out: port@1 {
745
-					#address-cells = <1>;
746
-					#size-cells = <0>;
747789 					reg = <1>;
748790 
749
-					be0_out_tcon0: endpoint@0 {
750
-						reg = <0>;
791
+					be0_out_tcon0: endpoint {
751792 						remote-endpoint = <&tcon0_in_be0>;
752793 					};
753794 				};