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2024-10-22 8ac6c7a54ed1b98d142dce24b11c6de6a1e239a5 
 kernel/arch/arm/boot/dts/am3517.dtsi
....@@ -1,7 +1,7 @@
11 /*
22  * Device Tree Source for am3517 SoC
33  *
4
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
4
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
55  *
66  * This file is licensed under the terms of the GNU General Public License
77  * version 2.  This program is licensed "as is" without any warranty of any
....@@ -10,10 +10,45 @@
1010 
1111 #include "omap3.dtsi"
1212 
13
+/* AM3517 doesn't appear to have the crypto engines defined in omap3.dtsi */
14
+/delete-node/ &aes1_target;
15
+/delete-node/ &aes2_target;
16
+
1317 / {
1418 	aliases {
1519 		serial3 = &uart4;
1620 		can = &hecc;
21
+	};
22
+
23
+	cpus {
24
+		cpu: cpu@0 {
25
+			/* Based on OMAP3630 variants OPP50 and OPP100 */
26
+			operating-points-v2 = <&cpu0_opp_table>;
27
+
28
+			clock-latency = <300000>; /* From legacy driver */
29
+		};
30
+	};
31
+
32
+	cpu0_opp_table: opp-table {
33
+		compatible = "operating-points-v2-ti-cpu";
34
+		syscon = <&scm_conf>;
35
+		/*
36
+		 * AM3517 TRM only lists 600MHz @ 1.2V, but omap36xx
37
+		 * appear to operate at 300MHz as well. Since AM3517 only
38
+		 * lists one operating voltage, it will remain fixed at 1.2V
39
+		 */
40
+		opp50-300000000 {
41
+			opp-hz = /bits/ 64 <300000000>;
42
+			opp-microvolt = <1200000>;
43
+			opp-supported-hw = <0xffffffff 0xffffffff>;
44
+			opp-suspend;
45
+		};
46
+
47
+		opp100-600000000 {
48
+			opp-hz = /bits/ 64 <600000000>;
49
+			opp-microvolt = <1200000>;
50
+			opp-supported-hw = <0xffffffff 0xffffffff>;
51
+		};
1752 	};
1853 
1954 	ocp@68000000 {
....@@ -43,7 +78,7 @@
4378 			clock-names = "ick";
4479 		};
4580 
46
-		davinci_mdio: ethernet@5c030000 {
81
+		davinci_mdio: mdio@5c030000 {
4782 			compatible = "ti,davinci_mdio";
4883 			ti,hwmods = "davinci_mdio";
4984 			status = "disabled";
....@@ -88,7 +123,37 @@
88123 			interrupts = <24>;
89124 			clocks = <&hecc_ck>;
90125 		};
126
+
127
+		/*
128
+		 * On am3517 the OCP registers do not seem to be accessible
129
+		 * similar to the omap34xx. Maybe SGX is permanently set to
130
+		 * "OCP bypass mode", or maybe there is OCP_SYSCONFIG that is
131
+		 * write-only at 0x50000e10. We detect SGX based on the SGX
132
+		 * revision register instead of the unreadable OCP revision
133
+		 * register.
134
+		 */
135
+		sgx_module: target-module@50000000 {
136
+			compatible = "ti,sysc-omap2", "ti,sysc";
137
+			reg = <0x50000014 0x4>;
138
+			reg-names = "rev";
139
+			clocks = <&sgx_fck>, <&sgx_ick>;
140
+			clock-names = "fck", "ick";
141
+			#address-cells = <1>;
142
+			#size-cells = <1>;
143
+			ranges = <0 0x50000000 0x4000>;
144
+
145
+			/*
146
+			 * Closed source PowerVR driver, no child device
147
+			 * binding or driver in mainline
148
+			 */
149
+		};
91150 	};
151
+};
152
+
153
+/* Not currently working, probably needs at least different clocks */
154
+&rng_target {
155
+	status = "disabled";
156
+	/delete-property/ clocks;
92157 };
93158 
94159 /* Table Table 5-79 of the TRM shows 480ab000 is reserved */
....@@ -108,5 +173,25 @@
108173 	status = "disabled";
109174 };
110175 
111
-/include/ "am35xx-clocks.dtsi"
112
-/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
176
+#include "am35xx-clocks.dtsi"
177
+#include "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
178
+
179
+/* Preferred always-on timer for clocksource */
180
+&timer1_target {
181
+	ti,no-reset-on-init;
182
+	ti,no-idle;
183
+	timer@0 {
184
+		assigned-clocks = <&gpt1_fck>;
185
+		assigned-clock-parents = <&sys_ck>;
186
+	};
187
+};
188
+
189
+/* Preferred timer for clockevent */
190
+&timer2_target {
191
+	ti,no-reset-on-init;
192
+	ti,no-idle;
193
+	timer@0 {
194
+		assigned-clocks = <&gpt2_fck>;
195
+		assigned-clock-parents = <&sys_ck>;
196
+	};
197
+};