| .. | .. |
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| 29 | 29 | - vdda-pll-max-microamp : specifies max. load that can be drawn from pll supply |
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| 30 | 30 | - vddp-ref-clk-supply : phandle to UFS device ref_clk pad power supply |
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| 31 | 31 | - vddp-ref-clk-max-microamp : specifies max. load that can be drawn from this supply |
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| 32 | +- resets : specifies the PHY reset in the UFS controller |
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| 32 | 33 | |
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| 33 | 34 | Example: |
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| 34 | 35 | |
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| .. | .. |
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| 51 | 52 | <&clock_gcc clk_ufs_phy_ldo>, |
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| 52 | 53 | <&clock_gcc clk_gcc_ufs_tx_cfg_clk>, |
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| 53 | 54 | <&clock_gcc clk_gcc_ufs_rx_cfg_clk>; |
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| 55 | + resets = <&ufshc 0>; |
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| 54 | 56 | }; |
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| 55 | 57 | |
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| 56 | | - ufshc@fc598000 { |
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| 58 | + ufshc: ufshc@fc598000 { |
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| 59 | + #reset-cells = <1>; |
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| 57 | 60 | ... |
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| 58 | 61 | phys = <&ufsphy1>; |
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| 59 | 62 | phy-names = "ufsphy"; |
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