| .. | .. |
|---|
| 1 | 1 | ARM Freescale DSPI controller |
|---|
| 2 | 2 | |
|---|
| 3 | 3 | Required properties: |
|---|
| 4 | | -- compatible : "fsl,vf610-dspi", "fsl,ls1021a-v1.0-dspi", |
|---|
| 5 | | - "fsl,ls2085a-dspi" |
|---|
| 6 | | - or |
|---|
| 7 | | - "fsl,ls2080a-dspi" followed by "fsl,ls2085a-dspi" |
|---|
| 8 | | - "fsl,ls1012a-dspi" followed by "fsl,ls1021a-v1.0-dspi" |
|---|
| 4 | +- compatible : must be one of: |
|---|
| 5 | + "fsl,vf610-dspi", |
|---|
| 6 | + "fsl,ls1021a-v1.0-dspi", |
|---|
| 7 | + "fsl,ls1012a-dspi" (optionally followed by "fsl,ls1021a-v1.0-dspi"), |
|---|
| 8 | + "fsl,ls1028a-dspi", |
|---|
| 9 | + "fsl,ls1043a-dspi" (optionally followed by "fsl,ls1021a-v1.0-dspi"), |
|---|
| 10 | + "fsl,ls1046a-dspi" (optionally followed by "fsl,ls1021a-v1.0-dspi"), |
|---|
| 11 | + "fsl,ls1088a-dspi" (optionally followed by "fsl,ls1021a-v1.0-dspi"), |
|---|
| 12 | + "fsl,ls2080a-dspi" (optionally followed by "fsl,ls2085a-dspi"), |
|---|
| 13 | + "fsl,ls2085a-dspi", |
|---|
| 14 | + "fsl,lx2160a-dspi", |
|---|
| 9 | 15 | - reg : Offset and length of the register set for the device |
|---|
| 10 | 16 | - interrupts : Should contain SPI controller interrupt |
|---|
| 11 | 17 | - clocks: from common clock binding: handle to dspi clock. |
|---|
| .. | .. |
|---|
| 13 | 19 | - pinctrl-0: pin control group to be used for this controller. |
|---|
| 14 | 20 | - pinctrl-names: must contain a "default" entry. |
|---|
| 15 | 21 | - spi-num-chipselects : the number of the chipselect signals. |
|---|
| 16 | | -- bus-num : the slave chip chipselect signal number. |
|---|
| 17 | 22 | |
|---|
| 18 | 23 | Optional property: |
|---|
| 19 | 24 | - big-endian: If present the dspi device's registers are implemented |
|---|
| 20 | 25 | in big endian mode. |
|---|
| 26 | +- bus-num : the slave chip chipselect signal number. |
|---|
| 21 | 27 | |
|---|
| 22 | 28 | Optional SPI slave node properties: |
|---|
| 23 | 29 | - fsl,spi-cs-sck-delay: a delay in nanoseconds between activating chip |
|---|