| .. | .. |
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| 2 | 2 | |
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| 3 | 3 | Required properties: |
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| 4 | 4 | - compatible: 'amlogic,axg-tdmin' or |
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| 5 | | - 'amlogic,axg-tdmout' |
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| 5 | + 'amlogic,axg-tdmout' or |
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| 6 | + 'amlogic,g12a-tdmin' or |
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| 7 | + 'amlogic,g12a-tdmout' or |
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| 8 | + 'amlogic,sm1-tdmin' or |
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| 9 | + 'amlogic,sm1-tdmout |
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| 6 | 10 | - reg: physical base address of the controller and length of memory |
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| 7 | 11 | mapped region. |
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| 8 | 12 | - clocks: list of clock phandle, one for each entry clock-names. |
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| .. | .. |
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| 13 | 17 | * "lrclk" : sample clock |
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| 14 | 18 | * "lrclk_sel": sample clock input multiplexer |
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| 15 | 19 | |
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| 16 | | -Example of TDMOUT_A on the A113 SoC: |
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| 20 | +Optional property: |
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| 21 | +- resets: phandle to the dedicated reset line of the tdm formatter. |
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| 22 | + |
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| 23 | +Example of TDMOUT_A on the S905X2 SoC: |
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| 17 | 24 | |
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| 18 | 25 | tdmout_a: audio-controller@500 { |
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| 19 | 26 | compatible = "amlogic,axg-tdmout"; |
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| 20 | 27 | reg = <0x0 0x500 0x0 0x40>; |
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| 28 | + resets = <&clkc_audio AUD_RESET_TDMOUT_A>; |
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| 21 | 29 | clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>, |
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| 22 | 30 | <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>, |
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| 23 | 31 | <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>, |
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