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| 1 | 1 | ADI AXI-I2S controller |
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| 2 | 2 | |
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| 3 | +The core can be generated with transmit (playback), only receive |
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| 4 | +(capture) or both directions enabled. |
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| 5 | + |
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| 3 | 6 | Required properties: |
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| 4 | 7 | - compatible : Must be "adi,axi-i2s-1.00.a" |
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| 5 | 8 | - reg : Must contain I2S core's registers location and length |
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| .. | .. |
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| 9 | 12 | - clock-names : "axi" for the clock to the AXI interface, "ref" for the sample |
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| 10 | 13 | rate reference clock. |
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| 11 | 14 | - dmas: Pairs of phandle and specifier for the DMA channels that are used by |
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| 12 | | - the core. The core expects two dma channels, one for transmit and one for |
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| 13 | | - receive. |
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| 15 | + the core. The core expects two dma channels if both transmit and receive are |
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| 16 | + enabled, one channel otherwise. |
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| 14 | 17 | - dma-names : "tx" for the transmit channel, "rx" for the receive channel. |
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| 15 | 18 | |
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| 16 | 19 | For more details on the 'dma', 'dma-names', 'clock' and 'clock-names' properties |
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