修改4g拨号为QMI,需要在系统里后台执行quectel-CM

hc

2024-10-22 8ac6c7a54ed1b98d142dce24b11c6de6a1e239a5

 kernel/Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt
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@@ -7,55 +7,47 @@
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 This binding doc is only for the IOMUXC1 support in A7 Domain and it only
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 supports generic pin config.
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-Please also refer pinctrl-bindings.txt in this directory for generic pinctrl
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-binding.
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-
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-=== Pin Controller Node ===
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+Please refer to fsl,imx-pinctrl.txt in this directory for common binding
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+part and usage.
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 Required properties:
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-- compatible:	"fsl,imx7ulp-iomuxc1"
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-- reg:		Should contain the base physical address and size of the iomuxc
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-		registers.
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+- compatible:	"fsl,imx7ulp-iomuxc1".
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+- fsl,pins:	Each entry consists of 5 integers which represents the mux
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+		and config setting for one pin. The first 4 integers
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+		<mux_conf_reg input_reg mux_mode input_val> are specified
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+		using a PIN_FUNC_ID macro, which can be found in
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+		imx7ulp-pinfunc.h in the device tree source folder.
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+		The last integer CONFIG is the pad setting value like
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+		pull-up on this pin.
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-=== Pin Configuration Node ===
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-- pinmux: One integers array, represents a group of pins mux setting.
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-	The format is pinmux = <PIN_FUNC_ID>, PIN_FUNC_ID is a pin working on
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-	a specific function.
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+		Please refer to i.MX7ULP Reference Manual for detailed
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+		CONFIG settings.
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-	NOTE: i.MX7ULP PIN_FUNC_ID consists of 4 integers as it shares one mux
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-	and config register as follows:
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-	<mux_conf_reg input_reg mux_mode input_val>
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-
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-	Refer to imx7ulp-pinfunc.h in in device tree source folder for all
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-	available imx7ulp PIN_FUNC_ID.
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-
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-Optional Properties:
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-- drive-strength		Integer. Controls Drive Strength
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-					0: Standard
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-					1: Hi Driver
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-- drive-push-pull		Bool. Enable Pin Push-pull
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-- drive-open-drain		Bool. Enable Pin Open-drian
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-- slew-rate:			Integer. Controls Slew Rate
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-					0: Standard
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-					1: Slow
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-- bias-disable:			Bool. Pull disabled
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-- bias-pull-down:		Bool. Pull down on pin
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-- bias-pull-up:			Bool. Pull up on pin
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+CONFIG bits definition:
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+PAD_CTL_OBE		(1 << 17)
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+PAD_CTL_IBE		(1 << 16)
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+PAD_CTL_LK		(1 << 16)
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+PAD_CTL_DSE_HI		(1 << 6)
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+PAD_CTL_DSE_STD		(0 << 6)
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+PAD_CTL_ODE		(1 << 5)
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+PAD_CTL_PUSH_PULL	(0 << 5)
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+PAD_CTL_SRE_SLOW	(1 << 2)
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+PAD_CTL_SRE_STD		(0 << 2)
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+PAD_CTL_PE		(1 << 0)
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 Examples:
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 #include "imx7ulp-pinfunc.h"
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 /* Pin Controller Node */
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-iomuxc1: iomuxc@40ac0000 {
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+iomuxc1: pinctrl@40ac0000 {
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 	compatible = "fsl,imx7ulp-iomuxc1";
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 	reg = <0x40ac0000 0x1000>;
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 	/* Pin Configuration Node */
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 	pinctrl_lpuart4: lpuart4grp {
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-		pinmux = <
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-			IMX7ULP_PAD_PTC3__LPUART4_RX
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-			IMX7ULP_PAD_PTC2__LPUART4_TX
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+		fsl,pins = <
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+			IMX7ULP_PAD_PTC3__LPUART4_RX	0x1
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+			IMX7ULP_PAD_PTC2__LPUART4_TX	0x1
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 		>;
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-		bias-pull-up;
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 	};
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 };