~hc/RK356X_SDK_RELEASE.git

..	..	@@ -13,10 +13,16 @@
13	13	"mediatek,mt8173-u3phy";
14	14	make use of "mediatek,generic-tphy-v1" on mt2701 instead and
15	15	"mediatek,generic-tphy-v2" on mt2712 instead.
16		- - clocks : (deprecated, use port's clocks instead) a list of phandle +
17		- clock-specifier pairs, one for each entry in clock-names
18		- - clock-names : (deprecated, use port's one instead) must contain
19		- "u3phya_ref": for reference clock of usb3.0 analog phy.
	16	+
	17	+- #address-cells: the number of cells used to represent physical
	18	+ base addresses.
	19	+- #size-cells: the number of cells used to represent the size of an address.
	20	+- ranges: the address mapping relationship to the parent, defined with
	21	+ - empty value: if optional 'reg' is used.
	22	+ - non-empty value: if optional 'reg' is not used. should set
	23	+ the child's base address to 0, the physical address
	24	+ within parent's address space, and the length of
	25	+ the address map.
20	26
21	27	Required nodes : a sub-node is required for each port the controller
22	28	provides. Address range information including the usual
..	..	@@ -34,12 +40,6 @@
34	40
35	41	Required properties (port (child) node):
36	42	- reg : address and length of the register set for the port.
37		-- clocks : a list of phandle + clock-specifier pairs, one for each
38		- entry in clock-names
39		-- clock-names : must contain
40		- "ref": 48M reference clock for HighSpeed analog phy; and 26M
41		- reference clock for SuperSpeed analog phy, sometimes is
42		- 24M, 25M or 27M, depended on platform.
43	43	- #phy-cells : should be 1 (See second example)
44	44	cell after port phandle is phy type from:
45	45	- PHY_TYPE_USB2
..	..	@@ -48,10 +48,22 @@
48	48	- PHY_TYPE_SATA
49	49
50	50	Optional properties (PHY_TYPE_USB2 port (child) node):
	51	+- clocks : a list of phandle + clock-specifier pairs, one for each
	52	+ entry in clock-names
	53	+- clock-names : may contain
	54	+ "ref": 48M reference clock for HighSpeed (digital) phy; and 26M
	55	+ reference clock for SuperSpeed (digital) phy, sometimes is
	56	+ 24M, 25M or 27M, depended on platform.
	57	+ "da_ref": the reference clock of analog phy, used if the clocks
	58	+ of analog and digital phys are separated, otherwise uses
	59	+ "ref" clock only if needed.
	60	+
51	61	- mediatek,eye-src : u32, the value of slew rate calibrate
52	62	- mediatek,eye-vrt : u32, the selection of VRT reference voltage
53	63	- mediatek,eye-term : u32, the selection of HS_TX TERM reference voltage
54	64	- mediatek,bc12 : bool, enable BC12 of u2phy if support it
	65	+- mediatek,discth : u32, the selection of disconnect threshold
	66	+- mediatek,intr : u32, the selection of internal R (resistance)
55	67
56	68	Example:
57	69