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| 1 | 1 | Broadcom STB USB PHY |
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| 2 | 2 | |
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| 3 | 3 | Required properties: |
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| 4 | | - - compatible: brcm,brcmstb-usb-phy |
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| 5 | | - - reg: two offset and length pairs. |
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| 6 | | - The first pair specifies a manditory set of memory mapped |
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| 7 | | - registers used for general control of the PHY. |
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| 8 | | - The second pair specifies optional registers used by some of |
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| 9 | | - the SoCs that support USB 3.x |
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| 10 | | - - #phy-cells: Shall be 1 as it expects one argument for setting |
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| 11 | | - the type of the PHY. Possible values are: |
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| 12 | | - - PHY_TYPE_USB2 for USB1.1/2.0 PHY |
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| 13 | | - - PHY_TYPE_USB3 for USB3.x PHY |
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| 4 | +- compatible: should be one of |
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| 5 | + "brcm,brcmstb-usb-phy" |
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| 6 | + "brcm,bcm7216-usb-phy" |
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| 7 | + "brcm,bcm7211-usb-phy" |
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| 8 | + |
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| 9 | +- reg and reg-names properties requirements are specific to the |
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| 10 | + compatible string. |
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| 11 | + "brcm,brcmstb-usb-phy": |
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| 12 | + - reg: 1 or 2 offset and length pairs. One for the base CTRL registers |
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| 13 | + and an optional pair for systems with USB 3.x support |
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| 14 | + - reg-names: not specified |
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| 15 | + "brcm,bcm7216-usb-phy": |
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| 16 | + - reg: 3 offset and length pairs for CTRL, XHCI_EC and XHCI_GBL |
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| 17 | + registers |
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| 18 | + - reg-names: "ctrl", "xhci_ec", "xhci_gbl" |
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| 19 | + "brcm,bcm7211-usb-phy": |
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| 20 | + - reg: 5 offset and length pairs for CTRL, XHCI_EC, XHCI_GBL, |
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| 21 | + USB_PHY and USB_MDIO registers and an optional pair |
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| 22 | + for the BDC registers |
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| 23 | + - reg-names: "ctrl", "xhci_ec", "xhci_gbl", "usb_phy", "usb_mdio", "bdc_ec" |
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| 24 | + |
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| 25 | +- #phy-cells: Shall be 1 as it expects one argument for setting |
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| 26 | + the type of the PHY. Possible values are: |
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| 27 | + - PHY_TYPE_USB2 for USB1.1/2.0 PHY |
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| 28 | + - PHY_TYPE_USB3 for USB3.x PHY |
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| 14 | 29 | |
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| 15 | 30 | Optional Properties: |
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| 16 | 31 | - clocks : clock phandles. |
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| 17 | 32 | - clock-names: String, clock name. |
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| 33 | +- interrupts: wakeup interrupt |
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| 34 | +- interrupt-names: "wakeup" |
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| 18 | 35 | - brcm,ipp: Boolean, Invert Port Power. |
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| 19 | 36 | Possible values are: 0 (Don't invert), 1 (Invert) |
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| 20 | 37 | - brcm,ioc: Boolean, Invert Over Current detection. |
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| 21 | 38 | Possible values are: 0 (Don't invert), 1 (Invert) |
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| 22 | | -NOTE: one or both of the following two properties must be set |
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| 23 | | -- brcm,has-xhci: Boolean indicating the phy has an XHCI phy. |
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| 24 | | -- brcm,has-eohci: Boolean indicating the phy has an EHCI/OHCI phy. |
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| 25 | 39 | - dr_mode: String, PHY Device mode. |
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| 26 | 40 | Possible values are: "host", "peripheral ", "drd" or "typec-pd" |
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| 27 | 41 | If this property is not defined, the phy will default to "host" mode. |
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| 42 | +- brcm,syscon-piarbctl: phandle to syscon for handling config registers |
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| 43 | +NOTE: one or both of the following two properties must be set |
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| 44 | +- brcm,has-xhci: Boolean indicating the phy has an XHCI phy. |
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| 45 | +- brcm,has-eohci: Boolean indicating the phy has an EHCI/OHCI phy. |
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| 46 | + |
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| 28 | 47 | |
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| 29 | 48 | Example: |
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| 30 | 49 | |
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| .. | .. |
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| 41 | 60 | clocks = <&usb20>, <&usb30>; |
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| 42 | 61 | clock-names = "sw_usb", "sw_usb3"; |
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| 43 | 62 | }; |
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| 63 | + |
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| 64 | +usb-phy@29f0200 { |
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| 65 | + reg = <0x29f0200 0x200>, |
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| 66 | + <0x29c0880 0x30>, |
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| 67 | + <0x29cc100 0x534>, |
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| 68 | + <0x2808000 0x24>, |
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| 69 | + <0x2980080 0x8>; |
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| 70 | + reg-names = "ctrl", |
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| 71 | + "xhci_ec", |
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| 72 | + "xhci_gbl", |
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| 73 | + "usb_phy", |
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| 74 | + "usb_mdio"; |
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| 75 | + brcm,ioc = <0x0>; |
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| 76 | + brcm,ipp = <0x0>; |
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| 77 | + compatible = "brcm,bcm7211-usb-phy"; |
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| 78 | + interrupts = <0x30>; |
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| 79 | + interrupt-parent = <&vpu_intr1_nosec_intc>; |
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| 80 | + interrupt-names = "wake"; |
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| 81 | + #phy-cells = <0x1>; |
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| 82 | + brcm,has-xhci; |
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| 83 | + syscon-piarbctl = <&syscon_piarbctl>; |
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| 84 | + clocks = <&scmi_clk 256>; |
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| 85 | + clock-names = "sw_usb"; |
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| 86 | +}; |
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