| .. | .. |
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| 4 | 4 | - compatible: Should be one of the following. |
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| 5 | 5 | - "rockchip,px30-otp" - for PX30 SoCs. |
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| 6 | 6 | - "rockchip,rk3308-otp" - for RK3308 SoCs. |
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| 7 | | - - "rockchip,rk3568-otp" - for RK3568 SoCs. |
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| 8 | | - - "rockchip,rv1126-otp" - for RV1126 SoCs. |
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| 9 | | -- reg: Must contain an entry with the physical base address and length |
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| 10 | | - for each entry in reg-names. |
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| 11 | | -- address-cells: must be set to 1. |
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| 12 | | -- size-cells: Must be set to 1. |
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| 7 | +- reg: Should contain the registers location and size |
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| 13 | 8 | - clocks: Must contain an entry for each entry in clock-names. |
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| 14 | | -- clock-names: Should contain "clk_otp", "pclk_otp" and |
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| 15 | | - optionally also "pclk_otp_phy". |
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| 9 | +- clock-names: Should be "otp", "apb_pclk" and "phy". |
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| 16 | 10 | |
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| 17 | 11 | Optional properties: |
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| 18 | 12 | - resets: Must contain an entry for each entry in reset-names. |
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| 19 | 13 | See ../../reset/reset.txt for details. |
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| 20 | | -- reset-names: Should be "otp_phy". |
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| 14 | +- reset-names: Should be "phy". |
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| 21 | 15 | |
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| 22 | 16 | See nvmem.txt for more information. |
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| 23 | 17 | |
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| .. | .. |
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| 29 | 23 | #size-cells = <1>; |
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| 30 | 24 | clocks = <&cru SCLK_OTP_USR>, <&cru PCLK_OTP_NS>, |
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| 31 | 25 | <&cru PCLK_OTP_PHY>; |
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| 32 | | - clock-names = "clk_otp", "pclk_otp", "pclk_otp_phy"; |
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| 26 | + clock-names = "otp", "apb_pclk", "phy"; |
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| 33 | 27 | }; |
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