~hc/RK356X_SDK_RELEASE.git

..	..	@@ -36,29 +36,29 @@
36	36
37	37	Required properties:
38	38	- reg: shall contain the native Chip Select ids (0-3).
39		-- nand-rb: see nand.txt (0-1).
	39	+- nand-rb: see nand-controller.yaml (0-1).
40	40
41	41	Optional properties:
42	42	- marvell,nand-keep-config: orders the driver not to take the timings
43	43	from the core and leaving them completely untouched. Bootloader
44	44	timings will then be used.
45	45	- label: MTD name.
46		-- nand-on-flash-bbt: see nand.txt.
47		-- nand-ecc-mode: see nand.txt. Will use hardware ECC if not specified.
48		-- nand-ecc-algo: see nand.txt. This property is essentially useful when
	46	+- nand-on-flash-bbt: see nand-controller.yaml.
	47	+- nand-ecc-mode: see nand-controller.yaml. Will use hardware ECC if not specified.
	48	+- nand-ecc-algo: see nand-controller.yaml. This property is essentially useful when
49	49	not using hardware ECC. Howerver, it may be added when using hardware
50	50	ECC for clarification but will be ignored by the driver because ECC
51	51	mode is chosen depending on the page size and the strength required by
52	52	the NAND chip. This value may be overwritten with nand-ecc-strength
53	53	property.
54		-- nand-ecc-strength: see nand.txt.
55		-- nand-ecc-step-size: see nand.txt. Marvell's NAND flash controller does
	54	+- nand-ecc-strength: see nand-controller.yaml.
	55	+- nand-ecc-step-size: see nand-controller.yaml. Marvell's NAND flash controller does
56	56	use fixed strength (1-bit for Hamming, 16-bit for BCH), so the actual
57	57	step size will shrink or grow in order to fit the required strength.
58	58	Step sizes are not completely random for all and follow certain
59	59	patterns described in AN-379, "Marvell SoC NFC ECC".
60	60
61		-See Documentation/devicetree/bindings/mtd/nand.txt for more details on
	61	+See Documentation/devicetree/bindings/mtd/nand-controller.yaml for more details on
62	62	generic bindings.
63	63
64	64