修改4g拨号为QMI,需要在系统里后台执行quectel-CM

hc

2024-10-22 8ac6c7a54ed1b98d142dce24b11c6de6a1e239a5

 kernel/Documentation/devicetree/bindings/media/mediatek-vcodec.txt
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@@ -4,8 +4,9 @@
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 supports high resolution encoding and decoding functionalities.
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 Required properties:
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-- compatible : "mediatek,mt8173-vcodec-enc" for encoder
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-  "mediatek,mt8173-vcodec-dec" for decoder.
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+- compatible : "mediatek,mt8173-vcodec-enc" for MT8173 encoder
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+  "mediatek,mt8183-vcodec-enc" for MT8183 encoder.
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+  "mediatek,mt8173-vcodec-dec" for MT8173 decoder.
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 - reg : Physical base address of the video codec registers and length of
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   memory mapped region.
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 - interrupts : interrupt number to the cpu.
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@@ -17,9 +18,11 @@
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   "univpll_d2", "clk_cci400_sel", "vdec_sel", "vdecpll", "vencpll",
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   "venc_lt_sel", "vdec_bus_clk_src".
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 - iommus : should point to the respective IOMMU block with master port as
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-  argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
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+  argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
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   for details.
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-- mediatek,vpu : the node of video processor unit
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+One of the two following nodes:
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+- mediatek,vpu : the node of the video processor unit, if using VPU.
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+- mediatek,scp : the node of the SCP unit, if using SCP.
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 Example:
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@@ -66,6 +69,15 @@
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                   "vencpll",
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                   "venc_lt_sel",
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                   "vdec_bus_clk_src";
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+    assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>,
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+                      <&topckgen CLK_TOP_CCI400_SEL>,
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+                      <&topckgen CLK_TOP_VDEC_SEL>,
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+                      <&apmixedsys CLK_APMIXED_VCODECPLL>,
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+                      <&apmixedsys CLK_APMIXED_VENCPLL>;
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+    assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>,
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+                             <&topckgen CLK_TOP_UNIVPLL_D2>,
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+                             <&topckgen CLK_TOP_VCODECPLL>;
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+    assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>;
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   };
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   vcodec_enc: vcodec@18002000 {
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@@ -105,4 +117,8 @@
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                   "venc_sel",
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                   "venc_lt_sel_src",
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                   "venc_lt_sel";
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+    assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>,
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+                      <&topckgen CLK_TOP_VENC_LT_SEL>;
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+    assigned-clock-parents = <&topckgen CLK_TOP_VENCPLL_D2>,
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+                             <&topckgen CLK_TOP_UNIVPLL1_D2>;
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   };