| .. | .. |
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| 17 | 17 | - compatible: |
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| 18 | 18 | Usage: required |
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| 19 | 19 | Value type: <string> |
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| 20 | | - Definition: Should contain "qcom,<soc>-pdc" |
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| 20 | + Definition: Should contain "qcom,<soc>-pdc" and "qcom,pdc" |
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| 21 | + - "qcom,sc7180-pdc": For SC7180 |
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| 21 | 22 | - "qcom,sdm845-pdc": For SDM845 |
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| 22 | 23 | |
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| 23 | 24 | - reg: |
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| 24 | 25 | Usage: required |
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| 25 | 26 | Value type: <prop-encoded-array> |
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| 26 | 27 | Definition: Specifies the base physical address for PDC hardware. |
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| 28 | + Optionally, specify the PDC's GIC interface registers that |
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| 29 | + need to be configured for wakeup capable GPIOs routed to |
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| 30 | + the PDC. |
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| 27 | 31 | |
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| 28 | 32 | - interrupt-cells: |
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| 29 | 33 | Usage: required |
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| .. | .. |
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| 50 | 54 | The second element is the GIC hwirq number for the PDC port. |
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| 51 | 55 | The third element is the number of interrupts in sequence. |
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| 52 | 56 | |
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| 57 | +- qcom,scm-spi-cfg: |
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| 58 | + Usage: optional |
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| 59 | + Value type: <bool> |
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| 60 | + Definition: Specifies if the SPI configuration registers have to be |
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| 61 | + written from the firmware. Sometimes the PDC interface |
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| 62 | + register to the GIC can only be written from the firmware. |
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| 63 | + |
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| 53 | 64 | Example: |
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| 54 | 65 | |
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| 55 | 66 | pdc: interrupt-controller@b220000 { |
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| 56 | 67 | compatible = "qcom,sdm845-pdc"; |
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| 57 | | - reg = <0xb220000 0x30000>; |
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| 68 | + reg = <0 0x0b220000 0 0x30000>, <0 0x179900f0 0 0x60>; |
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| 58 | 69 | qcom,pdc-ranges = <0 512 94>, <94 641 15>, <115 662 7>; |
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| 59 | 70 | #interrupt-cells = <2>; |
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| 60 | 71 | interrupt-parent = <&intc>; |
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| 61 | 72 | interrupt-controller; |
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| 73 | + qcom,scm-spi-cfg; |
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| 62 | 74 | }; |
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| 63 | 75 | |
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| 64 | 76 | DT binding of a device that wants to use the GIC SPI 514 as a wakeup |
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