修改4g拨号为QMI,需要在系统里后台执行quectel-CM

hc

2024-10-22 8ac6c7a54ed1b98d142dce24b11c6de6a1e239a5

 kernel/Documentation/devicetree/bindings/interrupt-controller/marvell,icu.txt
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@@ -5,6 +5,8 @@
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 responsible for collecting all wired-interrupt sources in the CP and
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 communicating them to the GIC in the AP, the unit translates interrupt
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 requests on input wires to MSG memory mapped transactions to the GIC.
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+These messages will access a different GIC memory area depending on
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+their type (NSR, SR, SEI, REI, etc).
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 Required properties:
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@@ -12,20 +14,23 @@
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 - reg: Should contain ICU registers location and length.
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+Subnodes: Each group of interrupt is declared as a subnode of the ICU,
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+with their own compatible.
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+
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+Required properties for the icu_nsr/icu_sei subnodes:
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+
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+- compatible: Should be one of:
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+              * "marvell,cp110-icu-nsr"
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+	      * "marvell,cp110-icu-sr"
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+	      * "marvell,cp110-icu-sei"
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+	      * "marvell,cp110-icu-rei"
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+
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 - #interrupt-cells: Specifies the number of cells needed to encode an
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-  interrupt source. The value shall be 3.
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+  interrupt source. The value shall be 2.
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-  The 1st cell is the group type of the ICU interrupt. Possible group
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-  types are:
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+  The 1st cell is the index of the interrupt in the ICU unit.
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-   ICU_GRP_NSR (0x0) : Shared peripheral interrupt, non-secure
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-   ICU_GRP_SR  (0x1) : Shared peripheral interrupt, secure
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-   ICU_GRP_SEI (0x4) : System error interrupt
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-   ICU_GRP_REI (0x5) : RAM error interrupt
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-
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-  The 2nd cell is the index of the interrupt in the ICU unit.
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-
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-  The 3rd cell is the type of the interrupt. See arm,gic.txt for
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+  The 2nd cell is the type of the interrupt. See arm,gic.txt for
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   details.
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 - interrupt-controller: Identifies the node as an interrupt
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@@ -35,17 +40,73 @@
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   that allows to trigger interrupts using MSG memory mapped
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   transactions.
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+Note: each 'interrupts' property referring to any 'icu_xxx' node shall
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+      have a different number within [0:206].
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+
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 Example:
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 icu: interrupt-controller@1e0000 {
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 	compatible = "marvell,cp110-icu";
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-	reg = <0x1e0000 0x10>;
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+	reg = <0x1e0000 0x440>;
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+
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+	CP110_LABEL(icu_nsr): interrupt-controller@10 {
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+		compatible = "marvell,cp110-icu-nsr";
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+		reg = <0x10 0x20>;
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+		#interrupt-cells = <2>;
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+		interrupt-controller;
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+		msi-parent = <&gicp>;
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+	};
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+
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+	CP110_LABEL(icu_sei): interrupt-controller@50 {
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+		compatible = "marvell,cp110-icu-sei";
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+		reg = <0x50 0x10>;
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+		#interrupt-cells = <2>;
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+		interrupt-controller;
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+		msi-parent = <&sei>;
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+	};
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+};
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+
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+node1 {
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+	interrupt-parent = <&icu_nsr>;
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+	interrupts = <106 IRQ_TYPE_LEVEL_HIGH>;
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+};
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+
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+node2 {
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+	interrupt-parent = <&icu_sei>;
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+	interrupts = <107 IRQ_TYPE_LEVEL_HIGH>;
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+};
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+
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+/* Would not work with the above nodes */
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+node3 {
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+	interrupt-parent = <&icu_nsr>;
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+	interrupts = <107 IRQ_TYPE_LEVEL_HIGH>;
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+};
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+
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+The legacy bindings were different in this way:
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+
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+- #interrupt-cells: The value was 3.
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+	The 1st cell was the group type of the ICU interrupt. Possible
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+	group types were:
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+	ICU_GRP_NSR (0x0) : Shared peripheral interrupt, non-secure
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+	ICU_GRP_SR  (0x1) : Shared peripheral interrupt, secure
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+	ICU_GRP_SEI (0x4) : System error interrupt
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+	ICU_GRP_REI (0x5) : RAM error interrupt
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+	The 2nd cell was the index of the interrupt in the ICU unit.
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+	The 3rd cell was the type of the interrupt. See arm,gic.txt for
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+	details.
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+
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+Example:
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+
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+icu: interrupt-controller@1e0000 {
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+	compatible = "marvell,cp110-icu";
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+	reg = <0x1e0000 0x440>;
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+
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 	#interrupt-cells = <3>;
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 	interrupt-controller;
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 	msi-parent = <&gicp>;
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 };
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-usb3h0: usb3@500000 {
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+node1 {
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 	interrupt-parent = <&icu>;
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 	interrupts = <ICU_GRP_NSR 106 IRQ_TYPE_LEVEL_HIGH>;
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 };