修改4g拨号为QMI,需要在系统里后台执行quectel-CM

hc

2024-10-22 8ac6c7a54ed1b98d142dce24b11c6de6a1e239a5

 kernel/Documentation/devicetree/bindings/gpu/nvidia,gk20a.txt
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@@ -6,6 +6,7 @@
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   - nvidia,gk20a
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   - nvidia,gm20b
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   - nvidia,gp10b
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+  - nvidia,gv11b
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 - reg: Physical base address and length of the controller's registers.
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   Must contain two entries:
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   - first entry for bar0
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@@ -25,6 +26,9 @@
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 If the compatible string is "nvidia,gm20b", then the following clock
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 is also required:
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   - ref
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+If the compatible string is "nvidia,gv11b", then the following clock is also
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+required:
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+  - fuse
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 - resets: Must contain an entry for each entry in reset-names.
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   See ../reset/reset.txt for details.
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 - reset-names: Must include the following entries:
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@@ -88,3 +92,24 @@
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 		power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>;
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 		iommus = <&smmu TEGRA186_SID_GPU>;
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 	};
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+
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+Example for GV11B:
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+
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+	gpu@17000000 {
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+		compatible = "nvidia,gv11b";
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+		reg = <0x17000000 0x10000000>,
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+		      <0x18000000 0x10000000>;
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+		interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
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+			     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
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+		interrupt-names = "stall", "nonstall";
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+		clocks = <&bpmp TEGRA194_CLK_GPCCLK>,
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+			 <&bpmp TEGRA194_CLK_GPU_PWR>,
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+			 <&bpmp TEGRA194_CLK_FUSE>;
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+		clock-names = "gpu", "pwr", "fuse";
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+		resets = <&bpmp TEGRA194_RESET_GPU>;
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+		reset-names = "gpu";
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+		dma-coherent;
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+
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+		power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>;
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+		iommus = <&smmu TEGRA194_SID_GPU>;
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+	};