| .. | .. |
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| 263 | 263 | gpio@10040 { |
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| 264 | 264 | compatible = "altr,pio-1.0"; |
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| 265 | 265 | reg = <0x10040 0x20>; |
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| 266 | | - altr,gpio-bank-width = <4>; |
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| 266 | + altr,ngpio = <4>; |
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| 267 | 267 | #gpio-cells = <2>; |
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| 268 | 268 | clocks = <2>; |
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| 269 | 269 | gpio-controller; |
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| .. | .. |
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| 415 | 415 | firmware-name = "base.rbf"; |
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| 416 | 416 | |
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| 417 | 417 | fpga-bridge@4400 { |
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| 418 | | - compatible = "altr,freeze-bridge"; |
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| 418 | + compatible = "altr,freeze-bridge-controller"; |
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| 419 | 419 | reg = <0x4400 0x10>; |
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| 420 | 420 | |
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| 421 | 421 | fpga_region1: fpga-region1 { |
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| .. | .. |
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| 427 | 427 | }; |
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| 428 | 428 | |
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| 429 | 429 | fpga-bridge@4420 { |
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| 430 | | - compatible = "altr,freeze-bridge"; |
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| 430 | + compatible = "altr,freeze-bridge-controller"; |
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| 431 | 431 | reg = <0x4420 0x10>; |
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| 432 | 432 | |
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| 433 | 433 | fpga_region2: fpga-region2 { |
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| .. | .. |
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| 468 | 468 | compatible = "altr,pio-1.0"; |
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| 469 | 469 | reg = <0x10040 0x20>; |
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| 470 | 470 | clocks = <0x2>; |
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| 471 | | - altr,gpio-bank-width = <0x4>; |
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| 472 | | - resetvalue = <0x0>; |
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| 471 | + altr,ngpio = <0x4>; |
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| 473 | 472 | #gpio-cells = <0x2>; |
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| 474 | 473 | gpio-controller; |
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| 475 | 474 | }; |
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| .. | .. |
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| 494 | 493 | -- |
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| 495 | 494 | [1] www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug_partrecon.pdf |
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| 496 | 495 | [2] tspace.library.utoronto.ca/bitstream/1807/67932/1/Byma_Stuart_A_201411_MAS_thesis.pdf |
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| 497 | | -[3] http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_1/ug702.pdf |
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| 496 | +[3] https://www.xilinx.com/support/documentation/sw_manuals/xilinx14_1/ug702.pdf |
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