修改4g拨号为QMI,需要在系统里后台执行quectel-CM

hc

2024-10-22 8ac6c7a54ed1b98d142dce24b11c6de6a1e239a5

 kernel/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
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@@ -4,44 +4,35 @@
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 Required properties:
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 - #address-cells: Should be <1>.
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 - #size-cells: Should be <0>.
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-- compatible: must be one of:
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-	"rockchip,px30-mipi-dsi", "snps,dw-mipi-dsi".
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-	"rockchip,rk1808-mipi-dsi", "snps,dw-mipi-dsi".
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-	"rockchip,rk3128-mipi-dsi", "snps,dw-mipi-dsi".
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-	"rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi".
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-	"rockchip,rk3368-mipi-dsi", "snps,dw-mipi-dsi".
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-	"rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi".
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-	"rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi".
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-	"rockchip,rv1126-mipi-dsi", "snps,dw-mipi-dsi".
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+- compatible: one of
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+	"rockchip,px30-mipi-dsi", "snps,dw-mipi-dsi"
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+	"rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi"
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+	"rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"
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 - reg: Represent the physical address range of the controller.
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 - interrupts: Represent the controller's interrupt to the CPU(s).
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-- power-domains: a phandle to mipi dsi power domain node.
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-- resets: list of phandle + reset specifier pairs, as described in [3].
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-- reset-names: string reset name, must be "apb".
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-- clocks, clock-names: Phandles to the controller's APB clock(pclk),
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-  As described in [1].
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+- clocks, clock-names: Phandles to the controller's pll reference
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+  clock(ref) when using an internal dphy and APB clock(pclk).
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+  For RK3399, a phy config clock (phy_cfg) and a grf clock(grf)
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+  are required. As described in [1].
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 - rockchip,grf: this soc should set GRF regs to mux vopl/vopb.
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 - ports: contain a port node with endpoint definitions as defined in [2].
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   For vopb,set the reg = <0> and set the reg = <1> for vopl.
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+- video port 0 for the VOP input, the remote endpoint maybe vopb or vopl
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+- video port 1 for either a panel or subsequent encoder
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 Optional properties:
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-- clocks, clock-names:
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-  phandle to the SNPS-PHY config clock, name should be "phy_cfg".
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-  phandle to the SNPS-PHY PLL reference clock, name should be "ref".
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-  phandle to the Non-SNPS PHY high speed clock, name should be "hs_clk".
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-- phys: phandle to Non-SNPS PHY node
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-- phy-names: the string "mipi_dphy" when is found in a node, along with "phys"
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-  attribute, provides phandle to MIPI PHY node
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-- rockchip,lane-rate: optional override of the desired bandwidth.
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-- rockchip,dual-channel: for dual-channel mode, phandle to the slave channel.
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-- rockchip,data-swap: for dual-channel mode, swap two channel data of MIPI.
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+- phys: from general PHY binding: the phandle for the PHY device.
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+- phy-names: Should be "dphy" if phys references an external phy.
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+- power-domains: a phandle to mipi dsi power domain node.
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+- resets: list of phandle + reset specifier pairs, as described in [3].
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+- reset-names: string reset name, must be "apb".
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 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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 [2] Documentation/devicetree/bindings/media/video-interfaces.txt
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 [3] Documentation/devicetree/bindings/reset/reset.txt
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 Example:
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-	dsi: dsi@ff960000 {
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+	mipi_dsi: mipi@ff960000 {
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 		#address-cells = <1>;
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 		#size-cells = <0>;
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 		compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
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@@ -56,20 +47,29 @@
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 		ports {
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 			#address-cells = <1>;
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 			#size-cells = <0>;
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-			reg = <1>;
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-			port {
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+			mipi_in: port@0 {
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+				reg = <0>;
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 				#address-cells = <1>;
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 				#size-cells = <0>;
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-				dsi_in_vopb: endpoint@0 {
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+				mipi_in_vopb: endpoint@0 {
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 					reg = <0>;
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-					remote-endpoint = <&vopb_out_dsi>;
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+					remote-endpoint = <&vopb_out_mipi>;
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 				};
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-
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-				dsi_in_vopl: endpoint@1 {
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+				mipi_in_vopl: endpoint@1 {
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 					reg = <1>;
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-					remote-endpoint = <&vopl_out_dsi>;
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+					remote-endpoint = <&vopl_out_mipi>;
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+				};
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+			};
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+
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+			mipi_out: port@1 {
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+				reg = <1>;
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+				#address-cells = <1>;
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+				#size-cells = <0>;
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+
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+				mipi_out_panel: endpoint {
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+					remote-endpoint = <&panel_in_mipi>;
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 				};
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 			};
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 		};
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@@ -82,5 +82,11 @@
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 			pinctrl-names = "default";
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 			pinctrl-0 = <&lcd_en>;
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 			backlight = <&backlight>;
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+
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+			port {
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+				panel_in_mipi: endpoint {
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+					remote-endpoint = <&mipi_out_panel>;
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+				};
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+			};
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 		};
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 	};