修改4g拨号为QMI,需要在系统里后台执行quectel-CM

hc

2024-10-22 8ac6c7a54ed1b98d142dce24b11c6de6a1e239a5

 kernel/Documentation/devicetree/bindings/display/msm/dsi.txt
..
..
@@ -87,7 +87,11 @@
87
87
   * "qcom,dsi-phy-20nm"
88
88
   * "qcom,dsi-phy-28nm-8960"
89
89
   * "qcom,dsi-phy-14nm"
90
+  * "qcom,dsi-phy-14nm-660"
90
91
   * "qcom,dsi-phy-10nm"
92
+  * "qcom,dsi-phy-10nm-8998"
93
+  * "qcom,dsi-phy-7nm"
94
+  * "qcom,dsi-phy-7nm-8150"
91
95
 - reg: Physical base address and length of the registers of PLL, PHY. Some
92
96
   revisions require the PHY regulator base address, whereas others require the
93
97
   PHY lane base address. See below for each PHY revision.
..
..
@@ -96,7 +100,7 @@
96
100
   * "dsi_pll"
97
101
   * "dsi_phy"
98
102
   * "dsi_phy_regulator"
99
-  For DSI 14nm and 10nm PHYs:
103
+  For DSI 14nm, 10nm and 7nm PHYs:
100
104
   * "dsi_pll"
101
105
   * "dsi_phy"
102
106
   * "dsi_phy_lane"
..
..
@@ -106,6 +110,7 @@
106
110
 - clocks: Phandles to device clocks. See [1] for details on clock bindings.
107
111
 - clock-names: the following clocks are required:
108
112
   * "iface"
113
+  * "ref" (only required for new DTS files/entries)
109
114
   For 28nm HPM/LP, 28nm 8960 PHYs:
110
115
 - vddio-supply: phandle to vdd-io regulator device node
111
116
   For 20nm PHY:
..
..
@@ -113,7 +118,7 @@
113
118
 - vcca-supply: phandle to vcca regulator device node
114
119
   For 14nm PHY:
115
120
 - vcca-supply: phandle to vcca regulator device node
116
-  For 10nm PHY:
121
+  For 10nm and 7nm PHY:
117
122
 - vdds-supply: phandle to vdds regulator device node
118
123
 
119
124
 Optional properties: