~hc/RK356X_SDK_RELEASE.git

..	..	@@ -28,11 +28,18 @@
28	28	* "fsl,p4080-clockgen"
29	29	* "fsl,p5020-clockgen"
30	30	* "fsl,p5040-clockgen"
	31	+ * "fsl,t1023-clockgen"
	32	+ * "fsl,t1024-clockgen"
	33	+ * "fsl,t1040-clockgen"
	34	+ * "fsl,t1042-clockgen"
	35	+ * "fsl,t2080-clockgen"
	36	+ * "fsl,t2081-clockgen"
31	37	* "fsl,t4240-clockgen"
32	38	* "fsl,b4420-clockgen"
33	39	* "fsl,b4860-clockgen"
34	40	* "fsl,ls1012a-clockgen"
35	41	* "fsl,ls1021a-clockgen"
	42	+ * "fsl,ls1028a-clockgen"
36	43	* "fsl,ls1043a-clockgen"
37	44	* "fsl,ls1046a-clockgen"
38	45	* "fsl,ls1088a-clockgen"
..	..	@@ -77,8 +84,8 @@
77	84	1 cmux index (n in CLKCnCSR)
78	85	2 hwaccel index (n in CLKCGnHWACSR)
79	86	3 fman 0 for fm1, 1 for fm2
80		- 4 platform pll 0=pll, 1=pll/2, 2=pll/3, 3=pll/4
81		- 4=pll/5, 5=pll/6, 6=pll/7, 7=pll/8
	87	+ 4 platform pll n=pll/(n+1). For example, when n=1,
	88	+ that means output_freq=PLL_freq/2.
82	89	5 coreclk must be 0
83	90
84	91	3. Example