~hc/RK356X_SDK_RELEASE.git

..	..	@@ -50,6 +50,8 @@
50	50	IPs.
51	51	- "samsung,exynos5433-cmu-cam1" - clock controller compatible for CMU_CAM1
52	52	which generates clocks for Cortex-A5/MIPI_CSIS2/FIMC-LITE_C/FIMC-FD IPs.
	53	+ - "samsung,exynos5433-cmu-imem" - clock controller compatible for CMU_IMEM
	54	+ which generates clocks for SSS (Security SubSystem) and SlimSSS IPs.
53	55
54	56	- reg: physical base address of the controller and length of memory mapped
55	57	region.
..	..	@@ -167,6 +169,12 @@
167	169	- aclk_cam1_333
168	170	- aclk_cam1_400
169	171	- aclk_cam1_552
	172	+
	173	+ Input clocks for imem clock controller:
	174	+ - oscclk
	175	+ - aclk_imem_sssx_266
	176	+ - aclk_imem_266
	177	+ - aclk_imem_200
170	178
171	179	Optional properties:
172	180	- power-domains: a phandle to respective power domain node as described by
..	..	@@ -469,6 +477,21 @@
469	477	power-domains = <&pd_cam1>;
470	478	};
471	479
	480	+ cmu_imem: clock-controller@11060000 {
	481	+ compatible = "samsung,exynos5433-cmu-imem";
	482	+ reg = <0x11060000 0x1000>;
	483	+ #clock-cells = <1>;
	484	+
	485	+ clock-names = "oscclk",
	486	+ "aclk_imem_sssx_266",
	487	+ "aclk_imem_266",
	488	+ "aclk_imem_200";
	489	+ clocks = <&xxti>,
	490	+ <&cmu_top CLK_DIV_ACLK_IMEM_SSSX_266>,
	491	+ <&cmu_top CLK_DIV_ACLK_IMEM_266>,
	492	+ <&cmu_top CLK_DIV_ACLK_IMEM_200>;
	493	+ };
	494	+
472	495	Example 3: UART controller node that consumes the clock generated by the clock
473	496	controller.
474	497