修改4g拨号为QMI,需要在系统里后台执行quectel-CM

hc

2024-10-22 8ac6c7a54ed1b98d142dce24b11c6de6a1e239a5

 kernel/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt
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@@ -10,7 +10,15 @@
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 	- GXL (S905X, S905D) : "amlogic,meson-gxl-aoclkc"
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 	- GXM (S912) : "amlogic,meson-gxm-aoclkc"
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 	- AXG (A113D, A113X) : "amlogic,meson-axg-aoclkc"
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+	- G12A (S905X2, S905D2, S905Y2) : "amlogic,meson-g12a-aoclkc"
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 	followed by the common "amlogic,meson-gx-aoclkc"
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+- clocks: list of clock phandle, one for each entry clock-names.
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+- clock-names: should contain the following:
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+  * "xtal"     : the platform xtal
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+  * "mpeg-clk" : the main clock controller mother clock (aka clk81)
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+  * "ext-32k-0"  : external 32kHz reference #0 if any (optional)
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+  * "ext-32k-1"  : external 32kHz reference #1 if any (optional - gx only)
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+  * "ext-32k-2"  : external 32kHz reference #2 if any (optional - gx only)
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 - #clock-cells: should be 1.
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@@ -40,8 +48,9 @@
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 		compatible = "amlogic,meson-gxbb-aoclkc", "amlogic,meson-gx-aoclkc";
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 		#clock-cells = <1>;
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 		#reset-cells = <1>;
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+		clocks = <&xtal>, <&clkc CLKID_CLK81>;
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+		clock-names = "xtal", "mpeg-clk";
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 	};
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-};
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 Example: UART controller node that consumes the clock and reset generated
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   by the clock controller: