修改4g拨号为QMI,需要在系统里后台执行quectel-CM

hc

2024-10-22 8ac6c7a54ed1b98d142dce24b11c6de6a1e239a5

 kernel/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x
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@@ -1,4 +1,4 @@
1
-What:		/sys/bus/coresight/devices/<memory_map>.etm/enable_source
1
+What:		/sys/bus/coresight/devices/etm<N>/enable_source
2
2
 Date:		April 2015
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3
 KernelVersion:  4.01
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 Contact:        Mathieu Poirier <mathieu.poirier@linaro.org>
..
..
@@ -8,82 +8,82 @@
8
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 		of coresight components linking the source to the sink is
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 		configured and managed automatically by the coresight framework.
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11
-What:		/sys/bus/coresight/devices/<memory_map>.etm/cpu
11
+What:		/sys/bus/coresight/devices/etm<N>/cpu
12
12
 Date:		April 2015
13
13
 KernelVersion:	4.01
14
14
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
15
-Description:	(R) The CPU this tracing entity is associated with.
15
+Description:	(Read) The CPU this tracing entity is associated with.
16
16
 
17
-What:		/sys/bus/coresight/devices/<memory_map>.etm/nr_pe_cmp
17
+What:		/sys/bus/coresight/devices/etm<N>/nr_pe_cmp
18
18
 Date:		April 2015
19
19
 KernelVersion:	4.01
20
20
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
21
-Description:	(R) Indicates the number of PE comparator inputs that are
21
+Description:	(Read) Indicates the number of PE comparator inputs that are
22
22
 		available for tracing.
23
23
 
24
-What:		/sys/bus/coresight/devices/<memory_map>.etm/nr_addr_cmp
24
+What:		/sys/bus/coresight/devices/etm<N>/nr_addr_cmp
25
25
 Date:		April 2015
26
26
 KernelVersion:	4.01
27
27
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
28
-Description:	(R) Indicates the number of address comparator pairs that are
28
+Description:	(Read) Indicates the number of address comparator pairs that are
29
29
 		available for tracing.
30
30
 
31
-What:		/sys/bus/coresight/devices/<memory_map>.etm/nr_cntr
31
+What:		/sys/bus/coresight/devices/etm<N>/nr_cntr
32
32
 Date:		April 2015
33
33
 KernelVersion:	4.01
34
34
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
35
-Description:	(R) Indicates the number of counters that are available for
35
+Description:	(Read) Indicates the number of counters that are available for
36
36
 		tracing.
37
37
 
38
-What:		/sys/bus/coresight/devices/<memory_map>.etm/nr_ext_inp
38
+What:		/sys/bus/coresight/devices/etm<N>/nr_ext_inp
39
39
 Date:		April 2015
40
40
 KernelVersion:	4.01
41
41
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
42
-Description:	(R) Indicates how many external inputs are implemented.
42
+Description:	(Read) Indicates how many external inputs are implemented.
43
43
 
44
-What:		/sys/bus/coresight/devices/<memory_map>.etm/numcidc
44
+What:		/sys/bus/coresight/devices/etm<N>/numcidc
45
45
 Date:		April 2015
46
46
 KernelVersion:	4.01
47
47
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
48
-Description:	(R) Indicates the number of Context ID comparators that are
48
+Description:	(Read) Indicates the number of Context ID comparators that are
49
49
 		available for tracing.
50
50
 
51
-What:		/sys/bus/coresight/devices/<memory_map>.etm/numvmidc
51
+What:		/sys/bus/coresight/devices/etm<N>/numvmidc
52
52
 Date:		April 2015
53
53
 KernelVersion:	4.01
54
54
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
55
-Description:	(R) Indicates the number of VMID comparators that are available
55
+Description:	(Read) Indicates the number of VMID comparators that are available
56
56
 		for tracing.
57
57
 
58
-What:		/sys/bus/coresight/devices/<memory_map>.etm/nrseqstate
58
+What:		/sys/bus/coresight/devices/etm<N>/nrseqstate
59
59
 Date:		April 2015
60
60
 KernelVersion:	4.01
61
61
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
62
-Description:	(R) Indicates the number of sequencer states that are
62
+Description:	(Read) Indicates the number of sequencer states that are
63
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 		implemented.
64
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65
-What:		/sys/bus/coresight/devices/<memory_map>.etm/nr_resource
65
+What:		/sys/bus/coresight/devices/etm<N>/nr_resource
66
66
 Date:		April 2015
67
67
 KernelVersion:	4.01
68
68
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
69
-Description:	(R) Indicates the number of resource selection pairs that are
69
+Description:	(Read) Indicates the number of resource selection pairs that are
70
70
 		available for tracing.
71
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72
-What:		/sys/bus/coresight/devices/<memory_map>.etm/nr_ss_cmp
72
+What:		/sys/bus/coresight/devices/etm<N>/nr_ss_cmp
73
73
 Date:		April 2015
74
74
 KernelVersion:	4.01
75
75
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
76
-Description:	(R) Indicates the number of single-shot comparator controls that
76
+Description:	(Read) Indicates the number of single-shot comparator controls that
77
77
 		are available for tracing.
78
78
 
79
-What:		/sys/bus/coresight/devices/<memory_map>.etm/reset
79
+What:		/sys/bus/coresight/devices/etm<N>/reset
80
80
 Date:		April 2015
81
81
 KernelVersion:	4.01
82
82
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
83
-Description: 	(W) Cancels all configuration on a trace unit and set it back
83
+Description: 	(Write) Cancels all configuration on a trace unit and set it back
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 		to its boot configuration.
85
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86
-What:		/sys/bus/coresight/devices/<memory_map>.etm/mode
86
+What:		/sys/bus/coresight/devices/etm<N>/mode
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87
 Date:		April 2015
88
88
 KernelVersion:	4.01
89
89
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
..
..
@@ -91,373 +91,428 @@
91
91
 		P0 instruction tracing, branch broadcast, cycle counting and
92
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 		context ID tracing.
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94
-What:		/sys/bus/coresight/devices/<memory_map>.etm/pe
94
+What:		/sys/bus/coresight/devices/etm<N>/pe
95
95
 Date:		April 2015
96
96
 KernelVersion:	4.01
97
97
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
98
98
 Description: 	(RW) Controls which PE to trace.
99
99
 
100
-What:		/sys/bus/coresight/devices/<memory_map>.etm/event
100
+What:		/sys/bus/coresight/devices/etm<N>/event
101
101
 Date:		April 2015
102
102
 KernelVersion:	4.01
103
103
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
104
104
 Description: 	(RW) Controls the tracing of arbitrary events from bank 0 to 3.
105
105
 
106
-What:		/sys/bus/coresight/devices/<memory_map>.etm/event_instren
106
+What:		/sys/bus/coresight/devices/etm<N>/event_instren
107
107
 Date:		April 2015
108
108
 KernelVersion:	4.01
109
109
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
110
110
 Description: 	(RW) Controls the behavior of the events in bank 0 to 3.
111
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112
-What:		/sys/bus/coresight/devices/<memory_map>.etm/event_ts
112
+What:		/sys/bus/coresight/devices/etm<N>/event_ts
113
113
 Date:		April 2015
114
114
 KernelVersion:	4.01
115
115
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
116
116
 Description: 	(RW) Controls the insertion of global timestamps in the trace
117
117
 		streams.
118
118
 
119
-What:		/sys/bus/coresight/devices/<memory_map>.etm/syncfreq
119
+What:		/sys/bus/coresight/devices/etm<N>/syncfreq
120
120
 Date:		April 2015
121
121
 KernelVersion:	4.01
122
122
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
123
123
 Description: 	(RW) Controls how often trace synchronization requests occur.
124
124
 
125
-What:		/sys/bus/coresight/devices/<memory_map>.etm/cyc_threshold
125
+What:		/sys/bus/coresight/devices/etm<N>/cyc_threshold
126
126
 Date:		April 2015
127
127
 KernelVersion:	4.01
128
128
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
129
129
 Description: 	(RW) Sets the threshold value for cycle counting.
130
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131
-What:		/sys/bus/coresight/devices/<memory_map>.etm/bb_ctrl
131
+What:		/sys/bus/coresight/devices/etm<N>/bb_ctrl
132
132
 Date:		April 2015
133
133
 KernelVersion:	4.01
134
134
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
135
135
 Description: 	(RW) Controls which regions in the memory map are enabled to
136
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 		use branch broadcasting.
137
137
 
138
-What:		/sys/bus/coresight/devices/<memory_map>.etm/event_vinst
138
+What:		/sys/bus/coresight/devices/etm<N>/event_vinst
139
139
 Date:		April 2015
140
140
 KernelVersion:	4.01
141
141
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
142
142
 Description: 	(RW) Controls instruction trace filtering.
143
143
 
144
-What:		/sys/bus/coresight/devices/<memory_map>.etm/s_exlevel_vinst
144
+What:		/sys/bus/coresight/devices/etm<N>/s_exlevel_vinst
145
145
 Date:		April 2015
146
146
 KernelVersion:	4.01
147
147
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
148
148
 Description: 	(RW) In Secure state, each bit controls whether instruction
149
149
 		tracing is enabled for the corresponding exception level.
150
150
 
151
-What:		/sys/bus/coresight/devices/<memory_map>.etm/ns_exlevel_vinst
151
+What:		/sys/bus/coresight/devices/etm<N>/ns_exlevel_vinst
152
152
 Date:		April 2015
153
153
 KernelVersion:	4.01
154
154
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
155
155
 Description: 	(RW) In non-secure state, each bit controls whether instruction
156
156
 		tracing is enabled for the corresponding exception level.
157
157
 
158
-What:		/sys/bus/coresight/devices/<memory_map>.etm/addr_idx
158
+What:		/sys/bus/coresight/devices/etm<N>/addr_idx
159
159
 Date:		April 2015
160
160
 KernelVersion:	4.01
161
161
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
162
162
 Description: 	(RW) Select which address comparator or pair (of comparators) to
163
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 		work with.
164
164
 
165
-What:		/sys/bus/coresight/devices/<memory_map>.etm/addr_instdatatype
165
+What:		/sys/bus/coresight/devices/etm<N>/addr_instdatatype
166
166
 Date:		April 2015
167
167
 KernelVersion:	4.01
168
168
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
169
169
 Description: 	(RW) Controls what type of comparison the trace unit performs.
170
170
 
171
-What:		/sys/bus/coresight/devices/<memory_map>.etm/addr_single
171
+What:		/sys/bus/coresight/devices/etm<N>/addr_single
172
172
 Date:		April 2015
173
173
 KernelVersion:	4.01
174
174
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
175
175
 Description: 	(RW) Used to setup single address comparator values.
176
176
 
177
-What:		/sys/bus/coresight/devices/<memory_map>.etm/addr_range
177
+What:		/sys/bus/coresight/devices/etm<N>/addr_range
178
178
 Date:		April 2015
179
179
 KernelVersion:	4.01
180
180
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
181
181
 Description: 	(RW) Used to setup address range comparator values.
182
182
 
183
-What:		/sys/bus/coresight/devices/<memory_map>.etm/seq_idx
183
+What:		/sys/bus/coresight/devices/etm<N>/seq_idx
184
184
 Date:		April 2015
185
185
 KernelVersion:	4.01
186
186
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
187
187
 Description: 	(RW) Select which sequensor.
188
188
 
189
-What:		/sys/bus/coresight/devices/<memory_map>.etm/seq_state
189
+What:		/sys/bus/coresight/devices/etm<N>/seq_state
190
190
 Date:		April 2015
191
191
 KernelVersion:	4.01
192
192
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
193
193
 Description: 	(RW) Use this to set, or read, the sequencer state.
194
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195
-What:		/sys/bus/coresight/devices/<memory_map>.etm/seq_event
195
+What:		/sys/bus/coresight/devices/etm<N>/seq_event
196
196
 Date:		April 2015
197
197
 KernelVersion:	4.01
198
198
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
199
199
 Description: 	(RW) Moves the sequencer state to a specific state.
200
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201
-What:		/sys/bus/coresight/devices/<memory_map>.etm/seq_reset_event
201
+What:		/sys/bus/coresight/devices/etm<N>/seq_reset_event
202
202
 Date:		April 2015
203
203
 KernelVersion:	4.01
204
204
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
205
205
 Description: 	(RW) Moves the sequencer to state 0 when a programmed event
206
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 		occurs.
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208
-What:		/sys/bus/coresight/devices/<memory_map>.etm/cntr_idx
208
+What:		/sys/bus/coresight/devices/etm<N>/cntr_idx
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209
 Date:		April 2015
210
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 KernelVersion:	4.01
211
211
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
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212
 Description: 	(RW) Select which counter unit to work with.
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214
-What:		/sys/bus/coresight/devices/<memory_map>.etm/cntrldvr
214
+What:		/sys/bus/coresight/devices/etm<N>/cntrldvr
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215
 Date:		April 2015
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216
 KernelVersion:	4.01
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 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
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218
 Description: 	(RW) This sets or returns the reload count value of the
219
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 		specific counter.
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221
-What:		/sys/bus/coresight/devices/<memory_map>.etm/cntr_val
221
+What:		/sys/bus/coresight/devices/etm<N>/cntr_val
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222
 Date:		April 2015
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223
 KernelVersion:	4.01
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 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
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225
 Description: 	(RW) This sets or returns the current count value of the
226
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                 specific counter.
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228
-What:		/sys/bus/coresight/devices/<memory_map>.etm/cntr_ctrl
228
+What:		/sys/bus/coresight/devices/etm<N>/cntr_ctrl
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229
 Date:		April 2015
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 KernelVersion:	4.01
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 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
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 Description: 	(RW) Controls the operation of the selected counter.
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-What:		/sys/bus/coresight/devices/<memory_map>.etm/res_idx
234
+What:		/sys/bus/coresight/devices/etm<N>/res_idx
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 Date:		April 2015
236
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 KernelVersion:	4.01
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 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
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 Description: 	(RW) Select which resource selection unit to work with.
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240
-What:		/sys/bus/coresight/devices/<memory_map>.etm/res_ctrl
240
+What:		/sys/bus/coresight/devices/etm<N>/res_ctrl
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241
 Date:		April 2015
242
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 KernelVersion:	4.01
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 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
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244
 Description: 	(RW) Controls the selection of the resources in the trace unit.
245
245
 
246
-What:		/sys/bus/coresight/devices/<memory_map>.etm/ctxid_idx
246
+What:		/sys/bus/coresight/devices/etm<N>/ctxid_idx
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 Date:		April 2015
248
248
 KernelVersion:	4.01
249
249
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
250
250
 Description:	(RW) Select which context ID comparator to work with.
251
251
 
252
-What:		/sys/bus/coresight/devices/<memory_map>.etm/ctxid_pid
252
+What:		/sys/bus/coresight/devices/etm<N>/ctxid_pid
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253
 Date:		April 2015
254
254
 KernelVersion:	4.01
255
255
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
256
256
 Description:	(RW) Get/Set the context ID comparator value to trigger on.
257
257
 
258
-What:		/sys/bus/coresight/devices/<memory_map>.etm/ctxid_masks
258
+What:		/sys/bus/coresight/devices/etm<N>/ctxid_masks
259
259
 Date:		April 2015
260
260
 KernelVersion:	4.01
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261
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
262
262
 Description:	(RW) Mask for all 8 context ID comparator value
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 		registers (if implemented).
264
264
 
265
-What:		/sys/bus/coresight/devices/<memory_map>.etm/vmid_idx
265
+What:		/sys/bus/coresight/devices/etm<N>/vmid_idx
266
266
 Date:		April 2015
267
267
 KernelVersion:	4.01
268
268
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
269
269
 Description:	(RW) Select which virtual machine ID comparator to work with.
270
270
 
271
-What:		/sys/bus/coresight/devices/<memory_map>.etm/vmid_val
271
+What:		/sys/bus/coresight/devices/etm<N>/vmid_val
272
272
 Date:		April 2015
273
273
 KernelVersion:	4.01
274
274
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
275
275
 Description:	(RW) Get/Set the virtual machine ID comparator value to
276
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 		trigger on.
277
277
 
278
-What:		/sys/bus/coresight/devices/<memory_map>.etm/vmid_masks
278
+What:		/sys/bus/coresight/devices/etm<N>/vmid_masks
279
279
 Date:		April 2015
280
280
 KernelVersion:	4.01
281
281
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
282
282
 Description:	(RW) Mask for all 8 virtual machine ID comparator value
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 		registers (if implemented).
284
284
 
285
-What:		/sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcoslsr
285
+What:		/sys/bus/coresight/devices/etm<N>/addr_exlevel_s_ns
286
+Date:		December 2019
287
+KernelVersion:	5.5
288
+Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
289
+Description:	(RW) Set the Exception Level matching bits for secure and
290
+		non-secure exception levels.
291
+
292
+What:		/sys/bus/coresight/devices/etm<N>/vinst_pe_cmp_start_stop
293
+Date:		December 2019
294
+KernelVersion:	5.5
295
+Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
296
+Description:	(RW) Access the start stop control register for PE input
297
+		comparators.
298
+
299
+What:		/sys/bus/coresight/devices/etm<N>/addr_cmp_view
300
+Date:		December 2019
301
+KernelVersion:	5.5
302
+Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
303
+Description:	(Read) Print the current settings for the selected address
304
+		comparator.
305
+
306
+What:		/sys/bus/coresight/devices/etm<N>/sshot_idx
307
+Date:		December 2019
308
+KernelVersion:	5.5
309
+Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
310
+Description:	(RW) Select the single shot control register to access.
311
+
312
+What:		/sys/bus/coresight/devices/etm<N>/sshot_ctrl
313
+Date:		December 2019
314
+KernelVersion:	5.5
315
+Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
316
+Description:	(RW) Access the selected single shot control register.
317
+
318
+What:		/sys/bus/coresight/devices/etm<N>/sshot_status
319
+Date:		December 2019
320
+KernelVersion:	5.5
321
+Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
322
+Description:	(Read) Print the current value of the selected single shot
323
+		status register.
324
+
325
+What:		/sys/bus/coresight/devices/etm<N>/sshot_pe_ctrl
326
+Date:		December 2019
327
+KernelVersion:	5.5
328
+Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
329
+Description:	(RW) Access the selected single show PE comparator control
330
+		register.
331
+
332
+What:		/sys/bus/coresight/devices/etm<N>/mgmt/trcoslsr
286
333
 Date:		April 2015
287
334
 KernelVersion:	4.01
288
335
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
289
-Description:	(R) Print the content of the OS Lock Status Register (0x304).
336
+Description:	(Read) Print the content of the OS Lock Status Register (0x304).
290
337
 		The value it taken directly  from the HW.
291
338
 
292
-What:		/sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpdcr
339
+What:		/sys/bus/coresight/devices/etm<N>/mgmt/trcpdcr
293
340
 Date:		April 2015
294
341
 KernelVersion:	4.01
295
342
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
296
-Description:	(R) Print the content of the Power Down Control Register
343
+Description:	(Read) Print the content of the Power Down Control Register
297
344
 		(0x310).  The value is taken directly from the HW.
298
345
 
299
-What:		/sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpdsr
346
+What:		/sys/bus/coresight/devices/etm<N>/mgmt/trcpdsr
300
347
 Date:		April 2015
301
348
 KernelVersion:	4.01
302
349
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
303
-Description:	(R) Print the content of the Power Down Status Register
350
+Description:	(Read) Print the content of the Power Down Status Register
304
351
 		(0x314).  The value is taken directly from the HW.
305
352
 
306
-What:		/sys/bus/coresight/devices/<memory_map>.etm/mgmt/trclsr
353
+What:		/sys/bus/coresight/devices/etm<N>/mgmt/trclsr
307
354
 Date:		April 2015
308
355
 KernelVersion:	4.01
309
356
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
310
-Description:	(R) Print the content of the SW Lock Status Register
357
+Description:	(Read) Print the content of the SW Lock Status Register
311
358
 		(0xFB4).  The value is taken directly from the HW.
312
359
 
313
-What:		/sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcauthstatus
360
+What:		/sys/bus/coresight/devices/etm<N>/mgmt/trcauthstatus
314
361
 Date:		April 2015
315
362
 KernelVersion:	4.01
316
363
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
317
-Description:	(R) Print the content of the Authentication Status Register
364
+Description:	(Read) Print the content of the Authentication Status Register
318
365
 		(0xFB8).  The value is taken directly from the HW.
319
366
 
320
-What:		/sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcdevid
367
+What:		/sys/bus/coresight/devices/etm<N>/mgmt/trcdevid
321
368
 Date:		April 2015
322
369
 KernelVersion:	4.01
323
370
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
324
-Description:	(R) Print the content of the Device ID Register
371
+Description:	(Read) Print the content of the Device ID Register
325
372
 		(0xFC8).  The value is taken directly from the HW.
326
373
 
327
-What:		/sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcdevtype
374
+What:		/sys/bus/coresight/devices/etm<N>/mgmt/trcdevarch
375
+Date:		January 2021
376
+KernelVersion:	5.12
377
+Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
378
+Description:	(Read) Print the content of the Device Architecture Register
379
+		(offset 0xFBC).  The value is taken directly read
380
+		from the HW.
381
+
382
+What:		/sys/bus/coresight/devices/etm<N>/mgmt/trcdevtype
328
383
 Date:		April 2015
329
384
 KernelVersion:	4.01
330
385
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
331
-Description:	(R) Print the content of the Device Type Register
386
+Description:	(Read) Print the content of the Device Type Register
332
387
 		(0xFCC).  The value is taken directly from the HW.
333
388
 
334
-What:		/sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpidr0
389
+What:		/sys/bus/coresight/devices/etm<N>/mgmt/trcpidr0
335
390
 Date:		April 2015
336
391
 KernelVersion:	4.01
337
392
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
338
-Description:	(R) Print the content of the Peripheral ID0 Register
393
+Description:	(Read) Print the content of the Peripheral ID0 Register
339
394
 		(0xFE0).  The value is taken directly from the HW.
340
395
 
341
-What:		/sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpidr1
396
+What:		/sys/bus/coresight/devices/etm<N>/mgmt/trcpidr1
342
397
 Date:		April 2015
343
398
 KernelVersion:	4.01
344
399
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
345
-Description:	(R) Print the content of the Peripheral ID1 Register
400
+Description:	(Read) Print the content of the Peripheral ID1 Register
346
401
 		(0xFE4).  The value is taken directly from the HW.
347
402
 
348
-What:		/sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpidr2
403
+What:		/sys/bus/coresight/devices/etm<N>/mgmt/trcpidr2
349
404
 Date:		April 2015
350
405
 KernelVersion:	4.01
351
406
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
352
-Description:	(R) Print the content of the Peripheral ID2 Register
407
+Description:	(Read) Print the content of the Peripheral ID2 Register
353
408
 		(0xFE8).  The value is taken directly from the HW.
354
409
 
355
-What:		/sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpidr3
410
+What:		/sys/bus/coresight/devices/etm<N>/mgmt/trcpidr3
356
411
 Date:		April 2015
357
412
 KernelVersion:	4.01
358
413
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
359
-Description:	(R) Print the content of the Peripheral ID3 Register
414
+Description:	(Read) Print the content of the Peripheral ID3 Register
360
415
 		(0xFEC).  The value is taken directly from the HW.
361
416
 
362
-What:		/sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcconfig
417
+What:		/sys/bus/coresight/devices/etm<N>/mgmt/trcconfig
363
418
 Date:		February 2016
364
419
 KernelVersion:	4.07
365
420
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
366
-Description:	(R) Print the content of the trace configuration register
421
+Description:	(Read) Print the content of the trace configuration register
367
422
 		(0x010) as currently set by SW.
368
423
 
369
-What:		/sys/bus/coresight/devices/<memory_map>.etm/mgmt/trctraceid
424
+What:		/sys/bus/coresight/devices/etm<N>/mgmt/trctraceid
370
425
 Date:		February 2016
371
426
 KernelVersion:	4.07
372
427
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
373
-Description:	(R) Print the content of the trace ID register (0x040).
428
+Description:	(Read) Print the content of the trace ID register (0x040).
374
429
 
375
-What:		/sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr0
430
+What:		/sys/bus/coresight/devices/etm<N>/trcidr/trcidr0
376
431
 Date:		April 2015
377
432
 KernelVersion:	4.01
378
433
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
379
-Description:	(R) Returns the tracing capabilities of the trace unit (0x1E0).
434
+Description:	(Read) Returns the tracing capabilities of the trace unit (0x1E0).
380
435
 		The value is taken directly from the HW.
381
436
 
382
-What:		/sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr1
437
+What:		/sys/bus/coresight/devices/etm<N>/trcidr/trcidr1
383
438
 Date:		April 2015
384
439
 KernelVersion:	4.01
385
440
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
386
-Description:	(R) Returns the tracing capabilities of the trace unit (0x1E4).
441
+Description:	(Read) Returns the tracing capabilities of the trace unit (0x1E4).
387
442
 		The value is taken directly from the HW.
388
443
 
389
-What:		/sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr2
444
+What:		/sys/bus/coresight/devices/etm<N>/trcidr/trcidr2
390
445
 Date:		April 2015
391
446
 KernelVersion:	4.01
392
447
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
393
-Description:	(R) Returns the maximum size of the data value, data address,
448
+Description:	(Read) Returns the maximum size of the data value, data address,
394
449
 		VMID, context ID and instuction address in the trace unit
395
450
 		(0x1E8).  The value is taken directly from the HW.
396
451
 
397
-What:		/sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr3
452
+What:		/sys/bus/coresight/devices/etm<N>/trcidr/trcidr3
398
453
 Date:		April 2015
399
454
 KernelVersion:	4.01
400
455
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
401
-Description:	(R) Returns the value associated with various resources
456
+Description:	(Read) Returns the value associated with various resources
402
457
 		available to the trace unit.  See the Trace Macrocell
403
458
 		architecture specification for more details (0x1E8).
404
459
 		The value is taken directly from the HW.
405
460
 
406
-What:		/sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr4
461
+What:		/sys/bus/coresight/devices/etm<N>/trcidr/trcidr4
407
462
 Date:		April 2015
408
463
 KernelVersion:	4.01
409
464
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
410
-Description:	(R) Returns how many resources the trace unit supports (0x1F0).
465
+Description:	(Read) Returns how many resources the trace unit supports (0x1F0).
411
466
 		The value is taken directly from the HW.
412
467
 
413
-What:		/sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr5
468
+What:		/sys/bus/coresight/devices/etm<N>/trcidr/trcidr5
414
469
 Date:		April 2015
415
470
 KernelVersion:	4.01
416
471
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
417
-Description:	(R) Returns how many resources the trace unit supports (0x1F4).
472
+Description:	(Read) Returns how many resources the trace unit supports (0x1F4).
418
473
 		The value is taken directly from the HW.
419
474
 
420
-What:		/sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr8
475
+What:		/sys/bus/coresight/devices/etm<N>/trcidr/trcidr8
421
476
 Date:		April 2015
422
477
 KernelVersion:	4.01
423
478
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
424
-Description:	(R) Returns the maximum speculation depth of the instruction
479
+Description:	(Read) Returns the maximum speculation depth of the instruction
425
480
 		trace stream. (0x180).  The value is taken directly from the HW.
426
481
 
427
-What:		/sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr9
482
+What:		/sys/bus/coresight/devices/etm<N>/trcidr/trcidr9
428
483
 Date:		April 2015
429
484
 KernelVersion:	4.01
430
485
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
431
-Description:	(R) Returns the number of P0 right-hand keys that the trace unit
486
+Description:	(Read) Returns the number of P0 right-hand keys that the trace unit
432
487
 		can use (0x184).  The value is taken directly from the HW.
433
488
 
434
-What:		/sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr10
489
+What:		/sys/bus/coresight/devices/etm<N>/trcidr/trcidr10
435
490
 Date:		April 2015
436
491
 KernelVersion:	4.01
437
492
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
438
-Description:	(R) Returns the number of P1 right-hand keys that the trace unit
493
+Description:	(Read) Returns the number of P1 right-hand keys that the trace unit
439
494
 		can use (0x188).  The value is taken directly from the HW.
440
495
 
441
-What:		/sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr11
496
+What:		/sys/bus/coresight/devices/etm<N>/trcidr/trcidr11
442
497
 Date:		April 2015
443
498
 KernelVersion:	4.01
444
499
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
445
-Description:	(R) Returns the number of special P1 right-hand keys that the
500
+Description:	(Read) Returns the number of special P1 right-hand keys that the
446
501
 		trace unit can use (0x18C).  The value is taken directly from
447
502
 		the HW.
448
503
 
449
-What:		/sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr12
504
+What:		/sys/bus/coresight/devices/etm<N>/trcidr/trcidr12
450
505
 Date:		April 2015
451
506
 KernelVersion:	4.01
452
507
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
453
-Description:	(R) Returns the number of conditional P1 right-hand keys that
508
+Description:	(Read) Returns the number of conditional P1 right-hand keys that
454
509
 		the trace unit can use (0x190).  The value is taken directly
455
510
 		from the HW.
456
511
 
457
-What:		/sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr13
512
+What:		/sys/bus/coresight/devices/etm<N>/trcidr/trcidr13
458
513
 Date:		April 2015
459
514
 KernelVersion:	4.01
460
515
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
461
-Description:	(R) Returns the number of special conditional P1 right-hand keys
516
+Description:	(Read) Returns the number of special conditional P1 right-hand keys
462
517
 		that the trace unit can use (0x194).  The value is taken
463
518
 		directly from the HW.