forked from ~ljy/RK356X_SDK_RELEASE
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2024-02-19 890e1df1bec891d9203724541e81f8fbe5183388 
 kernel/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c
....@@ -4,13 +4,17 @@
44  * Author: Andy Yan <andy.yan@rock-chips.com>
55  */
66 
7
-#include <drm/drmP.h>
87 #include <linux/kernel.h>
98 #include <linux/component.h>
9
+#include <linux/of.h>
10
+#include <linux/platform_device.h>
1011 #include <dt-bindings/display/rockchip_vop.h>
1112 
13
+#include <drm/drm_fourcc.h>
14
+#include <drm/drm_print.h>
1215 #include "rockchip_drm_vop.h"
1316 #include "rockchip_vop_reg.h"
17
+#include "rockchip_drm_drv.h"
1418 
1519 #define _VOP_REG(off, _mask, _shift, _write_mask) \
1620 		{ \
....@@ -27,6 +31,10 @@
2731 		_VOP_REG(off, _mask, s, true)
2832 
2933 static const uint32_t formats_for_cluster[] = {
34
+	DRM_FORMAT_XRGB2101010,
35
+	DRM_FORMAT_ARGB2101010,
36
+	DRM_FORMAT_XBGR2101010,
37
+	DRM_FORMAT_ABGR2101010,
3038 	DRM_FORMAT_XRGB8888,
3139 	DRM_FORMAT_ARGB8888,
3240 	DRM_FORMAT_XBGR8888,
....@@ -35,16 +43,17 @@
3543 	DRM_FORMAT_BGR888,
3644 	DRM_FORMAT_RGB565,
3745 	DRM_FORMAT_BGR565,
38
-	DRM_FORMAT_NV12,
39
-	DRM_FORMAT_NV16,
40
-	DRM_FORMAT_NV24,
41
-	DRM_FORMAT_NV12_10,
42
-	DRM_FORMAT_NV16_10,
43
-	DRM_FORMAT_NV24_10,
46
+	DRM_FORMAT_YUV420_8BIT, /* yuv420_8bit non-Linear mode only */
47
+	DRM_FORMAT_YUV420_10BIT, /* yuv420_10bit non-Linear mode only */
4448 	DRM_FORMAT_YUYV, /* yuv422_8bit non-Linear mode only*/
49
+	DRM_FORMAT_Y210, /* yuv422_10bit non-Linear mode only */
4550 };
4651 
47
-static const uint32_t formats_for_rk356x_esmart[] = {
52
+static const uint32_t formats_for_vop3_cluster[] = {
53
+	DRM_FORMAT_XRGB2101010,
54
+	DRM_FORMAT_ARGB2101010,
55
+	DRM_FORMAT_XBGR2101010,
56
+	DRM_FORMAT_ABGR2101010,
4857 	DRM_FORMAT_XRGB8888,
4958 	DRM_FORMAT_ARGB8888,
5059 	DRM_FORMAT_XBGR8888,
....@@ -53,14 +62,21 @@
5362 	DRM_FORMAT_BGR888,
5463 	DRM_FORMAT_RGB565,
5564 	DRM_FORMAT_BGR565,
56
-	DRM_FORMAT_NV12,
57
-	DRM_FORMAT_NV16,
58
-	DRM_FORMAT_NV24,
59
-	DRM_FORMAT_NV12_10,
60
-	DRM_FORMAT_NV16_10,
61
-	DRM_FORMAT_NV24_10,
62
-	DRM_FORMAT_YVYU,
63
-	DRM_FORMAT_VYUY,
65
+	DRM_FORMAT_NV12, /* yuv420_8bit linear mode, 2 plane */
66
+	DRM_FORMAT_NV21, /* yvu420_8bit linear mode, 2 plane */
67
+	DRM_FORMAT_NV16, /* yuv422_8bit linear mode, 2 plane */
68
+	DRM_FORMAT_NV61, /* yvu422_8bit linear mode, 2 plane */
69
+	DRM_FORMAT_NV24, /* yuv444_8bit linear mode, 2 plane */
70
+	DRM_FORMAT_NV42, /* yvu444_8bit linear mode, 2 plane */
71
+	DRM_FORMAT_NV15, /* yuv420_10bit linear mode, 2 plane, no padding */
72
+#ifdef CONFIG_NO_GKI
73
+	DRM_FORMAT_NV20, /* yuv422_10bit linear mode, 2 plane, no padding */
74
+	DRM_FORMAT_NV30, /* yuv444_10bit linear mode, 2 plane, no padding */
75
+#endif
76
+	DRM_FORMAT_YUV420_8BIT, /* yuv420_8bit non-Linear mode only */
77
+	DRM_FORMAT_YUV420_10BIT, /* yuv420_10bit non-Linear mode only */
78
+	DRM_FORMAT_YUYV, /* yuv422_8bit non-Linear mode only*/
79
+	DRM_FORMAT_Y210, /* yuv422_10bit non-Linear mode only */
6480 };
6581 
6682 static const uint32_t formats_for_esmart[] = {
....@@ -72,16 +88,43 @@
7288 	DRM_FORMAT_BGR888,
7389 	DRM_FORMAT_RGB565,
7490 	DRM_FORMAT_BGR565,
75
-	DRM_FORMAT_NV12,
76
-	DRM_FORMAT_NV16,
77
-	DRM_FORMAT_NV24,
78
-	DRM_FORMAT_NV12_10,
79
-	DRM_FORMAT_NV16_10,
80
-	DRM_FORMAT_NV24_10,
81
-	DRM_FORMAT_YVYU,
82
-	DRM_FORMAT_VYUY,
83
-	DRM_FORMAT_YUYV,
84
-	DRM_FORMAT_UYVY,
91
+	DRM_FORMAT_NV12, /* yuv420_8bit linear mode, 2 plane */
92
+	DRM_FORMAT_NV21, /* yvu420_8bit linear mode, 2 plane */
93
+	DRM_FORMAT_NV16, /* yuv422_8bit linear mode, 2 plane */
94
+	DRM_FORMAT_NV61, /* yvu422_8bit linear mode, 2 plane */
95
+	DRM_FORMAT_NV24, /* yuv444_8bit linear mode, 2 plane */
96
+	DRM_FORMAT_NV42, /* yvu444_8bit linear mode, 2 plane */
97
+	DRM_FORMAT_NV15, /* yuv420_10bit linear mode, 2 plane, no padding */
98
+#ifdef CONFIG_NO_GKI
99
+	DRM_FORMAT_NV20, /* yuv422_10bit linear mode, 2 plane, no padding */
100
+	DRM_FORMAT_NV30, /* yuv444_10bit linear mode, 2 plane, no padding */
101
+#endif
102
+	DRM_FORMAT_YVYU, /* yuv422_8bit[YVYU] linear mode */
103
+	DRM_FORMAT_VYUY, /* yuv422_8bit[VYUY] linear mode */
104
+	DRM_FORMAT_YUYV, /* yuv422_8bit[YUYV] linear mode */
105
+	DRM_FORMAT_UYVY, /* yuv422_8bit[UYVY] linear mode */
106
+};
107
+
108
+/* RK356x can't support uv swap for YUYV and UYVY */
109
+static const uint32_t formats_for_rk356x_esmart[] = {
110
+	DRM_FORMAT_XRGB8888,
111
+	DRM_FORMAT_ARGB8888,
112
+	DRM_FORMAT_XBGR8888,
113
+	DRM_FORMAT_ABGR8888,
114
+	DRM_FORMAT_RGB888,
115
+	DRM_FORMAT_BGR888,
116
+	DRM_FORMAT_RGB565,
117
+	DRM_FORMAT_BGR565,
118
+	DRM_FORMAT_NV12, /* yuv420_8bit linear mode, 2 plane */
119
+	DRM_FORMAT_NV16, /* yuv422_8bit linear mode, 2 plane */
120
+	DRM_FORMAT_NV24, /* yuv444_8bit linear mode, 2 plane */
121
+	DRM_FORMAT_NV15, /* yuv420_10bit linear mode, 2 plane, no padding */
122
+#ifdef CONFIG_NO_GKI
123
+	DRM_FORMAT_NV20, /* yuv422_10bit linear mode, 2 plane, no padding */
124
+	DRM_FORMAT_NV30, /* yuv444_10bit linear mode, 2 plane, no padding */
125
+#endif
126
+	DRM_FORMAT_YUYV, /* yuv422_8bit[YUYV] linear mode */
127
+	DRM_FORMAT_UYVY, /* yuv422_8bit[UYVY] linear mode */
85128 };
86129 
87130 static const uint32_t formats_for_smart[] = {
....@@ -108,6 +151,45 @@
108151 };
109152 
110153 static const uint64_t format_modifiers_afbc[] = {
154
+	DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16),
155
+
156
+	DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 |
157
+				AFBC_FORMAT_MOD_SPARSE),
158
+
159
+	DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 |
160
+				AFBC_FORMAT_MOD_YTR),
161
+
162
+	DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 |
163
+				AFBC_FORMAT_MOD_CBR),
164
+
165
+	DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 |
166
+				AFBC_FORMAT_MOD_YTR |
167
+				AFBC_FORMAT_MOD_SPARSE),
168
+
169
+	DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 |
170
+				AFBC_FORMAT_MOD_CBR |
171
+				AFBC_FORMAT_MOD_SPARSE),
172
+
173
+	DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 |
174
+				AFBC_FORMAT_MOD_YTR |
175
+				AFBC_FORMAT_MOD_CBR),
176
+
177
+	DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 |
178
+				AFBC_FORMAT_MOD_YTR |
179
+				AFBC_FORMAT_MOD_CBR |
180
+				AFBC_FORMAT_MOD_SPARSE),
181
+
182
+	/* SPLIT mandates SPARSE, RGB modes mandates YTR */
183
+	DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 |
184
+				AFBC_FORMAT_MOD_YTR |
185
+				AFBC_FORMAT_MOD_SPARSE |
186
+				AFBC_FORMAT_MOD_SPLIT),
187
+
188
+	DRM_FORMAT_MOD_LINEAR,
189
+	DRM_FORMAT_MOD_INVALID,
190
+};
191
+
192
+static const uint64_t format_modifiers_afbc_no_linear_mode[] = {
111193 	DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16),
112194 
113195 	DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 |
....@@ -496,6 +578,175 @@
496578 	.clear = VOP_REG_MASK(RK3568_VP2_INT_CLR, 0xffff, 0),
497579 };
498580 
581
+static const struct vop_intr rk3588_vp3_intr = {
582
+	.intrs = rk3568_vop_intrs,
583
+	.nintrs = ARRAY_SIZE(rk3568_vop_intrs),
584
+	.line_flag_num[0] = VOP_REG(RK3588_VP3_LINE_FLAG, 0x1fff, 0),
585
+	.line_flag_num[1] = VOP_REG(RK3588_VP3_LINE_FLAG, 0x1fff, 16),
586
+	.status = VOP_REG(RK3588_VP3_INT_STATUS, 0xffff, 0),
587
+	.enable = VOP_REG_MASK(RK3588_VP3_INT_EN, 0xffff, 0),
588
+	.clear = VOP_REG_MASK(RK3588_VP3_INT_CLR, 0xffff, 0),
589
+};
590
+
591
+static const struct vop2_dsc_regs rk3588_vop_dsc_8k_regs = {
592
+	/* DSC SYS CTRL */
593
+	.dsc_port_sel = VOP_REG(RK3588_DSC_8K_SYS_CTRL, 0x3, 0),
594
+	.dsc_man_mode = VOP_REG(RK3588_DSC_8K_SYS_CTRL, 0x1, 2),
595
+	.dsc_interface_mode = VOP_REG(RK3588_DSC_8K_SYS_CTRL, 0x3, 4),
596
+	.dsc_pixel_num = VOP_REG(RK3588_DSC_8K_SYS_CTRL, 0x3, 6),
597
+	.dsc_pxl_clk_div = VOP_REG(RK3588_DSC_8K_SYS_CTRL, 0x1, 8),
598
+	.dsc_cds_clk_div = VOP_REG(RK3588_DSC_8K_SYS_CTRL, 0x3, 12),
599
+	.dsc_txp_clk_div = VOP_REG(RK3588_DSC_8K_SYS_CTRL, 0x3, 14),
600
+	.dsc_init_dly_mode = VOP_REG(RK3588_DSC_8K_SYS_CTRL, 0x1, 16),
601
+	.dsc_scan_en = VOP_REG(RK3588_DSC_8K_SYS_CTRL, 0x1, 17),
602
+	.dsc_halt_en = VOP_REG(RK3588_DSC_8K_SYS_CTRL, 0x1, 18),
603
+	.rst_deassert = VOP_REG(RK3588_DSC_8K_RST, 0x1, 0),
604
+	.dsc_flush = VOP_REG(RK3588_DSC_8K_RST, 0x1, 16),
605
+	.dsc_cfg_done = VOP_REG(RK3588_DSC_8K_CFG_DONE, 0x1, 0),
606
+	.dsc_init_dly_num = VOP_REG(RK3588_DSC_8K_INIT_DLY, 0xffff, 0),
607
+	.scan_timing_para_imd_en = VOP_REG(RK3588_DSC_8K_INIT_DLY, 0x1, 16),
608
+	.dsc_htotal_pw = VOP_REG(RK3588_DSC_8K_HTOTAL_HS_END, 0xffffffff, 0),
609
+	.dsc_hact_st_end = VOP_REG(RK3588_DSC_8K_HACT_ST_END, 0xffffffff, 0),
610
+	.dsc_vtotal = VOP_REG(RK3588_DSC_8K_VTOTAL_VS_END, 0xffff, 16),
611
+	.dsc_vs_end = VOP_REG(RK3588_DSC_8K_VTOTAL_VS_END, 0xffff, 0),
612
+	.dsc_vact_st_end = VOP_REG(RK3588_DSC_8K_VACT_ST_END, 0xffffffff, 0),
613
+	.dsc_error_status = VOP_REG(RK3588_DSC_8K_STATUS, 0x1, 0),
614
+
615
+	/* DSC encoder */
616
+	.dsc_pps0_3 = VOP_REG(RK3588_DSC_8K_PPS0_3, 0xffffffff, 0),
617
+	.dsc_en = VOP_REG(RK3588_DSC_8K_CTRL0, 0x1, 0),
618
+	.dsc_rbit = VOP_REG(RK3588_DSC_8K_CTRL0, 0x1, 2),
619
+	.dsc_rbyt = VOP_REG(RK3588_DSC_8K_CTRL0, 0x1, 3),
620
+	.dsc_flal = VOP_REG(RK3588_DSC_8K_CTRL0, 0x1, 4),
621
+	.dsc_mer = VOP_REG(RK3588_DSC_8K_CTRL0, 0x1, 5),
622
+	.dsc_epb = VOP_REG(RK3588_DSC_8K_CTRL0, 0x1, 6),
623
+	.dsc_epl = VOP_REG(RK3588_DSC_8K_CTRL0, 0x1, 7),
624
+	.dsc_nslc = VOP_REG(RK3588_DSC_8K_CTRL0, 0x7, 16),
625
+	.dsc_sbo = VOP_REG(RK3588_DSC_8K_CTRL0, 0x1, 28),
626
+	.dsc_ifep = VOP_REG(RK3588_DSC_8K_CTRL0, 0x1, 29),
627
+	.dsc_pps_upd = VOP_REG(RK3588_DSC_8K_CTRL0, 0x1, 31),
628
+	.dsc_status = VOP_REG(RK3588_DSC_8K_STS0, 0xffffffff, 0),
629
+	.dsc_ecw = VOP_REG(RK3588_DSC_8K_ERS, 0xffffffff, 0),
630
+};
631
+
632
+static const struct vop2_dsc_regs rk3588_vop_dsc_4k_regs = {
633
+	/* DSC SYS CTRL */
634
+	.dsc_port_sel = VOP_REG(RK3588_DSC_4K_SYS_CTRL, 0x3, 0),
635
+	.dsc_man_mode = VOP_REG(RK3588_DSC_4K_SYS_CTRL, 0x1, 2),
636
+	.dsc_interface_mode = VOP_REG(RK3588_DSC_4K_SYS_CTRL, 0x3, 4),
637
+	.dsc_pixel_num = VOP_REG(RK3588_DSC_4K_SYS_CTRL, 0x3, 6),
638
+	.dsc_pxl_clk_div = VOP_REG(RK3588_DSC_4K_SYS_CTRL, 0x1, 8),
639
+	.dsc_cds_clk_div = VOP_REG(RK3588_DSC_4K_SYS_CTRL, 0x3, 12),
640
+	.dsc_txp_clk_div = VOP_REG(RK3588_DSC_4K_SYS_CTRL, 0x3, 14),
641
+	.dsc_init_dly_mode = VOP_REG(RK3588_DSC_4K_SYS_CTRL, 0x1, 16),
642
+	.dsc_scan_en = VOP_REG(RK3588_DSC_4K_SYS_CTRL, 0x1, 17),
643
+	.dsc_halt_en = VOP_REG(RK3588_DSC_4K_SYS_CTRL, 0x1, 18),
644
+	.rst_deassert = VOP_REG(RK3588_DSC_4K_RST, 0x1, 0),
645
+	.dsc_flush = VOP_REG(RK3588_DSC_4K_RST, 0x1, 16),
646
+	.dsc_cfg_done = VOP_REG(RK3588_DSC_4K_CFG_DONE, 0x1, 0),
647
+	.dsc_init_dly_num = VOP_REG(RK3588_DSC_4K_INIT_DLY, 0xffff, 0),
648
+	.scan_timing_para_imd_en = VOP_REG(RK3588_DSC_4K_INIT_DLY, 0x1, 16),
649
+	.dsc_htotal_pw = VOP_REG(RK3588_DSC_4K_HTOTAL_HS_END, 0xffffffff, 0),
650
+	.dsc_hact_st_end = VOP_REG(RK3588_DSC_4K_HACT_ST_END, 0xffffffff, 0),
651
+	.dsc_vtotal = VOP_REG(RK3588_DSC_4K_VTOTAL_VS_END, 0xffff, 16),
652
+	.dsc_vs_end = VOP_REG(RK3588_DSC_4K_VTOTAL_VS_END, 0xffff, 0),
653
+	.dsc_vact_st_end = VOP_REG(RK3588_DSC_4K_VACT_ST_END, 0xffffffff, 0),
654
+	.dsc_error_status = VOP_REG(RK3588_DSC_4K_STATUS, 0x1, 0),
655
+
656
+	/* DSC encoder */
657
+	.dsc_pps0_3 = VOP_REG(RK3588_DSC_4K_PPS0_3, 0xffffffff, 0),
658
+	.dsc_en = VOP_REG(RK3588_DSC_4K_CTRL0, 0x1, 0),
659
+	.dsc_rbit = VOP_REG(RK3588_DSC_4K_CTRL0, 0x1, 2),
660
+	.dsc_rbyt = VOP_REG(RK3588_DSC_4K_CTRL0, 0x1, 3),
661
+	.dsc_flal = VOP_REG(RK3588_DSC_4K_CTRL0, 0x1, 4),
662
+	.dsc_mer = VOP_REG(RK3588_DSC_4K_CTRL0, 0x1, 5),
663
+	.dsc_epb = VOP_REG(RK3588_DSC_4K_CTRL0, 0x1, 6),
664
+	.dsc_epl = VOP_REG(RK3588_DSC_4K_CTRL0, 0x1, 7),
665
+	.dsc_nslc = VOP_REG(RK3588_DSC_4K_CTRL0, 0x7, 16),
666
+	.dsc_sbo = VOP_REG(RK3588_DSC_4K_CTRL0, 0x1, 28),
667
+	.dsc_ifep = VOP_REG(RK3588_DSC_4K_CTRL0, 0x1, 29),
668
+	.dsc_pps_upd = VOP_REG(RK3588_DSC_4K_CTRL0, 0x1, 31),
669
+	.dsc_status = VOP_REG(RK3588_DSC_4K_STS0, 0xffffffff, 0),
670
+	.dsc_ecw = VOP_REG(RK3588_DSC_4K_ERS, 0xffffffff, 0),
671
+};
672
+
673
+static const struct dsc_error_info dsc_ecw[] = {
674
+	{0x00000000, "no error detected by DSC encoder"},
675
+	{0x0030ffff, "bits per component error"},
676
+	{0x0040ffff, "multiple mode error"},
677
+	{0x0050ffff, "line buffer depth error"},
678
+	{0x0060ffff, "minor version error"},
679
+	{0x0070ffff, "picture height error"},
680
+	{0x0080ffff, "picture width error"},
681
+	{0x0090ffff, "number of slices error"},
682
+	{0x00c0ffff, "slice height Error "},
683
+	{0x00d0ffff, "slice width error"},
684
+	{0x00e0ffff, "second line BPG offset error"},
685
+	{0x00f0ffff, "non second line BPG offset error"},
686
+	{0x0100ffff, "PPS ID error"},
687
+	{0x0110ffff, "bits per pixel (BPP) Error"},
688
+	{0x0120ffff, "buffer flow error"},  /* dsc_buffer_flow */
689
+
690
+	{0x01510001, "slice 0 RC buffer model overflow error"},
691
+	{0x01510002, "slice 1 RC buffer model overflow error"},
692
+	{0x01510004, "slice 2 RC buffer model overflow error"},
693
+	{0x01510008, "slice 3 RC buffer model overflow error"},
694
+	{0x01510010, "slice 4 RC buffer model overflow error"},
695
+	{0x01510020, "slice 5 RC buffer model overflow error"},
696
+	{0x01510040, "slice 6 RC buffer model overflow error"},
697
+	{0x01510080, "slice 7 RC buffer model overflow error"},
698
+
699
+	{0x01610001, "slice 0 RC buffer model underflow error"},
700
+	{0x01610002, "slice 1 RC buffer model underflow error"},
701
+	{0x01610004, "slice 2 RC buffer model underflow error"},
702
+	{0x01610008, "slice 3 RC buffer model underflow error"},
703
+	{0x01610010, "slice 4 RC buffer model underflow error"},
704
+	{0x01610020, "slice 5 RC buffer model underflow error"},
705
+	{0x01610040, "slice 6 RC buffer model underflow error"},
706
+	{0x01610080, "slice 7 RC buffer model underflow error"},
707
+
708
+	{0xffffffff, "unsuccessful RESET cycle status"},
709
+	{0x00a0ffff, "ICH full error precision settings error"},
710
+	{0x0020ffff, "native mode"},
711
+};
712
+
713
+static const struct dsc_error_info dsc_buffer_flow[] = {
714
+	{0x00000000, "rate buffer status"},
715
+	{0x00000001, "line buffer status"},
716
+	{0x00000002, "decoder model status"},
717
+	{0x00000003, "pixel buffer status"},
718
+	{0x00000004, "balance fifo buffer status"},
719
+	{0x00000005, "syntax element fifo status"},
720
+};
721
+
722
+static const struct vop2_dsc_data rk3588_vop_dsc_data[] = {
723
+	{
724
+	 .id = ROCKCHIP_VOP2_DSC_8K,
725
+	 .pd_id = VOP2_PD_DSC_8K,
726
+	 .max_slice_num = 8,
727
+	 .max_linebuf_depth = 11,
728
+	 .min_bits_per_pixel = 8,
729
+	 .dsc_txp_clk_src_name = "dsc_8k_txp_clk_src",
730
+	 .dsc_txp_clk_name = "dsc_8k_txp_clk",
731
+	 .dsc_pxl_clk_name = "dsc_8k_pxl_clk",
732
+	 .dsc_cds_clk_name = "dsc_8k_cds_clk",
733
+	 .regs = &rk3588_vop_dsc_8k_regs,
734
+	},
735
+
736
+	{
737
+	 .id = ROCKCHIP_VOP2_DSC_4K,
738
+	 .pd_id = VOP2_PD_DSC_4K,
739
+	 .max_slice_num = 2,
740
+	 .max_linebuf_depth = 11,
741
+	 .min_bits_per_pixel = 8,
742
+	 .dsc_txp_clk_src_name = "dsc_4k_txp_clk_src",
743
+	 .dsc_txp_clk_name = "dsc_4k_txp_clk",
744
+	 .dsc_pxl_clk_name = "dsc_4k_pxl_clk",
745
+	 .dsc_cds_clk_name = "dsc_4k_cds_clk",
746
+	 .regs = &rk3588_vop_dsc_4k_regs,
747
+	},
748
+};
749
+
499750 static const struct vop2_wb_regs rk3568_vop_wb_regs = {
500751 	.enable = VOP_REG(RK3568_WB_CTRL, 0x1, 0),
501752 	.format = VOP_REG(RK3568_WB_CTRL, 0x7, 1),
....@@ -526,12 +777,13 @@
526777 	.dsp_background = VOP_REG(RK3568_VP0_DSP_BG, 0xffffffff, 0),
527778 	.out_mode = VOP_REG(RK3568_VP0_DSP_CTRL, 0xf, 0),
528779 	.core_dclk_div = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 4),
529
-	.dclk_div2 = VOP_REG(RK3568_VP0_MIPI_CTRL, 0x1, 4),
530
-	.dclk_div2_phase_lock = VOP_REG(RK3568_VP0_MIPI_CTRL, 0x1, 5),
780
+	.dclk_div2 = VOP_REG(RK3568_VP0_DUAL_CHANNEL_CTRL, 0x1, 4),
781
+	.dclk_div2_phase_lock = VOP_REG(RK3568_VP0_DUAL_CHANNEL_CTRL, 0x1, 5),
531782 	.p2i_en = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 5),
532783 	.dsp_filed_pol = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 6),
533784 	.dsp_interlace = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 7),
534785 	.dsp_data_swap = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1f, 8),
786
+	.dsp_x_mir_en = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 13),
535787 	.post_dsp_out_r2y = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 15),
536788 	.pre_dither_down_en = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 16),
537789 	.dither_down_en = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 17),
....@@ -549,7 +801,9 @@
549801 	.post_scl_ctrl = VOP_REG(RK3568_VP0_POST_SCL_CTRL, 0x3, 0),
550802 	.htotal_pw = VOP_REG(RK3568_VP0_DSP_HTOTAL_HS_END, 0xffffffff, 0),
551803 	.hact_st_end = VOP_REG(RK3568_VP0_DSP_HACT_ST_END, 0xffffffff, 0),
552
-	.vtotal_pw = VOP_REG(RK3568_VP0_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
804
+	.dsp_vtotal = VOP_REG(RK3568_VP0_DSP_VTOTAL_VS_END, 0x1fff, 16),
805
+	.sw_dsp_vtotal_imd = VOP_REG(RK3568_VP0_DSP_VTOTAL_VS_END, 0x1, 15),
806
+	.dsp_vs_end = VOP_REG(RK3568_VP0_DSP_VTOTAL_VS_END, 0x1fff, 0),
553807 	.vact_st_end = VOP_REG(RK3568_VP0_DSP_VACT_ST_END, 0x1fff1fff, 0),
554808 	.vact_st_end_f1 = VOP_REG(RK3568_VP0_DSP_VACT_ST_END_F1, 0x1fff1fff, 0),
555809 	.vs_st_end_f1 = VOP_REG(RK3568_VP0_DSP_VS_ST_END_F1, 0x1fff1fff, 0),
....@@ -591,6 +845,8 @@
591845 	.csc_offset0 = VOP_REG(RK3528_VP0_CSC_OFFSET0, 0xffffffff, 0),
592846 	.csc_offset1 = VOP_REG(RK3528_VP0_CSC_OFFSET1, 0xffffffff, 0),
593847 	.csc_offset2 = VOP_REG(RK3528_VP0_CSC_OFFSET2, 0xffffffff, 0),
848
+	.color_bar_mode = VOP_REG(RK3568_VP0_COLOR_BAR_CTRL, 0x1, 1),
849
+	.color_bar_en = VOP_REG(RK3568_VP0_COLOR_BAR_CTRL, 0x1, 0),
594850 };
595851 
596852 static const struct vop2_video_port_regs rk3528_vop_vp1_regs = {
....@@ -603,6 +859,7 @@
603859 	.dsp_filed_pol = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 6),
604860 	.dsp_interlace = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 7),
605861 	.dsp_data_swap = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1f, 8),
862
+	.dsp_x_mir_en = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 13),
606863 	.post_dsp_out_r2y = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 15),
607864 	.pre_dither_down_en = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 16),
608865 	.dither_down_en = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 17),
....@@ -620,7 +877,9 @@
620877 	.post_scl_ctrl = VOP_REG(RK3568_VP1_POST_SCL_CTRL, 0x3, 0),
621878 	.htotal_pw = VOP_REG(RK3568_VP1_DSP_HTOTAL_HS_END, 0xffffffff, 0),
622879 	.hact_st_end = VOP_REG(RK3568_VP1_DSP_HACT_ST_END, 0xffffffff, 0),
623
-	.vtotal_pw = VOP_REG(RK3568_VP1_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
880
+	.dsp_vtotal = VOP_REG(RK3568_VP1_DSP_VTOTAL_VS_END, 0x1fff, 16),
881
+	.sw_dsp_vtotal_imd = VOP_REG(RK3568_VP1_DSP_VTOTAL_VS_END, 0x1, 15),
882
+	.dsp_vs_end = VOP_REG(RK3568_VP1_DSP_VTOTAL_VS_END, 0x1fff, 0),
624883 	.vact_st_end = VOP_REG(RK3568_VP1_DSP_VACT_ST_END, 0x1fff1fff, 0),
625884 	.vact_st_end_f1 = VOP_REG(RK3568_VP1_DSP_VACT_ST_END_F1, 0x1fff1fff, 0),
626885 	.vs_st_end_f1 = VOP_REG(RK3568_VP1_DSP_VS_ST_END_F1, 0x1fff1fff, 0),
....@@ -638,6 +897,8 @@
638897 	.bcsh_en = VOP_REG(RK3568_VP1_BCSH_COLOR_BAR, 0x1, 31),
639898 	.lut_dma_rid = VOP_REG(RK3568_SYS_AXI_LUT_CTRL, 0xf, 4),
640899 	.layer_sel = VOP_REG(RK3528_OVL_PORT1_LAYER_SEL, 0xffff, 0),
900
+	.color_bar_mode = VOP_REG(RK3568_VP1_COLOR_BAR_CTRL, 0x1, 1),
901
+	.color_bar_en = VOP_REG(RK3568_VP1_COLOR_BAR_CTRL, 0x1, 0),
641902 };
642903 
643904 static const struct vop3_ovl_mix_regs rk3528_vop_hdr_mix_regs = {
....@@ -693,7 +954,6 @@
693954 	 .soc_id = { 0x3528, 0x3528 },
694955 	 .feature = VOP_FEATURE_ALPHA_SCALE | VOP_FEATURE_OVERSCAN,
695956 	 .max_output = { 720, 576 },
696
-	 .pre_scan_max_dly = { 37, 40, 40, 40 },
697957 	 .hdrvivid_dly = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
698958 	 .sdr2hdr_dly = 0,
699959 	 .layer_mix_dly = 2,
....@@ -705,6 +965,94 @@
705965 	},
706966 };
707967 
968
+static const struct vop2_video_port_regs rk3562_vop_vp0_regs = {
969
+	.cfg_done = VOP_REG(RK3568_REG_CFG_DONE, 0x1, 0),
970
+	.overlay_mode = VOP_REG(RK3528_OVL_PORT0_CTRL, 0x1, 0),
971
+	.dsp_background = VOP_REG(RK3568_VP0_DSP_BG, 0xffffffff, 0),
972
+	.out_mode = VOP_REG(RK3568_VP0_DSP_CTRL, 0xf, 0),
973
+	.core_dclk_div = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 4),
974
+	.p2i_en = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 5),
975
+	.dsp_filed_pol = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 6),
976
+	.dsp_interlace = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 7),
977
+	.dsp_data_swap = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1f, 8),
978
+	.dsp_x_mir_en = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 13),
979
+	.post_dsp_out_r2y = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 15),
980
+	.pre_dither_down_en = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 16),
981
+	.dither_down_en = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 17),
982
+	.dither_down_sel = VOP_REG(RK3568_VP0_DSP_CTRL, 0x3, 18),
983
+	.dither_down_mode = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 20),
984
+	.gamma_update_en = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 22),
985
+	.dsp_lut_en = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 28),
986
+	.standby = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 31),
987
+	.bg_mix_ctrl = VOP_REG(RK3528_OVL_PORT0_BG_MIX_CTRL, 0xffff, 0),
988
+	.bg_dly = VOP_REG(RK3528_OVL_PORT0_BG_MIX_CTRL, 0xff, 24),
989
+	.pre_scan_htiming = VOP_REG(RK3568_VP0_PRE_SCAN_HTIMING, 0x1fff1fff, 0),
990
+	.hpost_st_end = VOP_REG(RK3568_VP0_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
991
+	.vpost_st_end = VOP_REG(RK3568_VP0_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
992
+	.post_scl_factor = VOP_REG(RK3568_VP0_POST_SCL_FACTOR_YRGB, 0xffffffff, 0),
993
+	.post_scl_ctrl = VOP_REG(RK3568_VP0_POST_SCL_CTRL, 0x3, 0),
994
+	.htotal_pw = VOP_REG(RK3568_VP0_DSP_HTOTAL_HS_END, 0xffffffff, 0),
995
+	.hact_st_end = VOP_REG(RK3568_VP0_DSP_HACT_ST_END, 0xffffffff, 0),
996
+	.dsp_vtotal = VOP_REG(RK3568_VP0_DSP_VTOTAL_VS_END, 0x1fff, 16),
997
+	.sw_dsp_vtotal_imd = VOP_REG(RK3568_VP0_DSP_VTOTAL_VS_END, 0x1, 15),
998
+	.dsp_vs_end = VOP_REG(RK3568_VP0_DSP_VTOTAL_VS_END, 0x1fff, 0),
999
+	.vact_st_end = VOP_REG(RK3568_VP0_DSP_VACT_ST_END, 0x1fff1fff, 0),
1000
+	.vact_st_end_f1 = VOP_REG(RK3568_VP0_DSP_VACT_ST_END_F1, 0x1fff1fff, 0),
1001
+	.vs_st_end_f1 = VOP_REG(RK3568_VP0_DSP_VS_ST_END_F1, 0x1fff1fff, 0),
1002
+	.vpost_st_end_f1 = VOP_REG(RK3568_VP0_POST_DSP_VACT_INFO_F1, 0x1fff1fff, 0),
1003
+	.bcsh_brightness = VOP_REG(RK3568_VP0_BCSH_BCS, 0xff, 0),
1004
+	.bcsh_contrast = VOP_REG(RK3568_VP0_BCSH_BCS, 0x1ff, 8),
1005
+	.bcsh_sat_con = VOP_REG(RK3568_VP0_BCSH_BCS, 0x3ff, 20),
1006
+	.bcsh_out_mode = VOP_REG(RK3568_VP0_BCSH_BCS, 0x3, 30),
1007
+	.bcsh_sin_hue = VOP_REG(RK3568_VP0_BCSH_H, 0x1ff, 0),
1008
+	.bcsh_cos_hue = VOP_REG(RK3568_VP0_BCSH_H, 0x1ff, 16),
1009
+	.bcsh_r2y_csc_mode = VOP_REG(RK3568_VP0_BCSH_CTRL, 0x3, 6),
1010
+	.bcsh_r2y_en = VOP_REG(RK3568_VP0_BCSH_CTRL, 0x1, 4),
1011
+	.bcsh_y2r_csc_mode = VOP_REG(RK3568_VP0_BCSH_CTRL, 0x3, 2),
1012
+	.bcsh_y2r_en = VOP_REG(RK3568_VP0_BCSH_CTRL, 0x1, 0),
1013
+	.bcsh_en = VOP_REG(RK3568_VP0_BCSH_COLOR_BAR, 0x1, 31),
1014
+	.edpi_te_en = VOP_REG(RK3568_VP0_DUAL_CHANNEL_CTRL, 0x1, 28),
1015
+	.edpi_wms_hold_en = VOP_REG(RK3568_VP0_DUAL_CHANNEL_CTRL, 0x1, 30),
1016
+	.edpi_wms_fs = VOP_REG(RK3568_VP0_DUAL_CHANNEL_CTRL, 0x1, 31),
1017
+	.lut_dma_rid = VOP_REG(RK3568_SYS_AXI_LUT_CTRL, 0xf, 4),
1018
+	.cubic_lut_en = VOP_REG(RK3568_VP0_3D_LUT_CTRL, 0x1, 0),
1019
+	.cubic_lut_update_en = VOP_REG(RK3568_VP0_3D_LUT_CTRL, 0x1, 2),
1020
+	.cubic_lut_mst = VOP_REG(RK3568_VP0_3D_LUT_MST, 0xffffffff, 0),
1021
+
1022
+	.mcu_pix_total = VOP_REG(RK3562_VP0_MCU_CTRL, 0x3f, 0),
1023
+	.mcu_cs_pst = VOP_REG(RK3562_VP0_MCU_CTRL, 0xf, 6),
1024
+	.mcu_cs_pend = VOP_REG(RK3562_VP0_MCU_CTRL, 0x3f, 10),
1025
+	.mcu_rw_pst = VOP_REG(RK3562_VP0_MCU_CTRL, 0xf, 16),
1026
+	.mcu_rw_pend = VOP_REG(RK3562_VP0_MCU_CTRL, 0x3f, 20),
1027
+	.mcu_hold_mode = VOP_REG(RK3562_VP0_MCU_CTRL, 0x1, 27),
1028
+	.mcu_frame_st = VOP_REG(RK3562_VP0_MCU_CTRL, 0x1, 28),
1029
+	.mcu_rs = VOP_REG(RK3562_VP0_MCU_CTRL, 0x1, 29),
1030
+	.mcu_bypass = VOP_REG(RK3562_VP0_MCU_CTRL, 0x1, 30),
1031
+	.mcu_type = VOP_REG(RK3562_VP0_MCU_CTRL, 0x1, 31),
1032
+	.mcu_rw_bypass_port = VOP_REG(RK3562_VP0_MCU_RW_BYPASS_PORT, 0xffffffff, 0),
1033
+	.layer_sel = VOP_REG(RK3528_OVL_PORT0_LAYER_SEL, 0xffff, 0),
1034
+
1035
+	.color_bar_mode = VOP_REG(RK3568_VP0_COLOR_BAR_CTRL, 0x1, 1),
1036
+	.color_bar_en = VOP_REG(RK3568_VP0_COLOR_BAR_CTRL, 0x1, 0),
1037
+};
1038
+
1039
+static const struct vop2_video_port_data rk3562_vop_video_ports[] = {
1040
+	{
1041
+	 .id = 0,
1042
+	 .soc_id = { 0x3562, 0x3562 },
1043
+	 .lut_dma_rid = 14,
1044
+	 .feature = VOP_FEATURE_ALPHA_SCALE | VOP_FEATURE_OVERSCAN,
1045
+	 .gamma_lut_len = 1024,
1046
+	 .cubic_lut_len = 729, /* 9x9x9 */
1047
+	 .max_output = { 2048, 4096 },
1048
+	 .win_dly = 8,
1049
+	 .layer_mix_dly = 8,
1050
+	 .intr = &rk3568_vp0_intr,
1051
+	 .regs = &rk3562_vop_vp0_regs,
1052
+	 .ovl_regs = &rk3528_vop_vp0_ovl_regs,
1053
+	},
1054
+};
1055
+
7081056 static const struct vop2_video_port_regs rk3568_vop_vp0_regs = {
7091057 	.cfg_done = VOP_REG(RK3568_REG_CFG_DONE, 0x1, 0),
7101058 	.overlay_mode = VOP_REG(RK3568_OVL_CTRL, 0x1, 0),
....@@ -713,8 +1061,8 @@
7131061 	.out_mode = VOP_REG(RK3568_VP0_DSP_CTRL, 0xf, 0),
7141062 	.standby = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 31),
7151063 	.core_dclk_div = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 4),
716
-	.dclk_div2 = VOP_REG(RK3568_VP0_MIPI_CTRL, 0x1, 4),
717
-	.dclk_div2_phase_lock = VOP_REG(RK3568_VP0_MIPI_CTRL, 0x1, 5),
1064
+	.dclk_div2 = VOP_REG(RK3568_VP0_DUAL_CHANNEL_CTRL, 0x1, 4),
1065
+	.dclk_div2_phase_lock = VOP_REG(RK3568_VP0_DUAL_CHANNEL_CTRL, 0x1, 5),
7181066 	.p2i_en = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 5),
7191067 	.dsp_filed_pol = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 6),
7201068 	.dsp_interlace = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 7),
....@@ -729,7 +1077,8 @@
7291077 	.post_scl_factor = VOP_REG(RK3568_VP0_POST_SCL_FACTOR_YRGB, 0xffffffff, 0),
7301078 	.post_scl_ctrl = VOP_REG(RK3568_VP0_POST_SCL_CTRL, 0x3, 0),
7311079 	.hact_st_end = VOP_REG(RK3568_VP0_DSP_HACT_ST_END, 0x1fff1fff, 0),
732
-	.vtotal_pw = VOP_REG(RK3568_VP0_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
1080
+	.dsp_vtotal = VOP_REG(RK3568_VP0_DSP_VTOTAL_VS_END, 0x1fff, 16),
1081
+	.dsp_vs_end = VOP_REG(RK3568_VP0_DSP_VTOTAL_VS_END, 0x1fff, 0),
7331082 	.vact_st_end = VOP_REG(RK3568_VP0_DSP_VACT_ST_END, 0x1fff1fff, 0),
7341083 	.vact_st_end_f1 = VOP_REG(RK3568_VP0_DSP_VACT_ST_END_F1, 0x1fff1fff, 0),
7351084 	.vs_st_end_f1 = VOP_REG(RK3568_VP0_DSP_VS_ST_END_F1, 0x1fff1fff, 0),
....@@ -738,8 +1087,8 @@
7381087 	.dither_down_en = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 17),
7391088 	.dither_down_sel = VOP_REG(RK3568_VP0_DSP_CTRL, 0x3, 18),
7401089 	.dither_down_mode = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 20),
741
-	.mipi_dual_en = VOP_REG(RK3568_VP0_MIPI_CTRL, 0x1, 20),
742
-	.mipi_dual_channel_swap = VOP_REG(RK3568_VP0_MIPI_CTRL, 0x1, 21),
1090
+	.dual_channel_en = VOP_REG(RK3568_VP0_DUAL_CHANNEL_CTRL, 0x1, 20),
1091
+	.dual_channel_swap = VOP_REG(RK3568_VP0_DUAL_CHANNEL_CTRL, 0x1, 21),
7431092 	.dsp_lut_en = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 28),
7441093 	.hdr10_en = VOP_REG(RK3568_OVL_CTRL, 0x1, 4),
7451094 	.hdr_lut_update_en = VOP_REG(RK3568_HDR_LUT_CTRL, 0x1, 0),
....@@ -786,6 +1135,9 @@
7861135 	.cubic_lut_en = VOP_REG(RK3568_VP0_3D_LUT_CTRL, 0x1, 0),
7871136 	.cubic_lut_update_en = VOP_REG(RK3568_VP0_3D_LUT_CTRL, 0x1, 2),
7881137 	.cubic_lut_mst = VOP_REG(RK3568_VP0_3D_LUT_MST, 0xffffffff, 0),
1138
+
1139
+	.color_bar_mode = VOP_REG(RK3568_VP0_COLOR_BAR_CTRL, 0x1, 1),
1140
+	.color_bar_en = VOP_REG(RK3568_VP0_COLOR_BAR_CTRL, 0x1, 0),
7891141 };
7901142 
7911143 static const struct vop2_video_port_regs rk3568_vop_vp1_regs = {
....@@ -796,8 +1148,8 @@
7961148 	.out_mode = VOP_REG(RK3568_VP1_DSP_CTRL, 0xf, 0),
7971149 	.standby = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 31),
7981150 	.core_dclk_div = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 4),
799
-	.dclk_div2 = VOP_REG(RK3568_VP1_MIPI_CTRL, 0x1, 4),
800
-	.dclk_div2_phase_lock = VOP_REG(RK3568_VP1_MIPI_CTRL, 0x1, 5),
1151
+	.dclk_div2 = VOP_REG(RK3568_VP1_DUAL_CHANNEL_CTRL, 0x1, 4),
1152
+	.dclk_div2_phase_lock = VOP_REG(RK3568_VP1_DUAL_CHANNEL_CTRL, 0x1, 5),
8011153 	.p2i_en = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 5),
8021154 	.dsp_filed_pol = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 6),
8031155 	.dsp_interlace = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 7),
....@@ -812,7 +1164,8 @@
8121164 	.post_scl_factor = VOP_REG(RK3568_VP1_POST_SCL_FACTOR_YRGB, 0xffffffff, 0),
8131165 	.post_scl_ctrl = VOP_REG(RK3568_VP1_POST_SCL_CTRL, 0x3, 0),
8141166 	.hact_st_end = VOP_REG(RK3568_VP1_DSP_HACT_ST_END, 0x1fff1fff, 0),
815
-	.vtotal_pw = VOP_REG(RK3568_VP1_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
1167
+	.dsp_vtotal = VOP_REG(RK3568_VP1_DSP_VTOTAL_VS_END, 0x1fff, 16),
1168
+	.dsp_vs_end = VOP_REG(RK3568_VP1_DSP_VTOTAL_VS_END, 0x1fff, 0),
8161169 	.vact_st_end = VOP_REG(RK3568_VP1_DSP_VACT_ST_END, 0x1fff1fff, 0),
8171170 	.vact_st_end_f1 = VOP_REG(RK3568_VP1_DSP_VACT_ST_END_F1, 0x1fff1fff, 0),
8181171 	.vs_st_end_f1 = VOP_REG(RK3568_VP1_DSP_VS_ST_END_F1, 0x1fff1fff, 0),
....@@ -821,8 +1174,8 @@
8211174 	.dither_down_en = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 17),
8221175 	.dither_down_sel = VOP_REG(RK3568_VP1_DSP_CTRL, 0x3, 18),
8231176 	.dither_down_mode = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 20),
824
-	.mipi_dual_en = VOP_REG(RK3568_VP1_MIPI_CTRL, 0x1, 20),
825
-	.mipi_dual_channel_swap = VOP_REG(RK3568_VP1_MIPI_CTRL, 0x1, 21),
1177
+	.dual_channel_en = VOP_REG(RK3568_VP1_DUAL_CHANNEL_CTRL, 0x1, 20),
1178
+	.dual_channel_swap = VOP_REG(RK3568_VP1_DUAL_CHANNEL_CTRL, 0x1, 21),
8261179 
8271180 	.bcsh_brightness = VOP_REG(RK3568_VP1_BCSH_BCS, 0xff, 0),
8281181 	.bcsh_contrast = VOP_REG(RK3568_VP1_BCSH_BCS, 0x1ff, 8),
....@@ -836,6 +1189,9 @@
8361189 	.bcsh_y2r_en = VOP_REG(RK3568_VP1_BCSH_CTRL, 0x1, 0),
8371190 	.bcsh_en = VOP_REG(RK3568_VP1_BCSH_COLOR_BAR, 0x1, 31),
8381191 	.dsp_lut_en = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 28),
1192
+
1193
+	.color_bar_mode = VOP_REG(RK3568_VP1_COLOR_BAR_CTRL, 0x1, 1),
1194
+	.color_bar_en = VOP_REG(RK3568_VP1_COLOR_BAR_CTRL, 0x1, 0),
8391195 };
8401196 
8411197 static const struct vop2_video_port_regs rk3568_vop_vp2_regs = {
....@@ -846,8 +1202,8 @@
8461202 	.out_mode = VOP_REG(RK3568_VP2_DSP_CTRL, 0xf, 0),
8471203 	.standby = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 31),
8481204 	.core_dclk_div = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 4),
849
-	.dclk_div2 = VOP_REG(RK3568_VP2_MIPI_CTRL, 0x1, 4),
850
-	.dclk_div2_phase_lock = VOP_REG(RK3568_VP2_MIPI_CTRL, 0x1, 5),
1205
+	.dclk_div2 = VOP_REG(RK3568_VP2_DUAL_CHANNEL_CTRL, 0x1, 4),
1206
+	.dclk_div2_phase_lock = VOP_REG(RK3568_VP2_DUAL_CHANNEL_CTRL, 0x1, 5),
8511207 	.p2i_en = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 5),
8521208 	.dsp_filed_pol = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 6),
8531209 	.dsp_interlace = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 7),
....@@ -862,7 +1218,8 @@
8621218 	.post_scl_ctrl = VOP_REG(RK3568_VP2_POST_SCL_CTRL, 0x3, 0),
8631219 	.htotal_pw = VOP_REG(RK3568_VP2_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
8641220 	.hact_st_end = VOP_REG(RK3568_VP2_DSP_HACT_ST_END, 0x1fff1fff, 0),
865
-	.vtotal_pw = VOP_REG(RK3568_VP2_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
1221
+	.dsp_vtotal = VOP_REG(RK3568_VP2_DSP_VTOTAL_VS_END, 0x1fff, 16),
1222
+	.dsp_vs_end = VOP_REG(RK3568_VP2_DSP_VTOTAL_VS_END, 0x1fff, 0),
8661223 	.vact_st_end = VOP_REG(RK3568_VP2_DSP_VACT_ST_END, 0x1fff1fff, 0),
8671224 	.vact_st_end_f1 = VOP_REG(RK3568_VP2_DSP_VACT_ST_END_F1, 0x1fff1fff, 0),
8681225 	.vs_st_end_f1 = VOP_REG(RK3568_VP2_DSP_VS_ST_END_F1, 0x1fff1fff, 0),
....@@ -871,8 +1228,8 @@
8711228 	.dither_down_en = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 17),
8721229 	.dither_down_sel = VOP_REG(RK3568_VP2_DSP_CTRL, 0x3, 18),
8731230 	.dither_down_mode = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 20),
874
-	.mipi_dual_en = VOP_REG(RK3568_VP2_MIPI_CTRL, 0x1, 20),
875
-	.mipi_dual_channel_swap = VOP_REG(RK3568_VP2_MIPI_CTRL, 0x1, 21),
1231
+	.dual_channel_en = VOP_REG(RK3568_VP2_DUAL_CHANNEL_CTRL, 0x1, 20),
1232
+	.dual_channel_swap = VOP_REG(RK3568_VP2_DUAL_CHANNEL_CTRL, 0x1, 21),
8761233 
8771234 	.bcsh_brightness = VOP_REG(RK3568_VP2_BCSH_BCS, 0xff, 0),
8781235 	.bcsh_contrast = VOP_REG(RK3568_VP2_BCSH_BCS, 0x1ff, 8),
....@@ -886,16 +1243,20 @@
8861243 	.bcsh_y2r_en = VOP_REG(RK3568_VP2_BCSH_CTRL, 0x1, 0),
8871244 	.bcsh_en = VOP_REG(RK3568_VP2_BCSH_COLOR_BAR, 0x1, 31),
8881245 	.dsp_lut_en = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 28),
1246
+
1247
+	.color_bar_mode = VOP_REG(RK3568_VP2_COLOR_BAR_CTRL, 0x1, 1),
1248
+	.color_bar_en = VOP_REG(RK3568_VP2_COLOR_BAR_CTRL, 0x1, 0),
8891249 };
8901250 
8911251 static const struct vop2_video_port_data rk3568_vop_video_ports[] = {
8921252 	{
8931253 	 .id = 0,
8941254 	 .soc_id = { 0x3568, 0x3566 },
895
-	 .feature = VOP_FEATURE_OUTPUT_10BIT,
1255
+	 .feature = VOP_FEATURE_OUTPUT_10BIT | VOP_FEATURE_ALPHA_SCALE |
1256
+			VOP_FEATURE_HDR10 | VOP_FEATURE_OVERSCAN,
8961257 	 .gamma_lut_len = 1024,
8971258 	 .cubic_lut_len = 729, /* 9x9x9 */
898
-	 .max_output = { 4096, 2304 },
1259
+	 .max_output = { 4096, 4096 },
8991260 	 .pre_scan_max_dly = { 69, 53, 53, 42 },
9001261 	 .intr = &rk3568_vp0_intr,
9011262 	 .hdr_table = &rk3568_vop_hdr_table,
....@@ -904,22 +1265,532 @@
9041265 	{
9051266 	 .id = 1,
9061267 	 .soc_id = { 0x3568, 0x3566 },
1268
+	 .feature = VOP_FEATURE_ALPHA_SCALE | VOP_FEATURE_OVERSCAN,
9071269 	 .gamma_lut_len = 1024,
908
-	 .max_output = { 2048, 1536 },
1270
+	 .max_output = { 2048, 2048 },
9091271 	 .pre_scan_max_dly = { 40, 40, 40, 40 },
9101272 	 .intr = &rk3568_vp1_intr,
9111273 	 .regs = &rk3568_vop_vp1_regs,
9121274 	},
9131275 	{
9141276 	 .id = 2,
1277
+	 .feature = VOP_FEATURE_ALPHA_SCALE | VOP_FEATURE_OVERSCAN,
9151278 	 .soc_id = { 0x3568, 0x3566 },
9161279 	 .gamma_lut_len = 1024,
917
-	 .max_output = { 1920, 1080 },
1280
+	 .max_output = { 1920, 1920 },
9181281 	 .pre_scan_max_dly = { 40, 40, 40, 40 },
9191282 	 .intr = &rk3568_vp2_intr,
9201283 	 .regs = &rk3568_vop_vp2_regs,
9211284 	},
9221285 };
1286
+
1287
+static const struct vop2_video_port_regs rk3588_vop_vp0_regs = {
1288
+	.cfg_done = VOP_REG(RK3568_REG_CFG_DONE, 0x1, 0),
1289
+	.overlay_mode = VOP_REG(RK3568_OVL_CTRL, 0x1, 0),
1290
+	.dsp_background = VOP_REG(RK3568_VP0_DSP_BG, 0xffffffff, 0),
1291
+	.port_mux = VOP_REG(RK3568_OVL_PORT_SEL, 0xf, 0),
1292
+	.out_mode = VOP_REG(RK3568_VP0_DSP_CTRL, 0xf, 0),
1293
+	.p2i_en = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 5),
1294
+	.dsp_filed_pol = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 6),
1295
+	.dsp_interlace = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 7),
1296
+	.dsp_data_swap = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1f, 8),
1297
+	.dsp_x_mir_en = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 13),
1298
+	.post_dsp_out_r2y = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 15),
1299
+	.pre_dither_down_en = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 16),
1300
+	.dither_down_en = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 17),
1301
+	.dither_down_sel = VOP_REG(RK3568_VP0_DSP_CTRL, 0x3, 18),
1302
+	.dither_down_mode = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 20),
1303
+	.gamma_update_en = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 22),
1304
+	.dsp_lut_en = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 28),
1305
+	.standby = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 31),
1306
+	.dclk_src_sel = VOP_REG(RK3568_LUT_PORT_SEL, 0x1, 30),
1307
+	.splice_en = VOP_REG(RK3568_LUT_PORT_SEL, 0x1, 16),
1308
+	.dclk_core_div = VOP_REG(RK3568_VP0_CLK_CTRL, 0x3, 0),
1309
+	.dclk_out_div = VOP_REG(RK3568_VP0_CLK_CTRL, 0x3, 2),
1310
+	.pre_scan_htiming = VOP_REG(RK3568_VP0_PRE_SCAN_HTIMING, 0x1fff1fff, 0),
1311
+	.bg_dly = VOP_REG(RK3568_VP0_BG_MIX_CTRL, 0xff, 24),
1312
+	.hpost_st_end = VOP_REG(RK3568_VP0_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
1313
+	.vpost_st_end = VOP_REG(RK3568_VP0_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
1314
+	.post_scl_factor = VOP_REG(RK3568_VP0_POST_SCL_FACTOR_YRGB, 0xffffffff, 0),
1315
+	.post_scl_ctrl = VOP_REG(RK3568_VP0_POST_SCL_CTRL, 0x3, 0),
1316
+	.htotal_pw = VOP_REG(RK3568_VP0_DSP_HTOTAL_HS_END, 0xffffffff, 0),
1317
+	.hact_st_end = VOP_REG(RK3568_VP0_DSP_HACT_ST_END, 0xffffffff, 0),
1318
+	.dsp_vtotal = VOP_REG(RK3568_VP0_DSP_VTOTAL_VS_END, 0x1fff, 16),
1319
+	.sw_dsp_vtotal_imd = VOP_REG(RK3568_VP0_DSP_VTOTAL_VS_END, 0x1, 15),
1320
+	.dsp_vs_end = VOP_REG(RK3568_VP0_DSP_VTOTAL_VS_END, 0x1fff, 0),
1321
+	.vact_st_end = VOP_REG(RK3568_VP0_DSP_VACT_ST_END, 0x1fff1fff, 0),
1322
+	.vact_st_end_f1 = VOP_REG(RK3568_VP0_DSP_VACT_ST_END_F1, 0x1fff1fff, 0),
1323
+	.vs_st_end_f1 = VOP_REG(RK3568_VP0_DSP_VS_ST_END_F1, 0x1fff1fff, 0),
1324
+	.vpost_st_end_f1 = VOP_REG(RK3568_VP0_POST_DSP_VACT_INFO_F1, 0x1fff1fff, 0),
1325
+	.dual_channel_en = VOP_REG(RK3568_VP0_DUAL_CHANNEL_CTRL, 0x1, 20),
1326
+	.dual_channel_swap = VOP_REG(RK3568_VP0_DUAL_CHANNEL_CTRL, 0x1, 21),
1327
+	.hdr10_en = VOP_REG(RK3568_OVL_CTRL, 0x1, 4),
1328
+	.hdr_lut_update_en = VOP_REG(RK3568_HDR_LUT_CTRL, 0x1, 0),
1329
+	.hdr_lut_mode = VOP_REG(RK3568_HDR_LUT_CTRL, 0x1, 1),
1330
+	.hdr_lut_mst = VOP_REG(RK3568_HDR_LUT_MST, 0xffffffff, 0),
1331
+	.sdr2hdr_eotf_en = VOP_REG(RK3568_SDR2HDR_CTRL, 0x1, 0),
1332
+	.sdr2hdr_r2r_en = VOP_REG(RK3568_SDR2HDR_CTRL, 0x1, 1),
1333
+	.sdr2hdr_r2r_mode = VOP_REG(RK3568_SDR2HDR_CTRL, 0x1, 2),
1334
+	.sdr2hdr_oetf_en = VOP_REG(RK3568_SDR2HDR_CTRL, 0x1, 3),
1335
+	.sdr2hdr_bypass_en = VOP_REG(RK3568_SDR2HDR_CTRL, 0x1, 8),
1336
+	.sdr2hdr_auto_gating_en = VOP_REG(RK3568_SDR2HDR_CTRL, 0x1, 9),
1337
+	.sdr2hdr_path_en = VOP_REG(RK3568_OVL_CTRL, 0x1, 5),
1338
+	.hdr2sdr_en = VOP_REG(RK3568_HDR2SDR_CTRL, 0x1, 0),
1339
+	.hdr2sdr_bypass_en = VOP_REG(RK3568_HDR2SDR_CTRL, 0x1, 8),
1340
+	.hdr2sdr_auto_gating_en = VOP_REG(RK3568_HDR2SDR_CTRL, 0x1, 9),
1341
+	.hdr2sdr_src_min = VOP_REG(RK3568_HDR2SDR_SRC_RANGE, 0x3fff, 0),
1342
+	.hdr2sdr_src_max = VOP_REG(RK3568_HDR2SDR_SRC_RANGE, 0x3fff, 16),
1343
+	.hdr2sdr_normfaceetf = VOP_REG(RK3568_HDR2SDR_NORMFACEETF, 0x7ff, 0),
1344
+	.hdr2sdr_dst_min = VOP_REG(RK3568_HDR2SDR_DST_RANGE, 0xffff, 0),
1345
+	.hdr2sdr_dst_max = VOP_REG(RK3568_HDR2SDR_DST_RANGE, 0xffff, 16),
1346
+	.hdr2sdr_normfacgamma = VOP_REG(RK3568_HDR2SDR_NORMFACCGAMMA, 0xffff, 0),
1347
+	.hdr2sdr_eetf_oetf_y0_offset = RK3568_HDR_EETF_OETF_Y0,
1348
+	.hdr2sdr_sat_y0_offset = RK3568_HDR_SAT_Y0,
1349
+	.sdr2hdr_eotf_oetf_y0_offset = RK3568_HDR_EOTF_OETF_Y0,
1350
+	.sdr2hdr_oetf_dx_pow1_offset = RK3568_HDR_OETF_DX_POW1,
1351
+	.sdr2hdr_oetf_xn1_offset = RK3568_HDR_OETF_XN1,
1352
+	.hdr_src_color_ctrl = VOP_REG(RK3568_HDR0_SRC_COLOR_CTRL, 0xffffffff, 0),
1353
+	.hdr_dst_color_ctrl = VOP_REG(RK3568_HDR0_DST_COLOR_CTRL, 0xffffffff, 0),
1354
+	.hdr_src_alpha_ctrl = VOP_REG(RK3568_HDR0_SRC_ALPHA_CTRL, 0xffffffff, 0),
1355
+	.hdr_dst_alpha_ctrl = VOP_REG(RK3568_HDR0_DST_ALPHA_CTRL, 0xffffffff, 0),
1356
+
1357
+	.bcsh_brightness = VOP_REG(RK3568_VP0_BCSH_BCS, 0xff, 0),
1358
+	.bcsh_contrast = VOP_REG(RK3568_VP0_BCSH_BCS, 0x1ff, 8),
1359
+	.bcsh_sat_con = VOP_REG(RK3568_VP0_BCSH_BCS, 0x3ff, 20),
1360
+	.bcsh_out_mode = VOP_REG(RK3568_VP0_BCSH_BCS, 0x3, 30),
1361
+	.bcsh_sin_hue = VOP_REG(RK3568_VP0_BCSH_H, 0x1ff, 0),
1362
+	.bcsh_cos_hue = VOP_REG(RK3568_VP0_BCSH_H, 0x1ff, 16),
1363
+	.bcsh_r2y_csc_mode = VOP_REG(RK3568_VP0_BCSH_CTRL, 0x3, 6),
1364
+	.bcsh_r2y_en = VOP_REG(RK3568_VP0_BCSH_CTRL, 0x1, 4),
1365
+	.bcsh_y2r_csc_mode = VOP_REG(RK3568_VP0_BCSH_CTRL, 0x3, 2),
1366
+	.bcsh_y2r_en = VOP_REG(RK3568_VP0_BCSH_CTRL, 0x1, 0),
1367
+	.bcsh_en = VOP_REG(RK3568_VP0_BCSH_COLOR_BAR, 0x1, 31),
1368
+	.edpi_te_en = VOP_REG(RK3568_VP0_DUAL_CHANNEL_CTRL, 0x1, 28),
1369
+	.edpi_wms_hold_en = VOP_REG(RK3568_VP0_DUAL_CHANNEL_CTRL, 0x1, 30),
1370
+	.edpi_wms_fs = VOP_REG(RK3568_VP0_DUAL_CHANNEL_CTRL, 0x1, 31),
1371
+
1372
+	.lut_dma_rid = VOP_REG(RK3568_SYS_AXI_LUT_CTRL, 0xf, 4),
1373
+	.cubic_lut_en = VOP_REG(RK3568_VP0_3D_LUT_CTRL, 0x1, 0),
1374
+	.cubic_lut_update_en = VOP_REG(RK3568_VP0_3D_LUT_CTRL, 0x1, 2),
1375
+	.cubic_lut_mst = VOP_REG(RK3568_VP0_3D_LUT_MST, 0xffffffff, 0),
1376
+
1377
+	.line_flag_or_en = VOP_REG(RK3588_SYS_VAR_FREQ_CTRL, 0x1, 20),
1378
+	.dsp_hold_or_en = VOP_REG(RK3588_SYS_VAR_FREQ_CTRL, 0x1, 24),
1379
+	.almost_full_or_en = VOP_REG(RK3588_SYS_VAR_FREQ_CTRL, 0x1, 28),
1380
+
1381
+	.color_bar_mode = VOP_REG(RK3568_VP0_COLOR_BAR_CTRL, 0x1, 1),
1382
+	.color_bar_en = VOP_REG(RK3568_VP0_COLOR_BAR_CTRL, 0x1, 0),
1383
+};
1384
+
1385
+/*
1386
+ * VP1 can splice with VP0 to output hdisplay > 4096,
1387
+ * VP1 has a another HDR10 controller, but share the
1388
+ * same eotf curve with VP1.
1389
+ */
1390
+static const struct vop2_video_port_regs rk3588_vop_vp1_regs = {
1391
+	.cfg_done = VOP_REG(RK3568_REG_CFG_DONE, 0x1, 1),
1392
+	.overlay_mode = VOP_REG(RK3568_OVL_CTRL, 0x1, 1),
1393
+	.dsp_background = VOP_REG(RK3568_VP1_DSP_BG, 0xffffffff, 0),
1394
+	.port_mux = VOP_REG(RK3568_OVL_PORT_SEL, 0xf, 4),
1395
+	.out_mode = VOP_REG(RK3568_VP1_DSP_CTRL, 0xf, 0),
1396
+	.p2i_en = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 5),
1397
+	.dsp_filed_pol = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 6),
1398
+	.dsp_interlace = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 7),
1399
+	.dsp_data_swap = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1f, 8),
1400
+	.dsp_x_mir_en = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 13),
1401
+	.post_dsp_out_r2y = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 15),
1402
+	.pre_dither_down_en = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 16),
1403
+	.dither_down_en = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 17),
1404
+	.dither_down_sel = VOP_REG(RK3568_VP1_DSP_CTRL, 0x3, 18),
1405
+	.dither_down_mode = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 20),
1406
+	.gamma_update_en = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 22),
1407
+	.dsp_lut_en = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 28),
1408
+	.standby = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 31),
1409
+	.dclk_core_div = VOP_REG(RK3568_VP1_CLK_CTRL, 0x3, 0),
1410
+	.dclk_out_div = VOP_REG(RK3568_VP1_CLK_CTRL, 0x3, 2),
1411
+	.pre_scan_htiming = VOP_REG(RK3568_VP1_PRE_SCAN_HTIMING, 0x1fff1fff, 0),
1412
+	.bg_dly = VOP_REG(RK3568_VP1_BG_MIX_CTRL, 0xff, 24),
1413
+	.hpost_st_end = VOP_REG(RK3568_VP1_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
1414
+	.vpost_st_end = VOP_REG(RK3568_VP1_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
1415
+	.post_scl_factor = VOP_REG(RK3568_VP1_POST_SCL_FACTOR_YRGB, 0xffffffff, 0),
1416
+	.post_scl_ctrl = VOP_REG(RK3568_VP1_POST_SCL_CTRL, 0x3, 0),
1417
+	.htotal_pw = VOP_REG(RK3568_VP1_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
1418
+	.hact_st_end = VOP_REG(RK3568_VP1_DSP_HACT_ST_END, 0x1fff1fff, 0),
1419
+	.dsp_vtotal = VOP_REG(RK3568_VP1_DSP_VTOTAL_VS_END, 0x1fff, 16),
1420
+	.sw_dsp_vtotal_imd = VOP_REG(RK3568_VP1_DSP_VTOTAL_VS_END, 0x1, 15),
1421
+	.dsp_vs_end = VOP_REG(RK3568_VP1_DSP_VTOTAL_VS_END, 0x1fff, 0),
1422
+	.vact_st_end = VOP_REG(RK3568_VP1_DSP_VACT_ST_END, 0x1fff1fff, 0),
1423
+	.vact_st_end_f1 = VOP_REG(RK3568_VP1_DSP_VACT_ST_END_F1, 0x1fff1fff, 0),
1424
+	.vs_st_end_f1 = VOP_REG(RK3568_VP1_DSP_VS_ST_END_F1, 0x1fff1fff, 0),
1425
+	.vpost_st_end_f1 = VOP_REG(RK3568_VP1_POST_DSP_VACT_INFO_F1, 0x1fff1fff, 0),
1426
+	.dual_channel_en = VOP_REG(RK3568_VP1_DUAL_CHANNEL_CTRL, 0x1, 20),
1427
+	.dual_channel_swap = VOP_REG(RK3568_VP1_DUAL_CHANNEL_CTRL, 0x1, 21),
1428
+	.hdr10_en = VOP_REG(RK3568_OVL_CTRL, 0x1, 24),
1429
+	.hdr_lut_update_en = VOP_REG(RK3568_HDR_LUT_CTRL, 0x1, 0),
1430
+	.hdr_lut_mode = VOP_REG(RK3568_HDR_LUT_CTRL, 0x1, 1),
1431
+	.hdr_lut_mst = VOP_REG(RK3568_HDR_LUT_MST, 0xffffffff, 0),
1432
+	.sdr2hdr_eotf_en = VOP_REG(RK3568_SDR2HDR_CTRL1, 0x1, 0),
1433
+	.sdr2hdr_r2r_en = VOP_REG(RK3568_SDR2HDR_CTRL1, 0x1, 1),
1434
+	.sdr2hdr_r2r_mode = VOP_REG(RK3568_SDR2HDR_CTRL1, 0x1, 2),
1435
+	.sdr2hdr_oetf_en = VOP_REG(RK3568_SDR2HDR_CTRL1, 0x1, 3),
1436
+	.sdr2hdr_bypass_en = VOP_REG(RK3568_SDR2HDR_CTRL1, 0x1, 8),
1437
+	.sdr2hdr_auto_gating_en = VOP_REG(RK3568_SDR2HDR_CTRL1, 0x1, 9),
1438
+	.sdr2hdr_path_en = VOP_REG(RK3568_OVL_CTRL, 0x1, 25),
1439
+	.hdr2sdr_en = VOP_REG(RK3568_HDR2SDR_CTRL1, 0x1, 0),
1440
+	.hdr2sdr_bypass_en = VOP_REG(RK3568_HDR2SDR_CTRL1, 0x1, 8),
1441
+	.hdr2sdr_auto_gating_en = VOP_REG(RK3568_HDR2SDR_CTRL1, 0x1, 9),
1442
+	.hdr2sdr_src_min = VOP_REG(RK3568_HDR2SDR_SRC_RANGE, 0x3fff, 0),
1443
+	.hdr2sdr_src_max = VOP_REG(RK3568_HDR2SDR_SRC_RANGE, 0x3fff, 16),
1444
+	.hdr2sdr_normfaceetf = VOP_REG(RK3568_HDR2SDR_NORMFACEETF, 0x7ff, 0),
1445
+	.hdr2sdr_dst_min = VOP_REG(RK3568_HDR2SDR_DST_RANGE, 0xffff, 0),
1446
+	.hdr2sdr_dst_max = VOP_REG(RK3568_HDR2SDR_DST_RANGE, 0xffff, 16),
1447
+	.hdr2sdr_normfacgamma = VOP_REG(RK3568_HDR2SDR_NORMFACCGAMMA, 0xffff, 0),
1448
+	.hdr2sdr_eetf_oetf_y0_offset = RK3568_HDR_EETF_OETF_Y0,
1449
+	.hdr2sdr_sat_y0_offset = RK3568_HDR_SAT_Y0,
1450
+	.sdr2hdr_eotf_oetf_y0_offset = RK3568_HDR_EOTF_OETF_Y0,
1451
+	.sdr2hdr_oetf_dx_pow1_offset = RK3568_HDR_OETF_DX_POW1,
1452
+	.sdr2hdr_oetf_xn1_offset = RK3568_HDR_OETF_XN1,
1453
+	.hdr_src_color_ctrl = VOP_REG(RK3568_HDR1_SRC_COLOR_CTRL, 0xffffffff, 0),
1454
+	.hdr_dst_color_ctrl = VOP_REG(RK3568_HDR1_DST_COLOR_CTRL, 0xffffffff, 0),
1455
+	.hdr_src_alpha_ctrl = VOP_REG(RK3568_HDR1_SRC_ALPHA_CTRL, 0xffffffff, 0),
1456
+	.hdr_dst_alpha_ctrl = VOP_REG(RK3568_HDR1_DST_ALPHA_CTRL, 0xffffffff, 0),
1457
+
1458
+	.bcsh_brightness = VOP_REG(RK3568_VP1_BCSH_BCS, 0xff, 0),
1459
+	.bcsh_contrast = VOP_REG(RK3568_VP1_BCSH_BCS, 0x1ff, 8),
1460
+	.bcsh_sat_con = VOP_REG(RK3568_VP1_BCSH_BCS, 0x3ff, 20),
1461
+	.bcsh_out_mode = VOP_REG(RK3568_VP1_BCSH_BCS, 0x3, 30),
1462
+	.bcsh_sin_hue = VOP_REG(RK3568_VP1_BCSH_H, 0x1ff, 0),
1463
+	.bcsh_cos_hue = VOP_REG(RK3568_VP1_BCSH_H, 0x1ff, 16),
1464
+	.bcsh_r2y_csc_mode = VOP_REG(RK3568_VP1_BCSH_CTRL, 0x3, 6),
1465
+	.bcsh_r2y_en = VOP_REG(RK3568_VP1_BCSH_CTRL, 0x1, 4),
1466
+	.bcsh_y2r_csc_mode = VOP_REG(RK3568_VP1_BCSH_CTRL, 0x3, 2),
1467
+	.bcsh_y2r_en = VOP_REG(RK3568_VP1_BCSH_CTRL, 0x1, 0),
1468
+	.bcsh_en = VOP_REG(RK3568_VP1_BCSH_COLOR_BAR, 0x1, 31),
1469
+	.edpi_te_en = VOP_REG(RK3568_VP1_DUAL_CHANNEL_CTRL, 0x1, 28),
1470
+	.edpi_wms_hold_en = VOP_REG(RK3568_VP1_DUAL_CHANNEL_CTRL, 0x1, 30),
1471
+	.edpi_wms_fs = VOP_REG(RK3568_VP1_DUAL_CHANNEL_CTRL, 0x1, 31),
1472
+
1473
+	.lut_dma_rid = VOP_REG(RK3568_SYS_AXI_LUT_CTRL, 0xf, 4),
1474
+	.cubic_lut_en = VOP_REG(RK3588_VP1_3D_LUT_CTRL, 0x1, 0),
1475
+	.cubic_lut_update_en = VOP_REG(RK3588_VP1_3D_LUT_CTRL, 0x1, 2),
1476
+	.cubic_lut_mst = VOP_REG(RK3588_VP1_3D_LUT_MST, 0xffffffff, 0),
1477
+
1478
+	.line_flag_or_en = VOP_REG(RK3588_SYS_VAR_FREQ_CTRL, 0x1, 21),
1479
+	.dsp_hold_or_en = VOP_REG(RK3588_SYS_VAR_FREQ_CTRL, 0x1, 25),
1480
+	.almost_full_or_en = VOP_REG(RK3588_SYS_VAR_FREQ_CTRL, 0x1, 29),
1481
+
1482
+	.color_bar_mode = VOP_REG(RK3568_VP1_COLOR_BAR_CTRL, 0x1, 1),
1483
+	.color_bar_en = VOP_REG(RK3568_VP1_COLOR_BAR_CTRL, 0x1, 0),
1484
+};
1485
+
1486
+static const struct vop2_video_port_regs rk3588_vop_vp2_regs = {
1487
+	.cfg_done = VOP_REG(RK3568_REG_CFG_DONE, 0x1, 2),
1488
+	.overlay_mode = VOP_REG(RK3568_OVL_CTRL, 0x1, 2),
1489
+	.dsp_background = VOP_REG(RK3568_VP2_DSP_BG, 0xffffffff, 0),
1490
+	.port_mux = VOP_REG(RK3568_OVL_PORT_SEL, 0xf, 8),
1491
+	.out_mode = VOP_REG(RK3568_VP2_DSP_CTRL, 0xf, 0),
1492
+	.p2i_en = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 5),
1493
+	.dsp_filed_pol = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 6),
1494
+	.dsp_interlace = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 7),
1495
+	.dsp_data_swap = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1f, 8),
1496
+	.dsp_x_mir_en = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 13),
1497
+	.post_dsp_out_r2y = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 15),
1498
+	.pre_dither_down_en = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 16),
1499
+	.dither_down_en = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 17),
1500
+	.dither_down_sel = VOP_REG(RK3568_VP2_DSP_CTRL, 0x3, 18),
1501
+	.dither_down_mode = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 20),
1502
+	.gamma_update_en = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 22),
1503
+	.dsp_lut_en = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 28),
1504
+	.standby = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 31),
1505
+	.dclk_src_sel = VOP_REG(RK3568_LUT_PORT_SEL, 0x1, 31),
1506
+	.dclk_core_div = VOP_REG(RK3568_VP2_CLK_CTRL, 0x3, 0),
1507
+	.dclk_out_div = VOP_REG(RK3568_VP2_CLK_CTRL, 0x3, 2),
1508
+	.pre_scan_htiming = VOP_REG(RK3568_VP2_PRE_SCAN_HTIMING, 0x1fff1fff, 0),
1509
+	.bg_dly = VOP_REG(RK3568_VP2_BG_MIX_CTRL, 0xff, 24),
1510
+	.hpost_st_end = VOP_REG(RK3568_VP2_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
1511
+	.vpost_st_end = VOP_REG(RK3568_VP2_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
1512
+	.post_scl_factor = VOP_REG(RK3568_VP2_POST_SCL_FACTOR_YRGB, 0xffffffff, 0),
1513
+	.post_scl_ctrl = VOP_REG(RK3568_VP2_POST_SCL_CTRL, 0x3, 0),
1514
+	.htotal_pw = VOP_REG(RK3568_VP2_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
1515
+	.hact_st_end = VOP_REG(RK3568_VP2_DSP_HACT_ST_END, 0x1fff1fff, 0),
1516
+	.dsp_vtotal = VOP_REG(RK3568_VP2_DSP_VTOTAL_VS_END, 0x1fff, 16),
1517
+	.sw_dsp_vtotal_imd = VOP_REG(RK3568_VP2_DSP_VTOTAL_VS_END, 0x1, 15),
1518
+	.dsp_vs_end = VOP_REG(RK3568_VP2_DSP_VTOTAL_VS_END, 0x1fff, 0),
1519
+	.vact_st_end = VOP_REG(RK3568_VP2_DSP_VACT_ST_END, 0x1fff1fff, 0),
1520
+	.vact_st_end_f1 = VOP_REG(RK3568_VP2_DSP_VACT_ST_END_F1, 0x1fff1fff, 0),
1521
+	.vs_st_end_f1 = VOP_REG(RK3568_VP2_DSP_VS_ST_END_F1, 0x1fff1fff, 0),
1522
+	.vpost_st_end_f1 = VOP_REG(RK3568_VP2_POST_DSP_VACT_INFO_F1, 0x1fff1fff, 0),
1523
+	.dual_channel_en = VOP_REG(RK3568_VP2_DUAL_CHANNEL_CTRL, 0x1, 20),
1524
+	.dual_channel_swap = VOP_REG(RK3568_VP2_DUAL_CHANNEL_CTRL, 0x1, 21),
1525
+	.bcsh_brightness = VOP_REG(RK3568_VP2_BCSH_BCS, 0xff, 0),
1526
+	.bcsh_contrast = VOP_REG(RK3568_VP2_BCSH_BCS, 0x1ff, 8),
1527
+	.bcsh_sat_con = VOP_REG(RK3568_VP2_BCSH_BCS, 0x3ff, 20),
1528
+	.bcsh_out_mode = VOP_REG(RK3568_VP2_BCSH_BCS, 0x3, 30),
1529
+	.bcsh_sin_hue = VOP_REG(RK3568_VP2_BCSH_H, 0x1ff, 0),
1530
+	.bcsh_cos_hue = VOP_REG(RK3568_VP2_BCSH_H, 0x1ff, 16),
1531
+	.bcsh_r2y_csc_mode = VOP_REG(RK3568_VP2_BCSH_CTRL, 0x3, 6),
1532
+	.bcsh_r2y_en = VOP_REG(RK3568_VP2_BCSH_CTRL, 0x1, 4),
1533
+	.bcsh_y2r_csc_mode = VOP_REG(RK3568_VP2_BCSH_CTRL, 0x3, 2),
1534
+	.bcsh_y2r_en = VOP_REG(RK3568_VP2_BCSH_CTRL, 0x1, 0),
1535
+	.bcsh_en = VOP_REG(RK3568_VP2_BCSH_COLOR_BAR, 0x1, 31),
1536
+	.edpi_te_en = VOP_REG(RK3568_VP2_DUAL_CHANNEL_CTRL, 0x1, 28),
1537
+	.edpi_wms_hold_en = VOP_REG(RK3568_VP2_DUAL_CHANNEL_CTRL, 0x1, 30),
1538
+	.edpi_wms_fs = VOP_REG(RK3568_VP2_DUAL_CHANNEL_CTRL, 0x1, 31),
1539
+
1540
+	.lut_dma_rid = VOP_REG(RK3568_SYS_AXI_LUT_CTRL, 0xf, 4),
1541
+	.cubic_lut_en = VOP_REG(RK3588_VP2_3D_LUT_CTRL, 0x1, 0),
1542
+	.cubic_lut_update_en = VOP_REG(RK3588_VP2_3D_LUT_CTRL, 0x1, 2),
1543
+	.cubic_lut_mst = VOP_REG(RK3588_VP2_3D_LUT_MST, 0xffffffff, 0),
1544
+
1545
+	.line_flag_or_en = VOP_REG(RK3588_SYS_VAR_FREQ_CTRL, 0x1, 22),
1546
+	.dsp_hold_or_en = VOP_REG(RK3588_SYS_VAR_FREQ_CTRL, 0x1, 26),
1547
+	.almost_full_or_en = VOP_REG(RK3588_SYS_VAR_FREQ_CTRL, 0x1, 30),
1548
+
1549
+	.color_bar_mode = VOP_REG(RK3568_VP2_COLOR_BAR_CTRL, 0x1, 1),
1550
+	.color_bar_en = VOP_REG(RK3568_VP2_COLOR_BAR_CTRL, 0x1, 0),
1551
+};
1552
+
1553
+static const struct vop2_video_port_regs rk3588_vop_vp3_regs = {
1554
+	.cfg_done = VOP_REG(RK3568_REG_CFG_DONE, 0x1, 3),
1555
+	.overlay_mode = VOP_REG(RK3568_OVL_CTRL, 0x1, 3),
1556
+	.port_mux = VOP_REG(RK3568_OVL_PORT_SEL, 0xf, 12),
1557
+	.dsp_background = VOP_REG(RK3588_VP3_DSP_BG, 0xffffffff, 0),
1558
+	.out_mode = VOP_REG(RK3588_VP3_DSP_CTRL, 0xf, 0),
1559
+	.p2i_en = VOP_REG(RK3588_VP3_DSP_CTRL, 0x1, 5),
1560
+	.dsp_filed_pol = VOP_REG(RK3588_VP3_DSP_CTRL, 0x1, 6),
1561
+	.dsp_interlace = VOP_REG(RK3588_VP3_DSP_CTRL, 0x1, 7),
1562
+	.dsp_data_swap = VOP_REG(RK3588_VP3_DSP_CTRL, 0x1f, 8),
1563
+	.dsp_x_mir_en = VOP_REG(RK3588_VP3_DSP_CTRL, 0x1, 13),
1564
+	.post_dsp_out_r2y = VOP_REG(RK3588_VP3_DSP_CTRL, 0x1, 15),
1565
+	.pre_dither_down_en = VOP_REG(RK3588_VP3_DSP_CTRL, 0x1, 16),
1566
+	.dither_down_en = VOP_REG(RK3588_VP3_DSP_CTRL, 0x1, 17),
1567
+	.dither_down_sel = VOP_REG(RK3588_VP3_DSP_CTRL, 0x3, 18),
1568
+	.dither_down_mode = VOP_REG(RK3588_VP3_DSP_CTRL, 0x1, 20),
1569
+	.gamma_update_en = VOP_REG(RK3588_VP3_DSP_CTRL, 0x1, 22),
1570
+	.dsp_lut_en = VOP_REG(RK3588_VP3_DSP_CTRL, 0x1, 28),
1571
+	.standby = VOP_REG(RK3588_VP3_DSP_CTRL, 0x1, 31),
1572
+	.dclk_src_sel = VOP_REG(RK3568_LUT_PORT_SEL, 0x1, 30),
1573
+	.dclk_core_div = VOP_REG(RK3568_VP3_CLK_CTRL, 0x3, 0),
1574
+	.dclk_out_div = VOP_REG(RK3568_VP3_CLK_CTRL, 0x3, 2),
1575
+	.pre_scan_htiming = VOP_REG(RK3588_VP3_PRE_SCAN_HTIMING, 0x1fff1fff, 0),
1576
+	.bg_dly = VOP_REG(RK3588_VP3_BG_MIX_CTRL, 0xff, 24),
1577
+	.hpost_st_end = VOP_REG(RK3588_VP3_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
1578
+	.vpost_st_end = VOP_REG(RK3588_VP3_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
1579
+	.post_scl_factor = VOP_REG(RK3588_VP3_POST_SCL_FACTOR_YRGB, 0xffffffff, 0),
1580
+	.post_scl_ctrl = VOP_REG(RK3588_VP3_POST_SCL_CTRL, 0x3, 0),
1581
+	.htotal_pw = VOP_REG(RK3588_VP3_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
1582
+	.hact_st_end = VOP_REG(RK3588_VP3_DSP_HACT_ST_END, 0x1fff1fff, 0),
1583
+	.dsp_vtotal = VOP_REG(RK3588_VP3_DSP_VTOTAL_VS_END, 0x1fff, 16),
1584
+	.sw_dsp_vtotal_imd = VOP_REG(RK3588_VP3_DSP_VTOTAL_VS_END, 0x1, 15),
1585
+	.dsp_vs_end = VOP_REG(RK3588_VP3_DSP_VTOTAL_VS_END, 0x1fff, 0),
1586
+	.vact_st_end = VOP_REG(RK3588_VP3_DSP_VACT_ST_END, 0x1fff1fff, 0),
1587
+	.vact_st_end_f1 = VOP_REG(RK3588_VP3_DSP_VACT_ST_END_F1, 0x1fff1fff, 0),
1588
+	.vs_st_end_f1 = VOP_REG(RK3588_VP3_DSP_VS_ST_END_F1, 0x1fff1fff, 0),
1589
+	.vpost_st_end_f1 = VOP_REG(RK3588_VP3_POST_DSP_VACT_INFO_F1, 0x1fff1fff, 0),
1590
+	.dual_channel_en = VOP_REG(RK3588_VP3_DUAL_CHANNEL_CTRL, 0x1, 20),
1591
+	.dual_channel_swap = VOP_REG(RK3588_VP3_DUAL_CHANNEL_CTRL, 0x1, 21),
1592
+	.bcsh_brightness = VOP_REG(RK3588_VP3_BCSH_BCS, 0xff, 0),
1593
+	.bcsh_contrast = VOP_REG(RK3588_VP3_BCSH_BCS, 0x1ff, 8),
1594
+	.bcsh_sat_con = VOP_REG(RK3588_VP3_BCSH_BCS, 0x3ff, 20),
1595
+	.bcsh_out_mode = VOP_REG(RK3588_VP3_BCSH_BCS, 0x3, 30),
1596
+	.bcsh_sin_hue = VOP_REG(RK3588_VP3_BCSH_H, 0x1ff, 0),
1597
+	.bcsh_cos_hue = VOP_REG(RK3588_VP3_BCSH_H, 0x1ff, 16),
1598
+	.bcsh_r2y_csc_mode = VOP_REG(RK3588_VP3_BCSH_CTRL, 0x3, 6),
1599
+	.bcsh_r2y_en = VOP_REG(RK3588_VP3_BCSH_CTRL, 0x1, 4),
1600
+	.bcsh_y2r_csc_mode = VOP_REG(RK3588_VP3_BCSH_CTRL, 0x3, 2),
1601
+	.bcsh_y2r_en = VOP_REG(RK3588_VP3_BCSH_CTRL, 0x1, 0),
1602
+	.bcsh_en = VOP_REG(RK3588_VP3_BCSH_COLOR_BAR, 0x1, 31),
1603
+	.edpi_te_en = VOP_REG(RK3588_VP3_DUAL_CHANNEL_CTRL, 0x1, 28),
1604
+	.edpi_wms_hold_en = VOP_REG(RK3588_VP3_DUAL_CHANNEL_CTRL, 0x1, 30),
1605
+	.edpi_wms_fs = VOP_REG(RK3588_VP3_DUAL_CHANNEL_CTRL, 0x1, 31),
1606
+
1607
+	.line_flag_or_en = VOP_REG(RK3588_SYS_VAR_FREQ_CTRL, 0x1, 23),
1608
+	.dsp_hold_or_en = VOP_REG(RK3588_SYS_VAR_FREQ_CTRL, 0x1, 27),
1609
+	.almost_full_or_en = VOP_REG(RK3588_SYS_VAR_FREQ_CTRL, 0x1, 31),
1610
+
1611
+	.color_bar_mode = VOP_REG(RK3588_VP3_COLOR_BAR_CTRL, 0x1, 1),
1612
+	.color_bar_en = VOP_REG(RK3588_VP3_COLOR_BAR_CTRL, 0x1, 0),
1613
+};
1614
+
1615
+static const struct vop2_video_port_data rk3588_vop_video_ports[] = {
1616
+	{
1617
+	 .id = 0,
1618
+	 .splice_vp_id = 1,
1619
+	 .lut_dma_rid = 0xd,
1620
+	 .soc_id = { 0x3588, 0x3588 },
1621
+	 .feature = VOP_FEATURE_OUTPUT_10BIT | VOP_FEATURE_ALPHA_SCALE |
1622
+			VOP_FEATURE_HDR10 | VOP_FEATURE_NEXT_HDR,
1623
+	 .gamma_lut_len = 1024,
1624
+	 .cubic_lut_len = 729, /* 9x9x9 */
1625
+	 .dclk_max = 600000000,
1626
+	 .max_output = { 7680, 4320 },
1627
+	 /* hdr2sdr sdr2hdr hdr2hdr sdr2sdr */
1628
+	 .pre_scan_max_dly = { 76, 65, 65, 54 },
1629
+	 .intr = &rk3568_vp0_intr,
1630
+	 .hdr_table = &rk3568_vop_hdr_table,
1631
+	 .regs = &rk3588_vop_vp0_regs,
1632
+	},
1633
+	{
1634
+	 .id = 1,
1635
+	 .lut_dma_rid = 0xe,
1636
+	 .soc_id = { 0x3588, 0x3588 },
1637
+	 .feature = VOP_FEATURE_OUTPUT_10BIT | VOP_FEATURE_ALPHA_SCALE,
1638
+	 .gamma_lut_len = 1024,
1639
+	 .cubic_lut_len = 729, /* 9x9x9 */
1640
+	 .dclk_max = 600000000,
1641
+	 .max_output = { 4096, 2304 },
1642
+	 .pre_scan_max_dly = { 76, 65, 65, 54 },
1643
+	 .intr = &rk3568_vp1_intr,
1644
+	 /* vp1 share the same hdr curve with vp0 */
1645
+	 .hdr_table = &rk3568_vop_hdr_table,
1646
+	 .regs = &rk3588_vop_vp1_regs,
1647
+	},
1648
+	{
1649
+	 .id = 2,
1650
+	 .lut_dma_rid = 0xe,
1651
+	 .soc_id = { 0x3588, 0x3588 },
1652
+	 .feature = VOP_FEATURE_OUTPUT_10BIT | VOP_FEATURE_ALPHA_SCALE,
1653
+	 .gamma_lut_len = 1024,
1654
+	 .cubic_lut_len = 4913, /* 17x17x17 */
1655
+	 .dclk_max = 600000000,
1656
+	 .max_output = { 4096, 2304 },
1657
+	 .pre_scan_max_dly = { 52, 52, 52, 52 },
1658
+	 .intr = &rk3568_vp2_intr,
1659
+	 .regs = &rk3588_vop_vp2_regs,
1660
+	},
1661
+	{
1662
+	 .id = 3,
1663
+	 .soc_id = { 0x3588, 0x3588 },
1664
+	 .feature = VOP_FEATURE_ALPHA_SCALE,
1665
+	 .gamma_lut_len = 1024,
1666
+	 .dclk_max = 200000000,
1667
+	 .max_output = { 2048, 1536 },
1668
+	 .pre_scan_max_dly = { 52, 52, 52, 52 },
1669
+	 .intr = &rk3588_vp3_intr,
1670
+	 .regs = &rk3588_vop_vp3_regs,
1671
+	},
1672
+};
1673
+
1674
+/*
1675
+ * HDMI/eDP infterface pixclk and dclk are independent of each other.
1676
+ * MIPI and DP interface pixclk and dclk are the same in itself.
1677
+ */
1678
+static const struct vop2_connector_if_data rk3588_conn_if_data[] = {
1679
+	{
1680
+	 .id = VOP_OUTPUT_IF_HDMI0,
1681
+	 .clk_src_name = "hdmi_edp0_clk_src",
1682
+	 .clk_parent_name = "dclk",
1683
+	 .pixclk_name = "hdmi_edp0_pixclk",
1684
+	 .dclk_name = "hdmi_edp0_dclk",
1685
+	 .post_proc_div_shift = 2,
1686
+	 .if_div_shift = 4,
1687
+	 .if_div_yuv420_shift = 1,
1688
+	 .bus_div_shift = 2,
1689
+	 .pixel_clk_div_shift = 2,
1690
+	},
1691
+
1692
+	{
1693
+	 .id = VOP_OUTPUT_IF_HDMI1,
1694
+	 .clk_src_name = "hdmi_edp1_clk_src",
1695
+	 .clk_parent_name = "dclk",
1696
+	 .pixclk_name = "hdmi_edp1_pixclk",
1697
+	 .dclk_name = "hdmi_edp1_dclk",
1698
+	 .post_proc_div_shift = 2,
1699
+	 .if_div_shift = 4,
1700
+	 .if_div_yuv420_shift = 1,
1701
+	 .bus_div_shift = 2,
1702
+	 .pixel_clk_div_shift = 2,
1703
+	},
1704
+
1705
+	{
1706
+	 .id = VOP_OUTPUT_IF_eDP0,
1707
+	 .clk_src_name = "hdmi_edp0_clk_src",
1708
+	 .clk_parent_name = "dclk",
1709
+	 .pixclk_name = "hdmi_edp0_pixclk",
1710
+	 .dclk_name = "hdmi_edp0_dclk",
1711
+	 .post_proc_div_shift = 2,
1712
+	 .if_div_shift = 4,
1713
+	 .if_div_yuv420_shift = 1,
1714
+	 .bus_div_shift = 1,
1715
+	 .pixel_clk_div_shift = 1,
1716
+	},
1717
+
1718
+	{
1719
+	 .id = VOP_OUTPUT_IF_eDP1,
1720
+	 .clk_src_name = "hdmi_edp1_clk_src",
1721
+	 .clk_parent_name = "dclk",
1722
+	 .pixclk_name = "hdmi_edp1_pixclk",
1723
+	 .dclk_name = "hdmi_edp1_dclk",
1724
+	 .post_proc_div_shift = 2,
1725
+	 .if_div_shift = 4,
1726
+	 .if_div_yuv420_shift = 1,
1727
+	 .bus_div_shift = 1,
1728
+	 .pixel_clk_div_shift = 1,
1729
+	},
1730
+
1731
+	{
1732
+	 .id = VOP_OUTPUT_IF_DP0,
1733
+	 .clk_src_name = "dp0_pixclk",
1734
+	 .clk_parent_name = "dclk_out",
1735
+	 .pixclk_name = "dp0_pixclk",
1736
+	 .post_proc_div_shift = 2,
1737
+	 .if_div_shift = 1,
1738
+	 .if_div_yuv420_shift = 2,
1739
+	 .bus_div_shift = 1,
1740
+	 .pixel_clk_div_shift = 1,
1741
+
1742
+	},
1743
+
1744
+	{
1745
+	 .id = VOP_OUTPUT_IF_DP1,
1746
+	 .clk_src_name = "dp1_pixclk",
1747
+	 .clk_parent_name = "dclk_out",
1748
+	 .pixclk_name = "dp1_pixclk",
1749
+	 .post_proc_div_shift = 2,
1750
+	 .if_div_shift = 1,
1751
+	 .if_div_yuv420_shift = 2,
1752
+	 .bus_div_shift = 1,
1753
+	 .pixel_clk_div_shift = 1,
1754
+
1755
+	},
1756
+
1757
+	{
1758
+	 .id = VOP_OUTPUT_IF_MIPI0,
1759
+	 .clk_src_name = "mipi0_clk_src",
1760
+	 .clk_parent_name = "dclk_out",
1761
+	 .pixclk_name = "mipi0_pixclk",
1762
+	 .post_proc_div_shift = 2,
1763
+	 .if_div_shift = 1,
1764
+	 .if_div_yuv420_shift = 1,
1765
+	 .bus_div_shift = 1,
1766
+	 .pixel_clk_div_shift = 1,
1767
+	},
1768
+
1769
+	{
1770
+	 .id = VOP_OUTPUT_IF_MIPI1,
1771
+	 .clk_src_name = "mipi1_clk_src",
1772
+	 .clk_parent_name = "dclk_out",
1773
+	 .pixclk_name = "mipi1_pixclk",
1774
+	 .post_proc_div_shift = 2,
1775
+	 .if_div_shift = 1,
1776
+	 .if_div_yuv420_shift = 1,
1777
+	 .bus_div_shift = 1,
1778
+	 .pixel_clk_div_shift = 1,
1779
+	},
1780
+
1781
+	{
1782
+	 .id = VOP_OUTPUT_IF_RGB,
1783
+	 .clk_src_name = "port3_dclk_src",
1784
+	 .clk_parent_name = "dclk",
1785
+	 .pixclk_name = "rgb_pixclk",
1786
+	 .post_proc_div_shift = 2,
1787
+	 .if_div_shift = 0,
1788
+	 .if_div_yuv420_shift = 0,
1789
+	 .bus_div_shift = 0,
1790
+	 .pixel_clk_div_shift = 0,
1791
+	},
1792
+};
1793
+
9231794 
9241795 const struct vop2_layer_regs rk3568_vop_layer0_regs = {
9251796 	.layer_sel = VOP_REG(RK3568_OVL_LAYER_SEL, 0x7, 0)
....@@ -943,6 +1814,14 @@
9431814 
9441815 const struct vop2_layer_regs rk3568_vop_layer5_regs = {
9451816 	.layer_sel = VOP_REG(RK3568_OVL_LAYER_SEL, 0x7, 20)
1817
+};
1818
+
1819
+const struct vop2_layer_regs rk3568_vop_layer6_regs = {
1820
+	.layer_sel = VOP_REG(RK3568_OVL_LAYER_SEL, 0x7, 24)
1821
+};
1822
+
1823
+const struct vop2_layer_regs rk3568_vop_layer7_regs = {
1824
+	.layer_sel = VOP_REG(RK3568_OVL_LAYER_SEL, 0x7, 28)
9461825 };
9471826 
9481827 static const struct vop2_layer_data rk3568_vop_layers[] = {
....@@ -975,24 +1854,36 @@
9751854 	 .id = 5,
9761855 	 .regs = &rk3568_vop_layer5_regs,
9771856 	},
1857
+
1858
+	{
1859
+	 .id = 6,
1860
+	 .regs = &rk3568_vop_layer6_regs,
1861
+	},
1862
+
1863
+	{
1864
+	 .id = 7,
1865
+	 .regs = &rk3568_vop_layer7_regs,
1866
+	},
1867
+
9781868 };
9791869 
9801870 static const struct vop2_cluster_regs rk3528_vop_cluster0 = {
981
-	 .afbc_enable = VOP_REG(RK3568_CLUSTER0_CTRL, 0x1, 1),
982
-	 .enable = VOP_REG(RK3568_CLUSTER0_CTRL, 1, 0),
983
-	 .lb_mode = VOP_REG(RK3568_CLUSTER0_CTRL, 0xf, 4),
984
-	 .scl_lb_mode = VOP_REG(RK3568_CLUSTER0_CTRL, 0x3, 9),
985
-	 .frm_reset_en = VOP_REG(RK3568_CLUSTER0_CTRL, 1, 31),
986
-	 .src_color_ctrl = VOP_REG(RK3528_CLUSTER0_MIX_SRC_COLOR_CTRL, 0xffffffff, 0),
987
-	 .dst_color_ctrl = VOP_REG(RK3528_CLUSTER0_MIX_DST_COLOR_CTRL, 0xffffffff, 0),
988
-	 .src_alpha_ctrl = VOP_REG(RK3528_CLUSTER0_MIX_SRC_ALPHA_CTRL, 0xffffffff, 0),
989
-	 .dst_alpha_ctrl = VOP_REG(RK3528_CLUSTER0_MIX_DST_ALPHA_CTRL, 0xffffffff, 0),
1871
+	.afbc_enable = VOP_REG(RK3568_CLUSTER0_CTRL, 0x1, 1),
1872
+	.enable = VOP_REG(RK3568_CLUSTER0_CTRL, 1, 0),
1873
+	.lb_mode = VOP_REG(RK3568_CLUSTER0_CTRL, 0xf, 4),
1874
+	.scl_lb_mode = VOP_REG(RK3568_CLUSTER0_CTRL, 0x3, 9),
1875
+	.frm_reset_en = VOP_REG(RK3568_CLUSTER0_CTRL, 1, 31),
1876
+	.src_color_ctrl = VOP_REG(RK3528_CLUSTER0_MIX_SRC_COLOR_CTRL, 0xffffffff, 0),
1877
+	.dst_color_ctrl = VOP_REG(RK3528_CLUSTER0_MIX_DST_COLOR_CTRL, 0xffffffff, 0),
1878
+	.src_alpha_ctrl = VOP_REG(RK3528_CLUSTER0_MIX_SRC_ALPHA_CTRL, 0xffffffff, 0),
1879
+	.dst_alpha_ctrl = VOP_REG(RK3528_CLUSTER0_MIX_DST_ALPHA_CTRL, 0xffffffff, 0),
9901880 };
9911881 
9921882 static const struct vop2_cluster_regs rk3568_vop_cluster0 = {
9931883 	.afbc_enable = VOP_REG(RK3568_CLUSTER0_CTRL, 0x1, 1),
9941884 	.enable = VOP_REG(RK3568_CLUSTER0_CTRL, 1, 0),
9951885 	.lb_mode = VOP_REG(RK3568_CLUSTER0_CTRL, 0xf, 4),
1886
+	.frm_reset_en = VOP_REG(RK3568_CLUSTER0_CTRL, 1, 31),
9961887 	.src_color_ctrl = VOP_REG(RK3568_CLUSTER0_MIX_SRC_COLOR_CTRL, 0xffffffff, 0),
9971888 	.dst_color_ctrl = VOP_REG(RK3568_CLUSTER0_MIX_DST_COLOR_CTRL, 0xffffffff, 0),
9981889 	.src_alpha_ctrl = VOP_REG(RK3568_CLUSTER0_MIX_SRC_ALPHA_CTRL, 0xffffffff, 0),
....@@ -1003,10 +1894,33 @@
10031894 	.afbc_enable = VOP_REG(RK3568_CLUSTER1_CTRL, 0x1, 1),
10041895 	.enable = VOP_REG(RK3568_CLUSTER1_CTRL, 1, 0),
10051896 	.lb_mode = VOP_REG(RK3568_CLUSTER1_CTRL, 0xf, 4),
1897
+	.frm_reset_en = VOP_REG(RK3568_CLUSTER1_CTRL, 1, 31),
10061898 	.src_color_ctrl = VOP_REG(RK3568_CLUSTER1_MIX_SRC_COLOR_CTRL, 0xffffffff, 0),
10071899 	.dst_color_ctrl = VOP_REG(RK3568_CLUSTER1_MIX_DST_COLOR_CTRL, 0xffffffff, 0),
10081900 	.src_alpha_ctrl = VOP_REG(RK3568_CLUSTER1_MIX_SRC_ALPHA_CTRL, 0xffffffff, 0),
10091901 	.dst_alpha_ctrl = VOP_REG(RK3568_CLUSTER1_MIX_DST_ALPHA_CTRL, 0xffffffff, 0),
1902
+};
1903
+
1904
+static const struct vop2_cluster_regs rk3588_vop_cluster2 = {
1905
+	.afbc_enable = VOP_REG(RK3588_CLUSTER2_CTRL, 0x1, 1),
1906
+	.enable = VOP_REG(RK3588_CLUSTER2_CTRL, 1, 0),
1907
+	.lb_mode = VOP_REG(RK3588_CLUSTER2_CTRL, 0xf, 4),
1908
+	.frm_reset_en = VOP_REG(RK3588_CLUSTER2_CTRL, 1, 31),
1909
+	.src_color_ctrl = VOP_REG(RK3588_CLUSTER2_MIX_SRC_COLOR_CTRL, 0xffffffff, 0),
1910
+	.dst_color_ctrl = VOP_REG(RK3588_CLUSTER2_MIX_DST_COLOR_CTRL, 0xffffffff, 0),
1911
+	.src_alpha_ctrl = VOP_REG(RK3588_CLUSTER2_MIX_SRC_ALPHA_CTRL, 0xffffffff, 0),
1912
+	.dst_alpha_ctrl = VOP_REG(RK3588_CLUSTER2_MIX_DST_ALPHA_CTRL, 0xffffffff, 0),
1913
+};
1914
+
1915
+static const struct vop2_cluster_regs rk3588_vop_cluster3 =  {
1916
+	.afbc_enable = VOP_REG(RK3588_CLUSTER3_CTRL, 0x1, 1),
1917
+	.enable = VOP_REG(RK3588_CLUSTER3_CTRL, 1, 0),
1918
+	.lb_mode = VOP_REG(RK3588_CLUSTER3_CTRL, 0xf, 4),
1919
+	.frm_reset_en = VOP_REG(RK3588_CLUSTER3_CTRL, 1, 31),
1920
+	.src_color_ctrl = VOP_REG(RK3588_CLUSTER3_MIX_SRC_COLOR_CTRL, 0xffffffff, 0),
1921
+	.dst_color_ctrl = VOP_REG(RK3588_CLUSTER3_MIX_DST_COLOR_CTRL, 0xffffffff, 0),
1922
+	.src_alpha_ctrl = VOP_REG(RK3588_CLUSTER3_MIX_SRC_ALPHA_CTRL, 0xffffffff, 0),
1923
+	.dst_alpha_ctrl = VOP_REG(RK3588_CLUSTER3_MIX_DST_ALPHA_CTRL, 0xffffffff, 0),
10101924 };
10111925 
10121926 static const struct vop_afbc rk3568_cluster0_afbc = {
....@@ -1055,6 +1969,7 @@
10551969 	.scale_yrgb_y = VOP_REG(RK3568_CLUSTER0_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
10561970 	.yrgb_ver_scl_mode = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL1, 0x3, 14),
10571971 	.yrgb_hor_scl_mode = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL1, 0x3, 12),
1972
+	.bic_coe_sel = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL1, 0x3, 2),
10581973 	.vsd_yrgb_gt2 = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL1, 0x1, 28),
10591974 	.vsd_yrgb_gt4 = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL1, 0x1, 29),
10601975 };
....@@ -1089,6 +2004,65 @@
10892004 	.vsd_yrgb_gt4 = VOP_REG(RK3568_CLUSTER1_WIN0_CTRL1, 0x1, 29),
10902005 };
10912006 
2007
+static const struct vop_afbc rk3588_cluster2_afbc = {
2008
+	.format = VOP_REG(RK3588_CLUSTER2_WIN0_AFBCD_CTRL, 0x1f, 2),
2009
+	.rb_swap = VOP_REG(RK3588_CLUSTER2_WIN0_AFBCD_CTRL, 0x1, 9),
2010
+	.uv_swap = VOP_REG(RK3588_CLUSTER2_WIN0_AFBCD_CTRL, 0x1, 10),
2011
+	.auto_gating_en = VOP_REG(RK3588_CLUSTER2_WIN0_AFBCD_OUTPUT_CTRL, 0x1, 4),
2012
+	.half_block_en = VOP_REG(RK3588_CLUSTER2_WIN0_AFBCD_CTRL, 0x1, 7),
2013
+	.block_split_en = VOP_REG(RK3588_CLUSTER2_WIN0_AFBCD_CTRL, 0x1, 8),
2014
+	.hdr_ptr = VOP_REG(RK3588_CLUSTER2_WIN0_AFBCD_HDR_PTR, 0xffffffff, 0),
2015
+	.pic_size = VOP_REG(RK3588_CLUSTER2_WIN0_AFBCD_PIC_SIZE, 0xffffffff, 0),
2016
+	.pic_vir_width = VOP_REG(RK3588_CLUSTER2_WIN0_AFBCD_VIR_WIDTH, 0xffff, 0),
2017
+	.tile_num = VOP_REG(RK3588_CLUSTER2_WIN0_AFBCD_VIR_WIDTH, 0xffff, 16),
2018
+	.pic_offset = VOP_REG(RK3588_CLUSTER2_WIN0_AFBCD_PIC_OFFSET, 0xffffffff, 0),
2019
+	.dsp_offset = VOP_REG(RK3588_CLUSTER2_WIN0_AFBCD_DSP_OFFSET, 0xffffffff, 0),
2020
+	.transform_offset = VOP_REG(RK3588_CLUSTER2_WIN0_AFBCD_TRANSFORM_OFFSET, 0xffffffff, 0),
2021
+	.rotate_90 = VOP_REG(RK3588_CLUSTER2_WIN0_AFBCD_ROTATE_MODE, 0x1, 0),
2022
+	.rotate_270 = VOP_REG(RK3588_CLUSTER2_WIN0_AFBCD_ROTATE_MODE, 0x1, 1),
2023
+	.xmirror = VOP_REG(RK3588_CLUSTER2_WIN0_AFBCD_ROTATE_MODE, 0x1, 2),
2024
+	.ymirror = VOP_REG(RK3588_CLUSTER2_WIN0_AFBCD_ROTATE_MODE, 0x1, 3),
2025
+};
2026
+
2027
+static const struct vop2_scl_regs rk3588_cluster2_win_scl = {
2028
+	.scale_yrgb_x = VOP_REG(RK3588_CLUSTER2_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
2029
+	.scale_yrgb_y = VOP_REG(RK3588_CLUSTER2_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
2030
+	.yrgb_ver_scl_mode = VOP_REG(RK3588_CLUSTER2_WIN0_CTRL1, 0x3, 14),
2031
+	.yrgb_hor_scl_mode = VOP_REG(RK3588_CLUSTER2_WIN0_CTRL1, 0x3, 12),
2032
+	.bic_coe_sel = VOP_REG(RK3588_CLUSTER2_WIN0_CTRL1, 0x3, 2),
2033
+	.vsd_yrgb_gt2 = VOP_REG(RK3588_CLUSTER2_WIN0_CTRL1, 0x1, 28),
2034
+	.vsd_yrgb_gt4 = VOP_REG(RK3588_CLUSTER2_WIN0_CTRL1, 0x1, 29),
2035
+};
2036
+
2037
+static const struct vop_afbc rk3588_cluster3_afbc = {
2038
+	.format = VOP_REG(RK3588_CLUSTER3_WIN0_AFBCD_CTRL, 0x1f, 2),
2039
+	.rb_swap = VOP_REG(RK3588_CLUSTER3_WIN0_AFBCD_CTRL, 0x1, 9),
2040
+	.uv_swap = VOP_REG(RK3588_CLUSTER3_WIN0_AFBCD_CTRL, 0x1, 10),
2041
+	.auto_gating_en = VOP_REG(RK3588_CLUSTER3_WIN0_AFBCD_OUTPUT_CTRL, 0x1, 4),
2042
+	.half_block_en = VOP_REG(RK3588_CLUSTER3_WIN0_AFBCD_CTRL, 0x1, 7),
2043
+	.block_split_en = VOP_REG(RK3588_CLUSTER3_WIN0_AFBCD_CTRL, 0x1, 8),
2044
+	.hdr_ptr = VOP_REG(RK3588_CLUSTER3_WIN0_AFBCD_HDR_PTR, 0xffffffff, 0),
2045
+	.pic_size = VOP_REG(RK3588_CLUSTER3_WIN0_AFBCD_PIC_SIZE, 0xffffffff, 0),
2046
+	.pic_vir_width = VOP_REG(RK3588_CLUSTER3_WIN0_AFBCD_VIR_WIDTH, 0xffff, 0),
2047
+	.tile_num = VOP_REG(RK3588_CLUSTER3_WIN0_AFBCD_VIR_WIDTH, 0xffff, 16),
2048
+	.pic_offset = VOP_REG(RK3588_CLUSTER3_WIN0_AFBCD_PIC_OFFSET, 0xffffffff, 0),
2049
+	.dsp_offset = VOP_REG(RK3588_CLUSTER3_WIN0_AFBCD_DSP_OFFSET, 0xffffffff, 0),
2050
+	.transform_offset = VOP_REG(RK3588_CLUSTER3_WIN0_AFBCD_TRANSFORM_OFFSET, 0xffffffff, 0),
2051
+	.rotate_90 = VOP_REG(RK3588_CLUSTER3_WIN0_AFBCD_ROTATE_MODE, 0x1, 0),
2052
+	.rotate_270 = VOP_REG(RK3588_CLUSTER3_WIN0_AFBCD_ROTATE_MODE, 0x1, 1),
2053
+	.xmirror = VOP_REG(RK3588_CLUSTER3_WIN0_AFBCD_ROTATE_MODE, 0x1, 2),
2054
+	.ymirror = VOP_REG(RK3588_CLUSTER3_WIN0_AFBCD_ROTATE_MODE, 0x1, 3),
2055
+};
2056
+
2057
+static const struct vop2_scl_regs rk3588_cluster3_win_scl = {
2058
+	.scale_yrgb_x = VOP_REG(RK3588_CLUSTER3_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
2059
+	.scale_yrgb_y = VOP_REG(RK3588_CLUSTER3_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
2060
+	.yrgb_ver_scl_mode = VOP_REG(RK3588_CLUSTER3_WIN0_CTRL1, 0x3, 14),
2061
+	.yrgb_hor_scl_mode = VOP_REG(RK3588_CLUSTER3_WIN0_CTRL1, 0x3, 12),
2062
+	.bic_coe_sel = VOP_REG(RK3588_CLUSTER3_WIN0_CTRL1, 0x3, 2),
2063
+	.vsd_yrgb_gt2 = VOP_REG(RK3588_CLUSTER3_WIN0_CTRL1, 0x1, 28),
2064
+	.vsd_yrgb_gt4 = VOP_REG(RK3588_CLUSTER3_WIN0_CTRL1, 0x1, 29),
2065
+};
10922066 
10932067 static const struct vop2_scl_regs rk3568_esmart_win_scl = {
10942068 	.scale_yrgb_x = VOP_REG(RK3568_ESMART0_REGION0_SCL_FACTOR_YRGB, 0xffff, 0x0),
....@@ -1193,7 +2167,6 @@
11932167 	.dsp_st = VOP_REG(RK3568_ESMART0_REGION1_DSP_ST, 0x1fff1fff, 0),
11942168 	.yrgb_mst = VOP_REG(RK3568_ESMART0_REGION1_YRGB_MST, 0xffffffff, 0),
11952169 	.uv_mst = VOP_REG(RK3568_ESMART0_REGION1_CBR_MST, 0xffffffff, 0),
1196
-	.yuv_clip = VOP_REG(RK3568_ESMART0_REGION1_CTRL, 0x1, 17),
11972170 	.yrgb_vir = VOP_REG(RK3568_ESMART0_REGION1_VIR, 0xffff, 0),
11982171 	.uv_vir = VOP_REG(RK3568_ESMART0_REGION1_VIR, 0xffff, 16),
11992172 };
....@@ -1209,7 +2182,6 @@
12092182 	.dsp_st = VOP_REG(RK3568_ESMART0_REGION2_DSP_ST, 0x1fff1fff, 0),
12102183 	.yrgb_mst = VOP_REG(RK3568_ESMART0_REGION2_YRGB_MST, 0xffffffff, 0),
12112184 	.uv_mst = VOP_REG(RK3568_ESMART0_REGION2_CBR_MST, 0xffffffff, 0),
1212
-	.yuv_clip = VOP_REG(RK3568_ESMART0_REGION2_CTRL, 0x1, 17),
12132185 	.yrgb_vir = VOP_REG(RK3568_ESMART0_REGION2_VIR, 0xffff, 0),
12142186 	.uv_vir = VOP_REG(RK3568_ESMART0_REGION2_VIR, 0xffff, 16),
12152187 };
....@@ -1225,7 +2197,6 @@
12252197 	.dsp_st = VOP_REG(RK3568_ESMART0_REGION3_DSP_ST, 0x1fff1fff, 0),
12262198 	.yrgb_mst = VOP_REG(RK3568_ESMART0_REGION3_YRGB_MST, 0xffffffff, 0),
12272199 	.uv_mst = VOP_REG(RK3568_ESMART0_REGION3_CBR_MST, 0xffffffff, 0),
1228
-	.yuv_clip = VOP_REG(RK3568_ESMART0_REGION3_CTRL, 0x1, 17),
12292200 	.yrgb_vir = VOP_REG(RK3568_ESMART0_REGION3_VIR, 0xffff, 0),
12302201 	.uv_vir = VOP_REG(RK3568_ESMART0_REGION3_VIR, 0xffff, 16),
12312202 };
....@@ -1270,16 +2241,18 @@
12702241 	.rb_swap = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL0, 0x1, 14),
12712242 	.dither_up = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL0, 0x1, 18),
12722243 	.act_info = VOP_REG(RK3568_CLUSTER0_WIN0_ACT_INFO, 0x1fff1fff, 0),
1273
-	.dsp_info = VOP_REG(RK3568_CLUSTER0_WIN0_DSP_INFO, 0x0fff0fff, 0),
2244
+	.dsp_info = VOP_REG(RK3568_CLUSTER0_WIN0_DSP_INFO, 0x1fff1fff, 0),
12742245 	.dsp_st = VOP_REG(RK3568_CLUSTER0_WIN0_DSP_ST, 0x1fff1fff, 0),
12752246 	.yrgb_mst = VOP_REG(RK3568_CLUSTER0_WIN0_YRGB_MST, 0xffffffff, 0),
12762247 	.uv_mst = VOP_REG(RK3568_CLUSTER0_WIN0_CBR_MST, 0xffffffff, 0),
1277
-	.yuv_clip = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL0, 0x1, 19),
12782248 	.yrgb_vir = VOP_REG(RK3568_CLUSTER0_WIN0_VIR, 0xffff, 0),
12792249 	.uv_vir = VOP_REG(RK3568_CLUSTER0_WIN0_VIR, 0xffff, 16),
12802250 	.y2r_en = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL0, 0x1, 8),
12812251 	.r2y_en = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL0, 0x1, 9),
12822252 	.csc_mode = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL0, 0x3, 10),
2253
+	.axi_yrgb_id = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL2, 0x1f, 0),
2254
+	.axi_uv_id = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL2, 0x1f, 5),
2255
+	.axi_id = VOP_REG(RK3568_CLUSTER0_CTRL, 0x1, 13),
12832256 };
12842257 
12852258 static const struct vop2_win_regs rk3568_cluster1_win_data = {
....@@ -1291,16 +2264,62 @@
12912264 	.rb_swap = VOP_REG(RK3568_CLUSTER1_WIN0_CTRL0, 0x1, 14),
12922265 	.dither_up = VOP_REG(RK3568_CLUSTER1_WIN0_CTRL0, 0x1, 18),
12932266 	.act_info = VOP_REG(RK3568_CLUSTER1_WIN0_ACT_INFO, 0x1fff1fff, 0),
1294
-	.dsp_info = VOP_REG(RK3568_CLUSTER1_WIN0_DSP_INFO, 0x0fff0fff, 0),
2267
+	.dsp_info = VOP_REG(RK3568_CLUSTER1_WIN0_DSP_INFO, 0x1fff1fff, 0),
12952268 	.dsp_st = VOP_REG(RK3568_CLUSTER1_WIN0_DSP_ST, 0x1fff1fff, 0),
12962269 	.yrgb_mst = VOP_REG(RK3568_CLUSTER1_WIN0_YRGB_MST, 0xffffffff, 0),
12972270 	.uv_mst = VOP_REG(RK3568_CLUSTER1_WIN0_CBR_MST, 0xffffffff, 0),
1298
-	.yuv_clip = VOP_REG(RK3568_CLUSTER1_WIN0_CTRL0, 0x1, 19),
12992271 	.yrgb_vir = VOP_REG(RK3568_CLUSTER1_WIN0_VIR, 0xffff, 0),
13002272 	.uv_vir = VOP_REG(RK3568_CLUSTER1_WIN0_VIR, 0xffff, 16),
13012273 	.y2r_en = VOP_REG(RK3568_CLUSTER1_WIN0_CTRL0, 0x1, 8),
13022274 	.r2y_en = VOP_REG(RK3568_CLUSTER1_WIN0_CTRL0, 0x1, 9),
13032275 	.csc_mode = VOP_REG(RK3568_CLUSTER1_WIN0_CTRL0, 0x3, 10),
2276
+	.axi_yrgb_id = VOP_REG(RK3568_CLUSTER1_WIN0_CTRL2, 0x1f, 0),
2277
+	.axi_uv_id = VOP_REG(RK3568_CLUSTER1_WIN0_CTRL2, 0x1f, 5),
2278
+	.axi_id = VOP_REG(RK3568_CLUSTER1_CTRL, 0x1, 13),
2279
+};
2280
+
2281
+static const struct vop2_win_regs rk3588_cluster2_win_data = {
2282
+	.scl = &rk3588_cluster2_win_scl,
2283
+	.afbc = &rk3588_cluster2_afbc,
2284
+	.cluster = &rk3588_vop_cluster2,
2285
+	.enable = VOP_REG(RK3588_CLUSTER2_WIN0_CTRL0, 0x1, 0),
2286
+	.format = VOP_REG(RK3588_CLUSTER2_WIN0_CTRL0, 0x1f, 1),
2287
+	.rb_swap = VOP_REG(RK3588_CLUSTER2_WIN0_CTRL0, 0x1, 14),
2288
+	.act_info = VOP_REG(RK3588_CLUSTER2_WIN0_ACT_INFO, 0x1fff1fff, 0),
2289
+	.dsp_info = VOP_REG(RK3588_CLUSTER2_WIN0_DSP_INFO, 0x1fff1fff, 0),
2290
+	.dsp_st = VOP_REG(RK3588_CLUSTER2_WIN0_DSP_ST, 0x1fff1fff, 0),
2291
+	.yrgb_mst = VOP_REG(RK3588_CLUSTER2_WIN0_YRGB_MST, 0xffffffff, 0),
2292
+	.uv_mst = VOP_REG(RK3588_CLUSTER2_WIN0_CBR_MST, 0xffffffff, 0),
2293
+	.yrgb_vir = VOP_REG(RK3588_CLUSTER2_WIN0_VIR, 0xffff, 0),
2294
+	.uv_vir = VOP_REG(RK3588_CLUSTER2_WIN0_VIR, 0xffff, 16),
2295
+	.y2r_en = VOP_REG(RK3588_CLUSTER2_WIN0_CTRL0, 0x1, 8),
2296
+	.r2y_en = VOP_REG(RK3588_CLUSTER2_WIN0_CTRL0, 0x1, 9),
2297
+	.csc_mode = VOP_REG(RK3588_CLUSTER2_WIN0_CTRL0, 0x3, 10),
2298
+	.axi_yrgb_id = VOP_REG(RK3588_CLUSTER2_WIN0_CTRL2, 0x1f, 0),
2299
+	.axi_uv_id = VOP_REG(RK3588_CLUSTER2_WIN0_CTRL2, 0x1f, 5),
2300
+	.axi_id = VOP_REG(RK3588_CLUSTER2_CTRL, 0x1, 13),
2301
+};
2302
+
2303
+static const struct vop2_win_regs rk3588_cluster3_win_data = {
2304
+	.scl = &rk3588_cluster3_win_scl,
2305
+	.afbc = &rk3588_cluster3_afbc,
2306
+	.cluster = &rk3588_vop_cluster3,
2307
+	.enable = VOP_REG(RK3588_CLUSTER3_WIN0_CTRL0, 0x1, 0),
2308
+	.format = VOP_REG(RK3588_CLUSTER3_WIN0_CTRL0, 0x1f, 1),
2309
+	.rb_swap = VOP_REG(RK3588_CLUSTER3_WIN0_CTRL0, 0x1, 14),
2310
+	.act_info = VOP_REG(RK3588_CLUSTER3_WIN0_ACT_INFO, 0x1fff1fff, 0),
2311
+	.dsp_info = VOP_REG(RK3588_CLUSTER3_WIN0_DSP_INFO, 0x1fff1fff, 0),
2312
+	.dsp_st = VOP_REG(RK3588_CLUSTER3_WIN0_DSP_ST, 0x1fff1fff, 0),
2313
+	.yrgb_mst = VOP_REG(RK3588_CLUSTER3_WIN0_YRGB_MST, 0xffffffff, 0),
2314
+	.uv_mst = VOP_REG(RK3588_CLUSTER3_WIN0_CBR_MST, 0xffffffff, 0),
2315
+	.yrgb_vir = VOP_REG(RK3588_CLUSTER3_WIN0_VIR, 0xffff, 0),
2316
+	.uv_vir = VOP_REG(RK3588_CLUSTER3_WIN0_VIR, 0xffff, 16),
2317
+	.y2r_en = VOP_REG(RK3588_CLUSTER3_WIN0_CTRL0, 0x1, 8),
2318
+	.r2y_en = VOP_REG(RK3588_CLUSTER3_WIN0_CTRL0, 0x1, 9),
2319
+	.csc_mode = VOP_REG(RK3588_CLUSTER3_WIN0_CTRL0, 0x3, 10),
2320
+	.axi_yrgb_id = VOP_REG(RK3588_CLUSTER3_WIN0_CTRL2, 0x1f, 0),
2321
+	.axi_uv_id = VOP_REG(RK3588_CLUSTER3_WIN0_CTRL2, 0x1f, 5),
2322
+	.axi_id = VOP_REG(RK3588_CLUSTER3_CTRL, 0x1, 13),
13042323 };
13052324 
13062325 static const struct vop2_win_regs rk3568_esmart_win_data = {
....@@ -1314,11 +2333,10 @@
13142333 	.rb_swap = VOP_REG(RK3568_ESMART0_REGION0_CTRL, 0x1, 14),
13152334 	.uv_swap = VOP_REG(RK3568_ESMART0_REGION0_CTRL, 0x1, 16),
13162335 	.act_info = VOP_REG(RK3568_ESMART0_REGION0_ACT_INFO, 0x1fff1fff, 0),
1317
-	.dsp_info = VOP_REG(RK3568_ESMART0_REGION0_DSP_INFO, 0x0fff0fff, 0),
2336
+	.dsp_info = VOP_REG(RK3568_ESMART0_REGION0_DSP_INFO, 0x1fff1fff, 0),
13182337 	.dsp_st = VOP_REG(RK3568_ESMART0_REGION0_DSP_ST, 0x1fff1fff, 0),
13192338 	.yrgb_mst = VOP_REG(RK3568_ESMART0_REGION0_YRGB_MST, 0xffffffff, 0),
13202339 	.uv_mst = VOP_REG(RK3568_ESMART0_REGION0_CBR_MST, 0xffffffff, 0),
1321
-	.yuv_clip = VOP_REG(RK3568_ESMART0_REGION0_CTRL, 0x1, 17),
13222340 	.yrgb_vir = VOP_REG(RK3568_ESMART0_REGION0_VIR, 0xffff, 0),
13232341 	.uv_vir = VOP_REG(RK3568_ESMART0_REGION0_VIR, 0xffff, 16),
13242342 	.y2r_en = VOP_REG(RK3568_ESMART0_CTRL0, 0x1, 0),
....@@ -1475,8 +2493,8 @@
14752493 	  .name = "Cluster0-win0",
14762494 	  .phys_id = ROCKCHIP_VOP2_CLUSTER0,
14772495 	  .base = 0x00,
1478
-	  .formats = formats_for_cluster,
1479
-	  .nformats = ARRAY_SIZE(formats_for_cluster),
2496
+	  .formats = formats_for_vop3_cluster,
2497
+	  .nformats = ARRAY_SIZE(formats_for_vop3_cluster),
14802498 	  .format_modifiers = format_modifiers_afbc_tiled,
14812499 	  .layer_sel_id = { 0, 0xff, 0xff, 0xff },
14822500 	  .supported_rotations = DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270 |
....@@ -1521,6 +2539,126 @@
15212539 	  .max_downscale_factor = 8,
15222540 	  .type = DRM_PLANE_TYPE_OVERLAY,
15232541 	  .feature = WIN_FEATURE_AFBDC | WIN_FEATURE_CLUSTER_SUB,
2542
+	},
2543
+};
2544
+
2545
+/*
2546
+ * RK3562 VOP with 4 Esmart win.
2547
+ * Every Esmart win support 4 multi-region and each Esmart win can by used by VP0 or VP1
2548
+ *
2549
+ * Scale filter mode:
2550
+ *
2551
+ * * Esmart:
2552
+ * * Support prescale down:
2553
+ * * H: gt2/avg2 or gt4/avg4
2554
+ * * V: gt2 or gt4
2555
+ * * After prescale down:
2556
+ *	* nearest-neighbor/bilinear/bicubic for scale up
2557
+ *	* nearest-neighbor/bilinear/average for scale down
2558
+ */
2559
+static const struct vop2_win_data rk3562_vop_win_data[] = {
2560
+	{
2561
+	  .name = "Esmart0-win0",
2562
+	  .phys_id = ROCKCHIP_VOP2_ESMART0,
2563
+	  .formats = formats_for_esmart,
2564
+	  .nformats = ARRAY_SIZE(formats_for_esmart),
2565
+	  .format_modifiers = format_modifiers,
2566
+	  .base = 0x0,
2567
+	  .layer_sel_id = { 0, 0, 0xff, 0xff },
2568
+	  .supported_rotations = DRM_MODE_REFLECT_Y,
2569
+	  .hsu_filter_mode = VOP2_SCALE_UP_BIC,
2570
+	  .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
2571
+	  .vsu_filter_mode = VOP2_SCALE_UP_BIL,
2572
+	  .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
2573
+	  .regs = &rk3568_esmart_win_data,
2574
+	  .area = rk3568_area_data,
2575
+	  .area_size = ARRAY_SIZE(rk3568_area_data),
2576
+	  .type = DRM_PLANE_TYPE_PRIMARY,
2577
+	  .axi_id = 0,
2578
+	  .axi_yrgb_id = 0x02,
2579
+	  .axi_uv_id = 0x03,
2580
+	  .max_upscale_factor = 8,
2581
+	  .max_downscale_factor = 8,
2582
+	  .dly = { 27, 45, 48 },
2583
+	  .feature = WIN_FEATURE_MULTI_AREA,
2584
+	},
2585
+
2586
+	{
2587
+	  .name = "Esmart1-win0",
2588
+	  .phys_id = ROCKCHIP_VOP2_ESMART1,
2589
+	  .formats = formats_for_esmart,
2590
+	  .nformats = ARRAY_SIZE(formats_for_esmart),
2591
+	  .format_modifiers = format_modifiers,
2592
+	  .base = 0x200,
2593
+	  .layer_sel_id = { 1, 1, 0xff, 0xff },
2594
+	  .supported_rotations = DRM_MODE_REFLECT_Y,
2595
+	  .hsu_filter_mode = VOP2_SCALE_UP_BIC,
2596
+	  .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
2597
+	  .vsu_filter_mode = VOP2_SCALE_UP_BIL,
2598
+	  .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
2599
+	  .regs = &rk3568_esmart_win_data,
2600
+	  .area = rk3568_area_data,
2601
+	  .area_size = ARRAY_SIZE(rk3568_area_data),
2602
+	  .type = DRM_PLANE_TYPE_OVERLAY,
2603
+	  .axi_id = 0,
2604
+	  .axi_yrgb_id = 0x04,
2605
+	  .axi_uv_id = 0x05,
2606
+	  .max_upscale_factor = 8,
2607
+	  .max_downscale_factor = 8,
2608
+	  .dly = { 27, 45, 48 },
2609
+	  .feature = WIN_FEATURE_MULTI_AREA,
2610
+	},
2611
+
2612
+	{
2613
+	  .name = "Esmart2-win0",
2614
+	  .phys_id = ROCKCHIP_VOP2_ESMART2,
2615
+	  .base = 0x400,
2616
+	  .formats = formats_for_esmart,
2617
+	  .nformats = ARRAY_SIZE(formats_for_esmart),
2618
+	  .format_modifiers = format_modifiers,
2619
+	  .layer_sel_id = { 2, 2, 0xff, 0xff },
2620
+	  .supported_rotations = DRM_MODE_REFLECT_Y,
2621
+	  .hsu_filter_mode = VOP2_SCALE_UP_BIC,
2622
+	  .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
2623
+	  .vsu_filter_mode = VOP2_SCALE_UP_BIL,
2624
+	  .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
2625
+	  .regs = &rk3568_esmart_win_data,
2626
+	  .area = rk3568_area_data,
2627
+	  .area_size = ARRAY_SIZE(rk3568_area_data),
2628
+	  .type = DRM_PLANE_TYPE_PRIMARY,
2629
+	  .axi_id = 0,
2630
+	  .axi_yrgb_id = 0x06,
2631
+	  .axi_uv_id = 0x07,
2632
+	  .max_upscale_factor = 8,
2633
+	  .max_downscale_factor = 8,
2634
+	  .dly = { 27, 45, 48 },
2635
+	  .feature = WIN_FEATURE_MULTI_AREA,
2636
+	},
2637
+
2638
+	{
2639
+	  .name = "Esmart3-win0",
2640
+	  .phys_id = ROCKCHIP_VOP2_ESMART3,
2641
+	  .formats = formats_for_esmart,
2642
+	  .nformats = ARRAY_SIZE(formats_for_esmart),
2643
+	  .format_modifiers = format_modifiers,
2644
+	  .base = 0x600,
2645
+	  .layer_sel_id = { 3, 3, 0xff, 0xff },
2646
+	  .supported_rotations = DRM_MODE_REFLECT_Y,
2647
+	  .hsu_filter_mode = VOP2_SCALE_UP_BIC,
2648
+	  .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
2649
+	  .vsu_filter_mode = VOP2_SCALE_UP_BIL,
2650
+	  .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
2651
+	  .regs = &rk3568_esmart_win_data,
2652
+	  .area = rk3568_area_data,
2653
+	  .area_size = ARRAY_SIZE(rk3568_area_data),
2654
+	  .type = DRM_PLANE_TYPE_OVERLAY,
2655
+	  .axi_id = 0,
2656
+	  .axi_yrgb_id = 0x08,
2657
+	  .axi_uv_id = 0x0d,
2658
+	  .max_upscale_factor = 8,
2659
+	  .max_downscale_factor = 8,
2660
+	  .dly = { 27, 45, 48 },
2661
+	  .feature = WIN_FEATURE_MULTI_AREA,
15242662 	},
15252663 };
15262664 
....@@ -1640,7 +2778,7 @@
16402778 	  .base = 0x00,
16412779 	  .formats = formats_for_cluster,
16422780 	  .nformats = ARRAY_SIZE(formats_for_cluster),
1643
-	  .format_modifiers = format_modifiers_afbc,
2781
+	  .format_modifiers = format_modifiers_afbc_no_linear_mode,
16442782 	  .layer_sel_id = { 0, 0, 0, 0xff },
16452783 	  .supported_rotations = DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270 |
16462784 				 DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y,
....@@ -1663,7 +2801,7 @@
16632801 	  .layer_sel_id = { 0xff, 0xff, 0xff, 0xff },
16642802 	  .formats = formats_for_cluster,
16652803 	  .nformats = ARRAY_SIZE(formats_for_cluster),
1666
-	  .format_modifiers = format_modifiers_afbc,
2804
+	  .format_modifiers = format_modifiers_afbc_no_linear_mode,
16672805 	  .supported_rotations = DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y,
16682806 	  .hsu_filter_mode = VOP2_SCALE_UP_BIC,
16692807 	  .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
....@@ -1682,7 +2820,7 @@
16822820 	  .base = 0x00,
16832821 	  .formats = formats_for_cluster,
16842822 	  .nformats = ARRAY_SIZE(formats_for_cluster),
1685
-	  .format_modifiers = format_modifiers_afbc,
2823
+	  .format_modifiers = format_modifiers_afbc_no_linear_mode,
16862824 	  .layer_sel_id = { 1, 1, 1, 0xff },
16872825 	  .supported_rotations = DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270 |
16882826 				 DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y,
....@@ -1704,7 +2842,7 @@
17042842 	  .layer_sel_id = { 0xff, 0xff, 0xff, 0xff },
17052843 	  .formats = formats_for_cluster,
17062844 	  .nformats = ARRAY_SIZE(formats_for_cluster),
1707
-	  .format_modifiers = format_modifiers_afbc,
2845
+	  .format_modifiers = format_modifiers_afbc_no_linear_mode,
17082846 	  .base = 0x80,
17092847 	  .supported_rotations = DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y,
17102848 	  .hsu_filter_mode = VOP2_SCALE_UP_BIC,
....@@ -1716,6 +2854,544 @@
17162854 	  .max_upscale_factor = 4,
17172855 	  .max_downscale_factor = 4,
17182856 	  .feature = WIN_FEATURE_AFBDC | WIN_FEATURE_CLUSTER_SUB | WIN_FEATURE_MIRROR,
2857
+	},
2858
+};
2859
+
2860
+const struct vop2_power_domain_regs rk3588_cluster0_pd_regs = {
2861
+	.pd = VOP_REG(RK3568_SYS_PD_CTRL, 0x1, 0),
2862
+	.status = VOP_REG(RK3568_SYS_STATUS0, 0x1, 8),
2863
+	.pmu_status = VOP_REG(RK3588_PMU_BISR_STATUS5, 0x1, 9),
2864
+	.bisr_en_status = VOP_REG(RK3588_PMU_BISR_CON3, 0x1, 9),
2865
+};
2866
+
2867
+const struct vop2_power_domain_regs rk3588_cluster1_pd_regs = {
2868
+	.pd = VOP_REG(RK3568_SYS_PD_CTRL, 0x1, 1),
2869
+	.status = VOP_REG(RK3568_SYS_STATUS0, 0x1, 9),
2870
+	.pmu_status = VOP_REG(RK3588_PMU_BISR_STATUS5, 0x1, 10),
2871
+	.bisr_en_status = VOP_REG(RK3588_PMU_BISR_CON3, 0x1, 10),
2872
+};
2873
+
2874
+const struct vop2_power_domain_regs rk3588_cluster2_pd_regs = {
2875
+	.pd = VOP_REG(RK3568_SYS_PD_CTRL, 0x1, 2),
2876
+	.status = VOP_REG(RK3568_SYS_STATUS0, 0x1, 10),
2877
+	.pmu_status = VOP_REG(RK3588_PMU_BISR_STATUS5, 0x1, 11),
2878
+	.bisr_en_status = VOP_REG(RK3588_PMU_BISR_CON3, 0x1, 11),
2879
+};
2880
+
2881
+const struct vop2_power_domain_regs rk3588_cluster3_pd_regs = {
2882
+	.pd = VOP_REG(RK3568_SYS_PD_CTRL, 0x1, 3),
2883
+	.status = VOP_REG(RK3568_SYS_STATUS0, 0x1, 11),
2884
+	.pmu_status = VOP_REG(RK3588_PMU_BISR_STATUS5, 0x1, 12),
2885
+	.bisr_en_status = VOP_REG(RK3588_PMU_BISR_CON3, 0x1, 12),
2886
+};
2887
+
2888
+const struct vop2_power_domain_regs rk3588_esmart_pd_regs = {
2889
+	.pd = VOP_REG(RK3568_SYS_PD_CTRL, 0x1, 7),
2890
+	.status = VOP_REG(RK3568_SYS_STATUS0, 0x1, 15),
2891
+	.pmu_status = VOP_REG(RK3588_PMU_BISR_STATUS5, 0x1, 15),
2892
+	.bisr_en_status = VOP_REG(RK3588_PMU_BISR_CON3, 0x1, 15),
2893
+};
2894
+
2895
+const struct vop2_power_domain_regs rk3588_dsc_8k_pd_regs = {
2896
+	.pd = VOP_REG(RK3568_SYS_PD_CTRL, 0x1, 5),
2897
+	.status = VOP_REG(RK3568_SYS_STATUS0, 0x1, 13),
2898
+	.pmu_status = VOP_REG(RK3588_PMU_BISR_STATUS5, 0x1, 13),
2899
+	.bisr_en_status = VOP_REG(RK3588_PMU_BISR_CON3, 0x1, 13),
2900
+};
2901
+
2902
+const struct vop2_power_domain_regs rk3588_dsc_4k_pd_regs = {
2903
+	.pd = VOP_REG(RK3568_SYS_PD_CTRL, 0x1, 6),
2904
+	.status = VOP_REG(RK3568_SYS_STATUS0, 0x1, 14),
2905
+	.pmu_status = VOP_REG(RK3588_PMU_BISR_STATUS5, 0x1, 14),
2906
+	.bisr_en_status = VOP_REG(RK3588_PMU_BISR_CON3, 0x1, 14),
2907
+};
2908
+
2909
+/*
2910
+ * There are 7 internal power domains on rk3588 vop,
2911
+ * Cluster0/1/2/3 each have on pd, and PD_CLUSTER0 as parent,
2912
+ * that means PD_CLUSTER0 should turn on first before
2913
+ * PD_CLUSTER1/2/3 turn on.
2914
+ *
2915
+ * Esmart1/2/3 share one pd PD_ESMART, and Esmart0 has no PD
2916
+ * DSC_8K/DSC_4K each have on pd.
2917
+ */
2918
+static const struct vop2_power_domain_data rk3588_vop_pd_data[] = {
2919
+	{
2920
+	  .id = VOP2_PD_CLUSTER0,
2921
+	  .module_id_mask = BIT(ROCKCHIP_VOP2_CLUSTER0),
2922
+	  .regs = &rk3588_cluster0_pd_regs,
2923
+	},
2924
+
2925
+	{
2926
+	  .id = VOP2_PD_CLUSTER1,
2927
+	  .module_id_mask = BIT(ROCKCHIP_VOP2_CLUSTER1),
2928
+	  .parent_id = VOP2_PD_CLUSTER0,
2929
+	  .regs = &rk3588_cluster1_pd_regs,
2930
+	},
2931
+
2932
+	{
2933
+	  .id = VOP2_PD_CLUSTER2,
2934
+	  .module_id_mask = BIT(ROCKCHIP_VOP2_CLUSTER2),
2935
+	  .parent_id = VOP2_PD_CLUSTER0,
2936
+	  .regs = &rk3588_cluster2_pd_regs,
2937
+	},
2938
+
2939
+	{
2940
+	  .id = VOP2_PD_CLUSTER3,
2941
+	  .module_id_mask = BIT(ROCKCHIP_VOP2_CLUSTER3),
2942
+	  .parent_id = VOP2_PD_CLUSTER0,
2943
+	  .regs = &rk3588_cluster3_pd_regs,
2944
+	},
2945
+
2946
+	{
2947
+	  .id = VOP2_PD_ESMART,
2948
+	  .module_id_mask = BIT(ROCKCHIP_VOP2_ESMART1) |
2949
+			    BIT(ROCKCHIP_VOP2_ESMART2) |
2950
+			    BIT(ROCKCHIP_VOP2_ESMART3),
2951
+	  .regs = &rk3588_esmart_pd_regs,
2952
+	},
2953
+
2954
+	{
2955
+	  .id = VOP2_PD_DSC_8K,
2956
+	  .module_id_mask = BIT(ROCKCHIP_VOP2_DSC_8K),
2957
+	  .regs = &rk3588_dsc_8k_pd_regs,
2958
+	},
2959
+
2960
+	{
2961
+	  .id = VOP2_PD_DSC_4K,
2962
+	  .module_id_mask = BIT(ROCKCHIP_VOP2_DSC_4K),
2963
+	  .regs = &rk3588_dsc_4k_pd_regs,
2964
+	},
2965
+};
2966
+
2967
+const struct vop2_power_domain_regs rk3588_mem_pg_vp0_regs = {
2968
+	.pd = VOP_REG(RK3588_PMU_SUBMEM_PWR_GATE_CON1, 0x1, 15),
2969
+	.status = VOP_REG(RK3588_PMU_SUBMEM_PWR_GATE_STATUS, 0x1, 19),
2970
+};
2971
+
2972
+const struct vop2_power_domain_regs rk3588_mem_pg_vp1_regs = {
2973
+	.pd = VOP_REG(RK3588_PMU_SUBMEM_PWR_GATE_CON2, 0x1, 0),
2974
+	.status = VOP_REG(RK3588_PMU_SUBMEM_PWR_GATE_STATUS, 0x1, 20),
2975
+};
2976
+
2977
+const struct vop2_power_domain_regs rk3588_mem_pg_vp2_regs = {
2978
+	.pd = VOP_REG(RK3588_PMU_SUBMEM_PWR_GATE_CON2, 0x1, 1),
2979
+	.status = VOP_REG(RK3588_PMU_SUBMEM_PWR_GATE_STATUS, 0x1, 21),
2980
+};
2981
+
2982
+const struct vop2_power_domain_regs rk3588_mem_pg_vp3_regs = {
2983
+	.pd = VOP_REG(RK3588_PMU_SUBMEM_PWR_GATE_CON2, 0x1, 2),
2984
+	.status = VOP_REG(RK3588_PMU_SUBMEM_PWR_GATE_STATUS, 0x1, 22),
2985
+};
2986
+
2987
+const struct vop2_power_domain_regs rk3588_mem_pg_db0_regs = {
2988
+	.pd = VOP_REG(RK3588_PMU_SUBMEM_PWR_GATE_CON2, 0x1, 3),
2989
+	.status = VOP_REG(RK3588_PMU_SUBMEM_PWR_GATE_STATUS, 0x1, 23),
2990
+};
2991
+
2992
+const struct vop2_power_domain_regs rk3588_mem_pg_db1_regs = {
2993
+	.pd = VOP_REG(RK3588_PMU_SUBMEM_PWR_GATE_CON2, 0x1, 4),
2994
+	.status = VOP_REG(RK3588_PMU_SUBMEM_PWR_GATE_STATUS, 0x1, 24),
2995
+};
2996
+
2997
+const struct vop2_power_domain_regs rk3588_mem_pg_db2_regs = {
2998
+	.pd = VOP_REG(RK3588_PMU_SUBMEM_PWR_GATE_CON2, 0x1, 5),
2999
+	.status = VOP_REG(RK3588_PMU_SUBMEM_PWR_GATE_STATUS, 0x1, 25),
3000
+};
3001
+
3002
+const struct vop2_power_domain_regs rk3588_mem_pg_wb_regs = {
3003
+	.pd = VOP_REG(RK3588_PMU_SUBMEM_PWR_GATE_CON2, 0x1, 6),
3004
+	.status = VOP_REG(RK3588_PMU_SUBMEM_PWR_GATE_STATUS, 0x1, 26),
3005
+};
3006
+
3007
+/*
3008
+ * All power gates will power on when PD_VOP is turn on.
3009
+ * Corresponding mem_pwr_ack_bypass bit should be enabled
3010
+ * if power gate powe down before PD_VOP.
3011
+ * power gates take effect immediately, this means there
3012
+ * is no synchronization between vop frame scanout, so
3013
+ * we can only enable a power gate before we enable
3014
+ * a module, and turn off power gate after the module
3015
+ * is actually disabled.
3016
+ */
3017
+static const struct vop2_power_domain_data rk3588_vop_mem_pg_data[] = {
3018
+	{
3019
+	  .id = VOP2_MEM_PG_VP0,
3020
+	  .regs = &rk3588_mem_pg_vp0_regs,
3021
+	},
3022
+
3023
+	{
3024
+	  .id = VOP2_MEM_PG_VP1,
3025
+	  .regs = &rk3588_mem_pg_vp1_regs,
3026
+	},
3027
+
3028
+	{
3029
+	  .id = VOP2_MEM_PG_VP2,
3030
+	  .regs = &rk3588_mem_pg_vp2_regs,
3031
+	},
3032
+
3033
+	{
3034
+	  .id = VOP2_MEM_PG_VP3,
3035
+	  .regs = &rk3588_mem_pg_vp3_regs,
3036
+	},
3037
+
3038
+	{
3039
+	  .id = VOP2_MEM_PG_DB0,
3040
+	  .regs = &rk3588_mem_pg_db0_regs,
3041
+	},
3042
+
3043
+	{
3044
+	  .id = VOP2_MEM_PG_DB1,
3045
+	  .regs = &rk3588_mem_pg_db1_regs,
3046
+	},
3047
+
3048
+	{
3049
+	  .id = VOP2_MEM_PG_DB2,
3050
+	  .regs = &rk3588_mem_pg_db2_regs,
3051
+	},
3052
+
3053
+	{
3054
+	  .id = VOP2_MEM_PG_WB,
3055
+	  .regs = &rk3588_mem_pg_wb_regs,
3056
+	},
3057
+};
3058
+
3059
+/*
3060
+ * rk3588 vop with 4 cluster, 4 esmart win.
3061
+ * Every cluster can work as 4K win or split into two win.
3062
+ * All win in cluster support AFBCD.
3063
+ *
3064
+ * Every esmart win and smart win support 4 Multi-region.
3065
+ *
3066
+ * Scale filter mode:
3067
+ *
3068
+ * * Cluster:  bicubic for horizontal scale up, others use bilinear
3069
+ * * ESmart:
3070
+ *    * nearest-neighbor/bilinear/bicubic for scale up
3071
+ *    * nearest-neighbor/bilinear/average for scale down
3072
+ *
3073
+ * AXI Read ID assignment:
3074
+ * Two AXI bus:
3075
+ * AXI0 is a read/write bus with a higher performance.
3076
+ * AXI1 is a read only bus.
3077
+ *
3078
+ * Every window on a AXI bus must assigned two unique
3079
+ * read id(yrgb_id/uv_id, valid id are 0x1~0xe).
3080
+ *
3081
+ * AXI0:
3082
+ * Cluster0/1, Esmart0/1, WriteBack
3083
+ *
3084
+ * AXI 1:
3085
+ * Cluster2/3, Esmart2/3
3086
+ *
3087
+ * @TODO describe the wind like cpu-map dt nodes;
3088
+ */
3089
+static const struct vop2_win_data rk3588_vop_win_data[] = {
3090
+	{
3091
+	  .name = "Cluster0-win0",
3092
+	  .phys_id = ROCKCHIP_VOP2_CLUSTER0,
3093
+	  .splice_win_id = ROCKCHIP_VOP2_CLUSTER1,
3094
+	  .base = 0x00,
3095
+	  .formats = formats_for_cluster,
3096
+	  .nformats = ARRAY_SIZE(formats_for_cluster),
3097
+	  .format_modifiers = format_modifiers_afbc,
3098
+	  .layer_sel_id = { 0, 0, 0, 0 },
3099
+	  .supported_rotations = DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270 |
3100
+				 DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y,
3101
+	  .hsu_filter_mode = VOP2_SCALE_UP_BIC,
3102
+	  .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
3103
+	  .vsu_filter_mode = VOP2_SCALE_UP_BIL,
3104
+	  .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
3105
+	  .regs = &rk3568_cluster0_win_data,
3106
+	  .pd_id = VOP2_PD_CLUSTER0,
3107
+	  .axi_id = 0,
3108
+	  .axi_yrgb_id = 2,
3109
+	  .axi_uv_id = 3,
3110
+	  .max_upscale_factor = 4,
3111
+	  .max_downscale_factor = 4,
3112
+	  .dly = { 4, 26, 29 },
3113
+	  .type = DRM_PLANE_TYPE_OVERLAY,
3114
+	  .feature = WIN_FEATURE_AFBDC | WIN_FEATURE_CLUSTER_MAIN | WIN_FEATURE_SPLICE_LEFT,
3115
+	},
3116
+
3117
+	{
3118
+	  .name = "Cluster0-win1",
3119
+	  .phys_id = ROCKCHIP_VOP2_CLUSTER0,
3120
+	  .base = 0x80,
3121
+	  .layer_sel_id = { 0xff, 0xff, 0xff, 0xff },
3122
+	  .formats = formats_for_cluster,
3123
+	  .nformats = ARRAY_SIZE(formats_for_cluster),
3124
+	  .format_modifiers = format_modifiers_afbc,
3125
+	  .supported_rotations = DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y,
3126
+	  .hsu_filter_mode = VOP2_SCALE_UP_BIC,
3127
+	  .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
3128
+	  .vsu_filter_mode = VOP2_SCALE_UP_BIL,
3129
+	  .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
3130
+	  .regs = &rk3568_cluster0_win_data,
3131
+	  .axi_id = 0,
3132
+	  .axi_yrgb_id = 4,
3133
+	  .axi_uv_id = 5,
3134
+	  .max_upscale_factor = 4,
3135
+	  .max_downscale_factor = 4,
3136
+	  .type = DRM_PLANE_TYPE_OVERLAY,
3137
+	  .feature = WIN_FEATURE_AFBDC | WIN_FEATURE_CLUSTER_SUB,
3138
+	},
3139
+
3140
+	{
3141
+	  .name = "Cluster1-win0",
3142
+	  .phys_id = ROCKCHIP_VOP2_CLUSTER1,
3143
+	  .base = 0x00,
3144
+	  .formats = formats_for_cluster,
3145
+	  .nformats = ARRAY_SIZE(formats_for_cluster),
3146
+	  .format_modifiers = format_modifiers_afbc,
3147
+	  .layer_sel_id = { 1, 1, 1, 1 },
3148
+	  .supported_rotations = DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270 |
3149
+				 DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y,
3150
+	  .hsu_filter_mode = VOP2_SCALE_UP_BIC,
3151
+	  .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
3152
+	  .vsu_filter_mode = VOP2_SCALE_UP_BIL,
3153
+	  .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
3154
+	  .regs = &rk3568_cluster1_win_data,
3155
+	  .pd_id = VOP2_PD_CLUSTER1,
3156
+	  .axi_id = 0,
3157
+	  .axi_yrgb_id = 6,
3158
+	  .axi_uv_id = 7,
3159
+	  .type = DRM_PLANE_TYPE_OVERLAY,
3160
+	  .max_upscale_factor = 4,
3161
+	  .max_downscale_factor = 4,
3162
+	  .dly = { 4, 26, 29 },
3163
+	  .feature = WIN_FEATURE_AFBDC | WIN_FEATURE_CLUSTER_MAIN,
3164
+	},
3165
+
3166
+	{
3167
+	  .name = "Cluster1-win1",
3168
+	  .phys_id = ROCKCHIP_VOP2_CLUSTER1,
3169
+	  .layer_sel_id = { 0xff, 0xff, 0xff, 0xff },
3170
+	  .formats = formats_for_cluster,
3171
+	  .nformats = ARRAY_SIZE(formats_for_cluster),
3172
+	  .format_modifiers = format_modifiers_afbc,
3173
+	  .base = 0x80,
3174
+	  .supported_rotations = DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y,
3175
+	  .hsu_filter_mode = VOP2_SCALE_UP_BIC,
3176
+	  .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
3177
+	  .vsu_filter_mode = VOP2_SCALE_UP_BIL,
3178
+	  .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
3179
+	  .regs = &rk3568_cluster1_win_data,
3180
+	  .type = DRM_PLANE_TYPE_OVERLAY,
3181
+	  .axi_id = 0,
3182
+	  .axi_yrgb_id = 8,
3183
+	  .axi_uv_id = 9,
3184
+	  .max_upscale_factor = 4,
3185
+	  .max_downscale_factor = 4,
3186
+	  .feature = WIN_FEATURE_AFBDC | WIN_FEATURE_CLUSTER_SUB,
3187
+	},
3188
+
3189
+	{
3190
+	  .name = "Cluster2-win0",
3191
+	  .phys_id = ROCKCHIP_VOP2_CLUSTER2,
3192
+	  .pd_id = VOP2_PD_CLUSTER2,
3193
+	  .splice_win_id = ROCKCHIP_VOP2_CLUSTER3,
3194
+	  .base = 0x00,
3195
+	  .formats = formats_for_cluster,
3196
+	  .nformats = ARRAY_SIZE(formats_for_cluster),
3197
+	  .format_modifiers = format_modifiers_afbc,
3198
+	  .layer_sel_id = { 4, 4, 4, 4 },
3199
+	  .supported_rotations = DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270 |
3200
+				 DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y,
3201
+	  .hsu_filter_mode = VOP2_SCALE_UP_BIC,
3202
+	  .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
3203
+	  .vsu_filter_mode = VOP2_SCALE_UP_BIL,
3204
+	  .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
3205
+	  .regs = &rk3588_cluster2_win_data,
3206
+	  .type = DRM_PLANE_TYPE_OVERLAY,
3207
+	  .axi_id = 1,
3208
+	  .axi_yrgb_id = 2,
3209
+	  .axi_uv_id = 3,
3210
+	  .max_upscale_factor = 4,
3211
+	  .max_downscale_factor = 4,
3212
+	  .dly = { 4, 26, 29 },
3213
+	  .feature = WIN_FEATURE_AFBDC | WIN_FEATURE_CLUSTER_MAIN | WIN_FEATURE_SPLICE_LEFT,
3214
+	},
3215
+
3216
+	{
3217
+	  .name = "Cluster2-win1",
3218
+	  .phys_id = ROCKCHIP_VOP2_CLUSTER2,
3219
+	  .layer_sel_id = { 0xff, 0xff, 0xff, 0xff },
3220
+	  .formats = formats_for_cluster,
3221
+	  .nformats = ARRAY_SIZE(formats_for_cluster),
3222
+	  .format_modifiers = format_modifiers_afbc,
3223
+	  .base = 0x80,
3224
+	  .supported_rotations = DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y,
3225
+	  .hsu_filter_mode = VOP2_SCALE_UP_BIC,
3226
+	  .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
3227
+	  .vsu_filter_mode = VOP2_SCALE_UP_BIL,
3228
+	  .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
3229
+	  .regs = &rk3588_cluster2_win_data,
3230
+	  .type = DRM_PLANE_TYPE_OVERLAY,
3231
+	  .axi_id = 1,
3232
+	  .axi_yrgb_id = 4,
3233
+	  .axi_uv_id = 5,
3234
+	  .max_upscale_factor = 4,
3235
+	  .max_downscale_factor = 4,
3236
+	  .feature = WIN_FEATURE_AFBDC | WIN_FEATURE_CLUSTER_SUB,
3237
+	},
3238
+
3239
+	{
3240
+	  .name = "Cluster3-win0",
3241
+	  .phys_id = ROCKCHIP_VOP2_CLUSTER3,
3242
+	  .pd_id = VOP2_PD_CLUSTER3,
3243
+	  .base = 0x00,
3244
+	  .formats = formats_for_cluster,
3245
+	  .nformats = ARRAY_SIZE(formats_for_cluster),
3246
+	  .format_modifiers = format_modifiers_afbc,
3247
+	  .layer_sel_id = { 5, 5, 5, 5 },
3248
+	  .supported_rotations = DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270 |
3249
+				 DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y,
3250
+	  .hsu_filter_mode = VOP2_SCALE_UP_BIC,
3251
+	  .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
3252
+	  .vsu_filter_mode = VOP2_SCALE_UP_BIL,
3253
+	  .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
3254
+	  .regs = &rk3588_cluster3_win_data,
3255
+	  .type = DRM_PLANE_TYPE_OVERLAY,
3256
+	  .axi_id = 1,
3257
+	  .axi_yrgb_id = 6,
3258
+	  .axi_uv_id = 7,
3259
+	  .max_upscale_factor = 4,
3260
+	  .max_downscale_factor = 4,
3261
+	  .dly = { 4, 26, 29 },
3262
+	  .feature = WIN_FEATURE_AFBDC | WIN_FEATURE_CLUSTER_MAIN,
3263
+	},
3264
+
3265
+	{
3266
+	  .name = "Cluster3-win1",
3267
+	  .phys_id = ROCKCHIP_VOP2_CLUSTER3,
3268
+	  .layer_sel_id = { 0xff, 0xff, 0xff, 0xff },
3269
+	  .formats = formats_for_cluster,
3270
+	  .nformats = ARRAY_SIZE(formats_for_cluster),
3271
+	  .format_modifiers = format_modifiers_afbc,
3272
+	  .base = 0x80,
3273
+	  .supported_rotations = DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y,
3274
+	  .hsu_filter_mode = VOP2_SCALE_UP_BIC,
3275
+	  .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
3276
+	  .vsu_filter_mode = VOP2_SCALE_UP_BIL,
3277
+	  .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
3278
+	  .regs = &rk3588_cluster3_win_data,
3279
+	  .type = DRM_PLANE_TYPE_OVERLAY,
3280
+	  .axi_id = 1,
3281
+	  .axi_yrgb_id = 8,
3282
+	  .axi_uv_id = 9,
3283
+	  .max_upscale_factor = 4,
3284
+	  .max_downscale_factor = 4,
3285
+	  .feature = WIN_FEATURE_AFBDC | WIN_FEATURE_CLUSTER_SUB,
3286
+	},
3287
+
3288
+	{
3289
+	  .name = "Esmart0-win0",
3290
+	  .phys_id = ROCKCHIP_VOP2_ESMART0,
3291
+	  .splice_win_id = ROCKCHIP_VOP2_ESMART1,
3292
+	  .formats = formats_for_esmart,
3293
+	  .nformats = ARRAY_SIZE(formats_for_esmart),
3294
+	  .format_modifiers = format_modifiers,
3295
+	  .base = 0x0,
3296
+	  .layer_sel_id = { 2, 2, 2, 2 },
3297
+	  .supported_rotations = DRM_MODE_REFLECT_Y,
3298
+	  .hsu_filter_mode = VOP2_SCALE_UP_BIC,
3299
+	  .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
3300
+	  .vsu_filter_mode = VOP2_SCALE_UP_BIL,
3301
+	  .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
3302
+	  .regs = &rk3568_esmart_win_data,
3303
+	  .area = rk3568_area_data,
3304
+	  .area_size = ARRAY_SIZE(rk3568_area_data),
3305
+	  .type = DRM_PLANE_TYPE_PRIMARY,
3306
+	  .axi_id = 0,
3307
+	  .axi_yrgb_id = 0x0a,
3308
+	  .axi_uv_id = 0x0b,
3309
+	  .max_upscale_factor = 8,
3310
+	  .max_downscale_factor = 8,
3311
+	  .dly = { 23, 45, 48 },
3312
+	  .feature = WIN_FEATURE_SPLICE_LEFT | WIN_FEATURE_MULTI_AREA,
3313
+	},
3314
+
3315
+	{
3316
+	  .name = "Esmart2-win0",
3317
+	  .phys_id = ROCKCHIP_VOP2_ESMART2,
3318
+	  .pd_id = VOP2_PD_ESMART,
3319
+	  .splice_win_id = ROCKCHIP_VOP2_ESMART3,
3320
+	  .base = 0x400,
3321
+	  .formats = formats_for_esmart,
3322
+	  .nformats = ARRAY_SIZE(formats_for_esmart),
3323
+	  .format_modifiers = format_modifiers,
3324
+	  .layer_sel_id = { 6, 6, 6, 6 },
3325
+	  .supported_rotations = DRM_MODE_REFLECT_Y,
3326
+	  .hsu_filter_mode = VOP2_SCALE_UP_BIC,
3327
+	  .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
3328
+	  .vsu_filter_mode = VOP2_SCALE_UP_BIL,
3329
+	  .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
3330
+	  .regs = &rk3568_esmart_win_data,
3331
+	  .area = rk3568_area_data,
3332
+	  .area_size = ARRAY_SIZE(rk3568_area_data),
3333
+	  .type = DRM_PLANE_TYPE_PRIMARY,
3334
+	  .axi_id = 1,
3335
+	  .axi_yrgb_id = 0x0a,
3336
+	  .axi_uv_id = 0x0b,
3337
+	  .max_upscale_factor = 8,
3338
+	  .max_downscale_factor = 8,
3339
+	  .dly = { 23, 45, 48 },
3340
+	  .feature = WIN_FEATURE_SPLICE_LEFT | WIN_FEATURE_MULTI_AREA,
3341
+	},
3342
+
3343
+	{
3344
+	  .name = "Esmart1-win0",
3345
+	  .phys_id = ROCKCHIP_VOP2_ESMART1,
3346
+	  .pd_id = VOP2_PD_ESMART,
3347
+	  .formats = formats_for_esmart,
3348
+	  .nformats = ARRAY_SIZE(formats_for_esmart),
3349
+	  .format_modifiers = format_modifiers,
3350
+	  .base = 0x200,
3351
+	  .layer_sel_id = { 3, 3, 3, 3 },
3352
+	  .supported_rotations = DRM_MODE_REFLECT_Y,
3353
+	  .hsu_filter_mode = VOP2_SCALE_UP_BIC,
3354
+	  .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
3355
+	  .vsu_filter_mode = VOP2_SCALE_UP_BIL,
3356
+	  .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
3357
+	  .regs = &rk3568_esmart_win_data,
3358
+	  .area = rk3568_area_data,
3359
+	  .area_size = ARRAY_SIZE(rk3568_area_data),
3360
+	  .type = DRM_PLANE_TYPE_PRIMARY,
3361
+	  .axi_id = 0,
3362
+	  .axi_yrgb_id = 0x0c,
3363
+	  .axi_uv_id = 0x01,
3364
+	  .max_upscale_factor = 8,
3365
+	  .max_downscale_factor = 8,
3366
+	  .dly = { 23, 45, 48 },
3367
+	  .feature = WIN_FEATURE_MULTI_AREA,
3368
+	},
3369
+
3370
+	{
3371
+	  .name = "Esmart3-win0",
3372
+	  .phys_id = ROCKCHIP_VOP2_ESMART3,
3373
+	  .pd_id = VOP2_PD_ESMART,
3374
+	  .formats = formats_for_esmart,
3375
+	  .nformats = ARRAY_SIZE(formats_for_esmart),
3376
+	  .format_modifiers = format_modifiers,
3377
+	  .base = 0x600,
3378
+	  .layer_sel_id = { 7, 7, 7, 7 },
3379
+	  .supported_rotations = DRM_MODE_REFLECT_Y,
3380
+	  .hsu_filter_mode = VOP2_SCALE_UP_BIC,
3381
+	  .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
3382
+	  .vsu_filter_mode = VOP2_SCALE_UP_BIL,
3383
+	  .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
3384
+	  .regs = &rk3568_esmart_win_data,
3385
+	  .area = rk3568_area_data,
3386
+	  .area_size = ARRAY_SIZE(rk3568_area_data),
3387
+	  .type = DRM_PLANE_TYPE_PRIMARY,
3388
+	  .axi_id = 1,
3389
+	  .axi_yrgb_id = 0x0c,
3390
+	  .axi_uv_id = 0x0d,
3391
+	  .max_upscale_factor = 8,
3392
+	  .max_downscale_factor = 8,
3393
+	  .dly = { 23, 45, 48 },
3394
+	  .feature = WIN_FEATURE_MULTI_AREA,
17193395 	},
17203396 };
17213397 
....@@ -1750,7 +3426,50 @@
17503426 	.win_dly[ROCKCHIP_VOP2_ESMART3] = VOP_REG(RK3528_OVL_SYS_ESMART3_CTRL, 0xff, 0),
17513427 };
17523428 
1753
-static const struct vop_grf_ctrl rk3568_grf_ctrl = {
3429
+static const struct vop_grf_ctrl rk3562_sys_grf_ctrl = {
3430
+	.grf_bt656_clk_inv = VOP_REG(RK3562_GRF_IOC_VO_IO_CON, 0x1, 3),
3431
+	.grf_bt1120_clk_inv = VOP_REG(RK3562_GRF_IOC_VO_IO_CON, 0x1, 3),
3432
+	.grf_dclk_inv = VOP_REG(RK3562_GRF_IOC_VO_IO_CON, 0x1, 3),
3433
+};
3434
+
3435
+static const struct vop2_ctrl rk3562_vop_ctrl = {
3436
+	.cfg_done_en = VOP_REG(RK3568_REG_CFG_DONE, 0x1, 15),
3437
+	.wb_cfg_done = VOP_REG_MASK(RK3568_REG_CFG_DONE, 0x1, 14),
3438
+	.auto_gating_en = VOP_REG(RK3568_SYS_AUTO_GATING_CTRL, 0x1, 31),
3439
+	.aclk_pre_auto_gating_en = VOP_REG(RK3568_SYS_AUTO_GATING_CTRL, 0x1, 7),
3440
+	.if_ctrl_cfg_done_imd = VOP_REG(RK3568_DSP_IF_POL, 0x1, 28),
3441
+	.version = VOP_REG(RK3568_VERSION_INFO, 0xffff, 16),
3442
+	.lut_dma_en = VOP_REG(RK3568_SYS_AXI_LUT_CTRL, 0x1, 0),
3443
+	.rgb_en = VOP_REG(RK3568_DSP_IF_EN, 0x1, 0),
3444
+	.mipi0_en = VOP_REG(RK3568_DSP_IF_EN, 0x1, 4),
3445
+	.lvds0_en = VOP_REG(RK3568_DSP_IF_EN, 0x1, 5),
3446
+	.bt1120_en = VOP_REG(RK3568_DSP_IF_EN, 0x1, 6),
3447
+	.bt656_en = VOP_REG(RK3568_DSP_IF_EN, 0x1, 7),
3448
+	.rgb_mux = VOP_REG(RK3568_DSP_IF_EN, 0x3, 8),
3449
+	.mipi0_mux = VOP_REG(RK3568_DSP_IF_EN, 0x3, 16),
3450
+	.lvds0_mux = VOP_REG(RK3568_DSP_IF_EN, 0x3, 18),
3451
+	.bt656_yc_swap = VOP_REG(RK3568_DSP_IF_CTRL, 0x1, 5),
3452
+	.bt656_dclk_pol = VOP_REG(RK3568_DSP_IF_CTRL, 0x1, 6),
3453
+	.bt1120_yc_swap = VOP_REG(RK3568_DSP_IF_CTRL, 0x1, 9),
3454
+	.bt1120_dclk_pol = VOP_REG(RK3568_DSP_IF_CTRL, 0x1, 10),
3455
+	.rgb_pin_pol = VOP_REG(RK3568_DSP_IF_POL, 0x7, 0),
3456
+	.lvds_pin_pol = VOP_REG(RK3568_DSP_IF_POL, 0x7, 0),
3457
+	.lvds_dclk_pol = VOP_REG(RK3568_DSP_IF_POL, 0x1, 3),
3458
+	.mipi_pin_pol = VOP_REG(RK3568_DSP_IF_POL, 0x7, 12),
3459
+	.mipi_dclk_pol = VOP_REG(RK3568_DSP_IF_POL, 0x1, 15),
3460
+	.gamma_port_sel = VOP_REG(RK3568_LUT_PORT_SEL, 0x3, 12),
3461
+	.esmart_lb_mode = VOP_REG(RK3568_LUT_PORT_SEL, 0x3, 26),
3462
+	.win_vp_id[ROCKCHIP_VOP2_ESMART0] = VOP_REG(RK3528_OVL_SYS_PORT_SEL_IMD, 0x3, 16),
3463
+	.win_vp_id[ROCKCHIP_VOP2_ESMART1] = VOP_REG(RK3528_OVL_SYS_PORT_SEL_IMD, 0x3, 20),
3464
+	.win_vp_id[ROCKCHIP_VOP2_ESMART2] = VOP_REG(RK3528_OVL_SYS_PORT_SEL_IMD, 0x3, 24),
3465
+	.win_vp_id[ROCKCHIP_VOP2_ESMART3] = VOP_REG(RK3528_OVL_SYS_PORT_SEL_IMD, 0x3, 28),
3466
+	.win_dly[ROCKCHIP_VOP2_ESMART0] = VOP_REG(RK3528_OVL_SYS_ESMART0_CTRL, 0xff, 0),
3467
+	.win_dly[ROCKCHIP_VOP2_ESMART1] = VOP_REG(RK3528_OVL_SYS_ESMART1_CTRL, 0xff, 0),
3468
+	.win_dly[ROCKCHIP_VOP2_ESMART2] = VOP_REG(RK3528_OVL_SYS_ESMART2_CTRL, 0xff, 0),
3469
+	.win_dly[ROCKCHIP_VOP2_ESMART3] = VOP_REG(RK3528_OVL_SYS_ESMART3_CTRL, 0xff, 0),
3470
+};
3471
+
3472
+static const struct vop_grf_ctrl rk3568_sys_grf_ctrl = {
17543473 	.grf_bt656_clk_inv = VOP_REG(RK3568_GRF_VO_CON1, 0x1, 1),
17553474 	.grf_bt1120_clk_inv = VOP_REG(RK3568_GRF_VO_CON1, 0x1, 2),
17563475 	.grf_dclk_inv = VOP_REG(RK3568_GRF_VO_CON1, 0x1, 3),
....@@ -1807,13 +3526,116 @@
18073526 	.win_vp_id[ROCKCHIP_VOP2_ESMART1] = VOP_REG(RK3568_OVL_PORT_SEL, 0x3, 26),
18083527 	.win_vp_id[ROCKCHIP_VOP2_SMART0] = VOP_REG(RK3568_OVL_PORT_SEL, 0x3, 28),
18093528 	.win_vp_id[ROCKCHIP_VOP2_SMART1] = VOP_REG(RK3568_OVL_PORT_SEL, 0x3, 30),
1810
-	.win_dly[0] = VOP_REG(RK3568_CLUSTER_DLY_NUM, 0xffff, 0),
1811
-	.win_dly[1] = VOP_REG(RK3568_CLUSTER_DLY_NUM, 0xffff, 16),
1812
-	.win_dly[2] = VOP_REG(RK3568_SMART_DLY_NUM, 0xff, 0),
1813
-	.win_dly[3] = VOP_REG(RK3568_SMART_DLY_NUM, 0xff, 8),
1814
-	.win_dly[4] = VOP_REG(RK3568_SMART_DLY_NUM, 0xff, 16),
1815
-	.win_dly[5] = VOP_REG(RK3568_SMART_DLY_NUM, 0xff, 24),
3529
+	.win_dly[ROCKCHIP_VOP2_CLUSTER0] = VOP_REG(RK3568_CLUSTER_DLY_NUM, 0xffff, 0),
3530
+	.win_dly[ROCKCHIP_VOP2_CLUSTER1] = VOP_REG(RK3568_CLUSTER_DLY_NUM, 0xffff, 16),
3531
+	.win_dly[ROCKCHIP_VOP2_ESMART0] = VOP_REG(RK3568_SMART_DLY_NUM, 0xff, 0),
3532
+	.win_dly[ROCKCHIP_VOP2_ESMART1] = VOP_REG(RK3568_SMART_DLY_NUM, 0xff, 8),
3533
+	.win_dly[ROCKCHIP_VOP2_SMART0] = VOP_REG(RK3568_SMART_DLY_NUM, 0xff, 16),
3534
+	.win_dly[ROCKCHIP_VOP2_SMART1] = VOP_REG(RK3568_SMART_DLY_NUM, 0xff, 24),
18163535 	.otp_en = VOP_REG(RK3568_OTP_WIN_EN, 0x1, 0),
3536
+};
3537
+
3538
+static const struct vop_grf_ctrl rk3588_sys_grf_ctrl = {
3539
+	.grf_bt656_clk_inv = VOP_REG(RK3588_GRF_SOC_CON1, 0x1, 14),
3540
+	.grf_bt1120_clk_inv = VOP_REG(RK3588_GRF_SOC_CON1, 0x1, 14),
3541
+	.grf_dclk_inv = VOP_REG(RK3588_GRF_SOC_CON1, 0x1, 14),
3542
+};
3543
+
3544
+static const struct vop_grf_ctrl rk3588_vop_grf_ctrl = {
3545
+	.grf_edp0_en = VOP_REG(RK3588_GRF_VOP_CON2, 0x1, 0),
3546
+	.grf_hdmi0_en = VOP_REG(RK3588_GRF_VOP_CON2, 0x1, 1),
3547
+	.grf_hdmi0_dsc_en = VOP_REG(RK3588_GRF_VOP_CON2, 0x1, 2),
3548
+	.grf_edp1_en = VOP_REG(RK3588_GRF_VOP_CON2, 0x1, 3),
3549
+	.grf_hdmi1_en = VOP_REG(RK3588_GRF_VOP_CON2, 0x1, 4),
3550
+	.grf_hdmi1_dsc_en = VOP_REG(RK3588_GRF_VOP_CON2, 0x1, 4),
3551
+};
3552
+
3553
+static const struct vop_grf_ctrl rk3588_vo1_grf_ctrl = {
3554
+	.grf_hdmi0_pin_pol = VOP_REG(RK3588_GRF_VO1_CON0, 0x3, 5),
3555
+	.grf_hdmi1_pin_pol = VOP_REG(RK3588_GRF_VO1_CON0, 0x3, 7),
3556
+};
3557
+
3558
+static const struct vop2_ctrl rk3588_vop_ctrl = {
3559
+	.cfg_done_en = VOP_REG(RK3568_REG_CFG_DONE, 0x1, 15),
3560
+	.wb_cfg_done = VOP_REG_MASK(RK3568_REG_CFG_DONE, 0x1, 14),
3561
+	.auto_gating_en = VOP_REG(RK3568_SYS_AUTO_GATING_CTRL, 0x1, 31),
3562
+	.dma_finish_mode = VOP_REG(RK3588_SYS_VAR_FREQ_CTRL, 0x3, 0),
3563
+	.axi_dma_finish_and_en = VOP_REG(RK3588_SYS_VAR_FREQ_CTRL, 0x1, 2),
3564
+	.wb_dma_finish_and_en = VOP_REG(RK3588_SYS_VAR_FREQ_CTRL, 0x1, 3),
3565
+	.ovl_cfg_done_port = VOP_REG(RK3568_OVL_CTRL, 0x3, 30),
3566
+	.ovl_port_mux_cfg_done_imd = VOP_REG(RK3568_OVL_CTRL, 0x1, 28),
3567
+	.ovl_port_mux_cfg = VOP_REG(RK3568_OVL_PORT_SEL, 0xffff, 0),
3568
+	.if_ctrl_cfg_done_imd = VOP_REG(RK3568_DSP_IF_POL, 0x1, 28),
3569
+	.version = VOP_REG(RK3568_VERSION_INFO, 0xffff, 16),
3570
+	.lut_dma_en = VOP_REG(RK3568_SYS_AXI_LUT_CTRL, 0x1, 0),
3571
+	.src_color_ctrl = VOP_REG(RK3568_MIX0_SRC_COLOR_CTRL, 0xffffffff, 0),
3572
+	.dst_color_ctrl = VOP_REG(RK3568_MIX0_DST_COLOR_CTRL, 0xffffffff, 0),
3573
+	.src_alpha_ctrl = VOP_REG(RK3568_MIX0_SRC_ALPHA_CTRL, 0xffffffff, 0),
3574
+	.dst_alpha_ctrl = VOP_REG(RK3568_MIX0_DST_ALPHA_CTRL, 0xffffffff, 0),
3575
+	.dp0_en = VOP_REG(RK3568_DSP_IF_EN, 0x1, 0),
3576
+	.dp1_en = VOP_REG(RK3568_DSP_IF_EN, 0x1, 1),
3577
+	.edp0_en = VOP_REG(RK3568_DSP_IF_EN, 0x1, 2),
3578
+	.hdmi0_en = VOP_REG(RK3568_DSP_IF_EN, 0x1, 3),
3579
+	.edp1_en = VOP_REG(RK3568_DSP_IF_EN, 0x1, 4),
3580
+	.hdmi1_en = VOP_REG(RK3568_DSP_IF_EN, 0x1, 5),
3581
+	.mipi0_en = VOP_REG(RK3568_DSP_IF_EN, 0x1, 6),
3582
+	.mipi1_en = VOP_REG(RK3568_DSP_IF_EN, 0x1, 7),
3583
+	.bt1120_en = VOP_REG(RK3568_DSP_IF_EN, 0x3, 8),
3584
+	.bt656_en = VOP_REG(RK3568_DSP_IF_EN, 0x1, 9),
3585
+	.rgb_en = VOP_REG(RK3568_DSP_IF_EN, 0x1, 10),
3586
+	.dp0_mux = VOP_REG(RK3568_DSP_IF_EN, 0x3, 12),
3587
+	.dp1_mux = VOP_REG(RK3568_DSP_IF_EN, 0x3, 14),
3588
+	.hdmi0_mux = VOP_REG(RK3568_DSP_IF_EN, 0x3, 16),
3589
+	.edp0_mux = VOP_REG(RK3568_DSP_IF_EN, 0x3, 16),
3590
+	.hdmi1_mux = VOP_REG(RK3568_DSP_IF_EN, 0x3, 18),
3591
+	.edp1_mux = VOP_REG(RK3568_DSP_IF_EN, 0x3, 18),
3592
+	.mipi0_mux = VOP_REG(RK3568_DSP_IF_EN, 0x1, 20),
3593
+	.mipi1_mux = VOP_REG(RK3568_DSP_IF_EN, 0x3, 21),
3594
+	.bt656_yc_swap = VOP_REG(RK3568_DSP_IF_CTRL, 0x1, 1),
3595
+	.bt1120_yc_swap = VOP_REG(RK3568_DSP_IF_CTRL, 0x1, 5),
3596
+	.hdmi_dual_en = VOP_REG(RK3568_DSP_IF_CTRL, 0x1, 8),
3597
+	.edp_dual_en = VOP_REG(RK3568_DSP_IF_CTRL, 0x1, 8),
3598
+	.dp_dual_en = VOP_REG(RK3568_DSP_IF_CTRL, 0x1, 9),
3599
+	.mipi_dual_en = VOP_REG(RK3568_DSP_IF_CTRL, 0x1, 10),
3600
+	.mipi0_ds_mode = VOP_REG(RK3568_DSP_IF_CTRL, 0x1, 11),
3601
+	.mipi1_ds_mode = VOP_REG(RK3568_DSP_IF_CTRL, 0x1, 12),
3602
+	.hdmi0_dclk_div = VOP_REG(RK3568_DSP_IF_CTRL, 0x3, 16),
3603
+	.hdmi0_pixclk_div = VOP_REG(RK3568_DSP_IF_CTRL, 0x3, 18),
3604
+	.hdmi1_dclk_div = VOP_REG(RK3568_DSP_IF_CTRL, 0x3, 20),
3605
+	.hdmi1_pixclk_div = VOP_REG(RK3568_DSP_IF_CTRL, 0x3, 22),
3606
+	.edp0_dclk_div = VOP_REG(RK3568_DSP_IF_CTRL, 0x3, 16),
3607
+	.edp0_pixclk_div = VOP_REG(RK3568_DSP_IF_CTRL, 0x3, 18),
3608
+	.edp1_dclk_div = VOP_REG(RK3568_DSP_IF_CTRL, 0x3, 20),
3609
+	.edp1_pixclk_div = VOP_REG(RK3568_DSP_IF_CTRL, 0x3, 22),
3610
+
3611
+	.mipi0_pixclk_div = VOP_REG(RK3568_DSP_IF_CTRL, 0x3, 24),
3612
+	.mipi1_pixclk_div = VOP_REG(RK3568_DSP_IF_CTRL, 0x3, 26),
3613
+	/* HDMI pol control by GRF_VO1_CON0
3614
+	 * DP0/1 clk pol is fixed
3615
+	 * MIPI/eDP pol is fixed
3616
+	 */
3617
+	.rgb_pin_pol = VOP_REG(RK3568_DSP_IF_POL, 0x7, 0),
3618
+	.rgb_dclk_pol = VOP_REG(RK3568_DSP_IF_POL, 0x1, 3),
3619
+	.dp0_pin_pol = VOP_REG(RK3568_DSP_IF_POL, 0x7, 8),
3620
+	.dp1_pin_pol = VOP_REG(RK3568_DSP_IF_POL, 0x7, 12),
3621
+	.gamma_port_sel = VOP_REG(RK3568_LUT_PORT_SEL, 0x3, 12),
3622
+	.pd_off_imd = VOP_REG(RK3568_SYS_PD_CTRL, 0x1, 31),
3623
+	.win_vp_id[ROCKCHIP_VOP2_CLUSTER0] = VOP_REG(RK3568_OVL_PORT_SEL, 0x3, 16),
3624
+	.win_vp_id[ROCKCHIP_VOP2_CLUSTER1] = VOP_REG(RK3568_OVL_PORT_SEL, 0x3, 18),
3625
+	.win_vp_id[ROCKCHIP_VOP2_CLUSTER2] = VOP_REG(RK3568_OVL_PORT_SEL, 0x3, 20),
3626
+	.win_vp_id[ROCKCHIP_VOP2_CLUSTER3] = VOP_REG(RK3568_OVL_PORT_SEL, 0x3, 22),
3627
+	.win_vp_id[ROCKCHIP_VOP2_ESMART0] = VOP_REG(RK3568_OVL_PORT_SEL, 0x3, 24),
3628
+	.win_vp_id[ROCKCHIP_VOP2_ESMART1] = VOP_REG(RK3568_OVL_PORT_SEL, 0x3, 26),
3629
+	.win_vp_id[ROCKCHIP_VOP2_ESMART2] = VOP_REG(RK3568_OVL_PORT_SEL, 0x3, 28),
3630
+	.win_vp_id[ROCKCHIP_VOP2_ESMART3] = VOP_REG(RK3568_OVL_PORT_SEL, 0x3, 30),
3631
+	.win_dly[ROCKCHIP_VOP2_CLUSTER0] = VOP_REG(RK3568_CLUSTER_DLY_NUM, 0xffff, 0),
3632
+	.win_dly[ROCKCHIP_VOP2_CLUSTER1] = VOP_REG(RK3568_CLUSTER_DLY_NUM, 0xffff, 16),
3633
+	.win_dly[ROCKCHIP_VOP2_CLUSTER2] = VOP_REG(RK3568_CLUSTER_DLY_NUM1, 0xffff, 0),
3634
+	.win_dly[ROCKCHIP_VOP2_CLUSTER3] = VOP_REG(RK3568_CLUSTER_DLY_NUM1, 0xffff, 16),
3635
+	.win_dly[ROCKCHIP_VOP2_ESMART0] = VOP_REG(RK3568_SMART_DLY_NUM, 0xff, 0),
3636
+	.win_dly[ROCKCHIP_VOP2_ESMART1] = VOP_REG(RK3568_SMART_DLY_NUM, 0xff, 8),
3637
+	.win_dly[ROCKCHIP_VOP2_ESMART2] = VOP_REG(RK3568_SMART_DLY_NUM, 0xff, 16),
3638
+	.win_dly[ROCKCHIP_VOP2_ESMART3] = VOP_REG(RK3568_SMART_DLY_NUM, 0xff, 24),
18173639 };
18183640 
18193641 static const struct vop_dump_regs rk3528_dump_regs[] = {
....@@ -1828,6 +3650,20 @@
18283650 	{ RK3568_ESMART1_CTRL0, "Esmart1", VOP_REG(RK3568_ESMART1_REGION0_CTRL, 0x1, 0), 1 },
18293651 	{ RK3568_SMART0_CTRL0, "Esmart2", VOP_REG(RK3568_SMART0_CTRL0, 0x1, 0), 1 },
18303652 	{ RK3568_SMART1_CTRL0, "Esmart3", VOP_REG(RK3568_SMART1_CTRL0, 0x1, 0), 1 },
3653
+	{ RK3528_HDR_LUT_CTRL, "HDR", {0}, 0 },
3654
+};
3655
+
3656
+static const struct vop_dump_regs rk3562_dump_regs[] = {
3657
+	{ RK3568_REG_CFG_DONE, "SYS", {0}, 0 },
3658
+	{ RK3528_OVL_SYS, "OVL_SYS", {0}, 0 },
3659
+	{ RK3528_OVL_PORT0_CTRL, "OVL_VP0", VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 31), 0 },
3660
+	{ RK3528_OVL_PORT1_CTRL, "OVL_VP1", VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 31), 0 },
3661
+	{ RK3568_VP0_DSP_CTRL, "VP0", VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 31), 0 },
3662
+	{ RK3568_VP1_DSP_CTRL, "VP1", VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 31), 0 },
3663
+	{ RK3568_ESMART0_CTRL0, "Esmart0", VOP_REG(RK3568_ESMART0_REGION0_CTRL, 0x1, 0), 1 },
3664
+	{ RK3568_ESMART1_CTRL0, "Esmart1", VOP_REG(RK3568_ESMART1_REGION0_CTRL, 0x1, 0), 1 },
3665
+	{ RK3568_SMART0_CTRL0, "Esmart2", VOP_REG(RK3568_SMART0_CTRL0, 0x1, 0), 1 },
3666
+	{ RK3568_SMART1_CTRL0, "Esmart3", VOP_REG(RK3568_SMART1_CTRL0, 0x1, 0), 1 },
18313667 };
18323668 
18333669 static const struct vop_dump_regs rk3568_dump_regs[] = {
....@@ -1836,19 +3672,204 @@
18363672 	{ RK3568_VP0_DSP_CTRL, "VP0", VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 31), 0 },
18373673 	{ RK3568_VP1_DSP_CTRL, "VP1", VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 31), 0 },
18383674 	{ RK3568_VP2_DSP_CTRL, "VP2", VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 31), 0 },
1839
-	{ RK3568_CLUSTER0_WIN0_CTRL0, "Cluster0", VOP_REG(RK3568_CLUSTER0_CTRL, 1, 0), 1 },
1840
-	{ RK3568_CLUSTER1_WIN0_CTRL0, "Cluster1", VOP_REG(RK3568_CLUSTER1_CTRL, 1, 0), 1 },
3675
+	{ RK3568_CLUSTER0_WIN0_CTRL0, "Cluster0", VOP_REG(RK3568_CLUSTER0_WIN0_CTRL0, 0x1, 0), 1 },
3676
+	{ RK3568_CLUSTER1_WIN0_CTRL0, "Cluster1", VOP_REG(RK3568_CLUSTER1_WIN0_CTRL0, 0x1, 0), 1 },
18413677 	{ RK3568_ESMART0_CTRL0, "Esmart0", VOP_REG(RK3568_ESMART0_REGION0_CTRL, 0x1, 0), 1 },
18423678 	{ RK3568_ESMART1_CTRL0, "Esmart1", VOP_REG(RK3568_ESMART1_REGION0_CTRL, 0x1, 0), 1 },
18433679 	{ RK3568_SMART0_CTRL0, "Smart0", VOP_REG(RK3568_SMART0_REGION0_CTRL, 0x1, 0), 1 },
18443680 	{ RK3568_SMART1_CTRL0, "Smart1", VOP_REG(RK3568_SMART1_REGION0_CTRL, 0x1, 0), 1 },
1845
-	{ RK3568_HDR_LUT_CTRL, "HDR", VOP_REG(RK3568_OVL_CTRL, 0x1, 4), 1 },
3681
+	{ RK3568_HDR_LUT_CTRL, "HDR", {0}, 0 },
3682
+};
3683
+
3684
+static const struct vop_dump_regs rk3588_dump_regs[] = {
3685
+	{ RK3568_REG_CFG_DONE, "SYS", {0}, 0 },
3686
+	{ RK3568_OVL_CTRL, "OVL", {0}, 0 },
3687
+	{ RK3568_VP0_DSP_CTRL, "VP0", VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 31), 0 },
3688
+	{ RK3568_VP1_DSP_CTRL, "VP1", VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 31), 0 },
3689
+	{ RK3568_VP2_DSP_CTRL, "VP2", VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 31), 0 },
3690
+	{ RK3588_VP3_DSP_CTRL, "VP3", VOP_REG(RK3588_VP3_DSP_CTRL, 0x1, 31), 0 },
3691
+	{ RK3568_CLUSTER0_WIN0_CTRL0, "Cluster0", VOP_REG(RK3568_CLUSTER0_WIN0_CTRL0, 0x1, 0), 1 },
3692
+	{ RK3568_CLUSTER1_WIN0_CTRL0, "Cluster1", VOP_REG(RK3568_CLUSTER1_WIN0_CTRL0, 0x1, 0), 1 },
3693
+	{ RK3588_CLUSTER2_WIN0_CTRL0, "Cluster2", VOP_REG(RK3588_CLUSTER2_WIN0_CTRL0, 0x1, 0), 1 },
3694
+	{ RK3588_CLUSTER3_WIN0_CTRL0, "Cluster3", VOP_REG(RK3588_CLUSTER3_WIN0_CTRL0, 0x1, 0), 1 },
3695
+	{ RK3568_ESMART0_CTRL0, "Esmart0", VOP_REG(RK3568_ESMART0_REGION0_CTRL, 0x1, 0), 1 },
3696
+	{ RK3568_ESMART1_CTRL0, "Esmart1", VOP_REG(RK3568_ESMART1_REGION0_CTRL, 0x1, 0), 1 },
3697
+	{ RK3568_SMART0_CTRL0, "Esmart2", VOP_REG(RK3568_SMART0_REGION0_CTRL, 0x1, 0), 1 },
3698
+	{ RK3568_SMART1_CTRL0, "Esmart3", VOP_REG(RK3568_SMART1_REGION0_CTRL, 0x1, 0), 1 },
3699
+	{ RK3568_HDR_LUT_CTRL, "HDR", {0}, 0 },
3700
+};
3701
+
3702
+#define RK3568_PLANE_MASK_BASE \
3703
+	(BIT(ROCKCHIP_VOP2_CLUSTER0) | BIT(ROCKCHIP_VOP2_CLUSTER1) | \
3704
+	 BIT(ROCKCHIP_VOP2_ESMART0)  | BIT(ROCKCHIP_VOP2_ESMART1)  | \
3705
+	 BIT(ROCKCHIP_VOP2_SMART0)   | BIT(ROCKCHIP_VOP2_SMART1))
3706
+
3707
+#define RK3588_PLANE_MASK_BASE \
3708
+	(BIT(ROCKCHIP_VOP2_CLUSTER0) | BIT(ROCKCHIP_VOP2_CLUSTER1) | \
3709
+	 BIT(ROCKCHIP_VOP2_CLUSTER2) | BIT(ROCKCHIP_VOP2_CLUSTER3) | \
3710
+	 BIT(ROCKCHIP_VOP2_ESMART0)  | BIT(ROCKCHIP_VOP2_ESMART1)  | \
3711
+	 BIT(ROCKCHIP_VOP2_ESMART2)  | BIT(ROCKCHIP_VOP2_ESMART3))
3712
+
3713
+static struct vop2_vp_plane_mask rk3568_vp_plane_mask[ROCKCHIP_MAX_CRTC][ROCKCHIP_MAX_CRTC] = {
3714
+	{ /* one display policy */
3715
+		{/* main display */
3716
+			.primary_plane_id = ROCKCHIP_VOP2_SMART0,
3717
+			.attached_layers_nr = 6,
3718
+			.attached_layers = {
3719
+				  ROCKCHIP_VOP2_CLUSTER0, ROCKCHIP_VOP2_ESMART0, ROCKCHIP_VOP2_SMART0,
3720
+				  ROCKCHIP_VOP2_CLUSTER1, ROCKCHIP_VOP2_ESMART1, ROCKCHIP_VOP2_SMART1
3721
+				},
3722
+		},
3723
+		{/* second display */},
3724
+		{/* third  display */},
3725
+		{/* fourth display */},
3726
+	},
3727
+
3728
+	{ /* two display policy */
3729
+		{/* main display */
3730
+			.primary_plane_id = ROCKCHIP_VOP2_SMART0,
3731
+			.attached_layers_nr = 3,
3732
+			.attached_layers = {
3733
+				  ROCKCHIP_VOP2_CLUSTER0, ROCKCHIP_VOP2_ESMART0, ROCKCHIP_VOP2_SMART0
3734
+				},
3735
+		},
3736
+
3737
+		{/* second display */
3738
+			.primary_plane_id = ROCKCHIP_VOP2_SMART1,
3739
+			.attached_layers_nr = 3,
3740
+			.attached_layers = {
3741
+				  ROCKCHIP_VOP2_CLUSTER1, ROCKCHIP_VOP2_ESMART1, ROCKCHIP_VOP2_SMART1
3742
+				},
3743
+		},
3744
+		{/* third  display */},
3745
+		{/* fourth display */},
3746
+	},
3747
+
3748
+	{ /* three display policy */
3749
+		{/* main display */
3750
+			.primary_plane_id = ROCKCHIP_VOP2_SMART0,
3751
+			.attached_layers_nr = 3,
3752
+			.attached_layers = {
3753
+				  ROCKCHIP_VOP2_CLUSTER0, ROCKCHIP_VOP2_ESMART0, ROCKCHIP_VOP2_SMART0
3754
+				},
3755
+		},
3756
+
3757
+		{/* second display */
3758
+			.primary_plane_id = ROCKCHIP_VOP2_SMART1,
3759
+			.attached_layers_nr = 2,
3760
+			.attached_layers = {
3761
+				  ROCKCHIP_VOP2_CLUSTER1, ROCKCHIP_VOP2_SMART1
3762
+				},
3763
+		},
3764
+
3765
+		{/* third  display */
3766
+			.primary_plane_id = ROCKCHIP_VOP2_ESMART1,
3767
+			.attached_layers_nr = 1,
3768
+			.attached_layers = { ROCKCHIP_VOP2_ESMART1 },
3769
+		},
3770
+
3771
+		{/* fourth display */},
3772
+	},
3773
+
3774
+	{/* reserved for four display policy */},
3775
+};
3776
+
3777
+static struct vop2_vp_plane_mask rk3588_vp_plane_mask[ROCKCHIP_MAX_CRTC][ROCKCHIP_MAX_CRTC] = {
3778
+	{ /* one display policy */
3779
+		{/* main display */
3780
+			.primary_plane_id = ROCKCHIP_VOP2_ESMART0,
3781
+			.attached_layers_nr = 8,
3782
+			.attached_layers = {
3783
+				  ROCKCHIP_VOP2_CLUSTER0, ROCKCHIP_VOP2_ESMART0, ROCKCHIP_VOP2_ESMART2,
3784
+				  ROCKCHIP_VOP2_CLUSTER1, ROCKCHIP_VOP2_ESMART1, ROCKCHIP_VOP2_ESMART3,
3785
+				  ROCKCHIP_VOP2_CLUSTER2, ROCKCHIP_VOP2_CLUSTER3
3786
+			},
3787
+		},
3788
+		{/* second display */},
3789
+		{/* third  display */},
3790
+		{/* fourth display */},
3791
+	},
3792
+
3793
+	{ /* two display policy */
3794
+		{/* main display */
3795
+			.primary_plane_id = ROCKCHIP_VOP2_ESMART0,
3796
+			.attached_layers_nr = 4,
3797
+			.attached_layers = {
3798
+				  ROCKCHIP_VOP2_CLUSTER0, ROCKCHIP_VOP2_ESMART0,
3799
+				  ROCKCHIP_VOP2_CLUSTER1, ROCKCHIP_VOP2_ESMART1
3800
+			},
3801
+		},
3802
+
3803
+		{/* second display */
3804
+			.primary_plane_id = ROCKCHIP_VOP2_ESMART2,
3805
+			.attached_layers_nr = 4,
3806
+			.attached_layers = {
3807
+				  ROCKCHIP_VOP2_CLUSTER2, ROCKCHIP_VOP2_ESMART2,
3808
+				  ROCKCHIP_VOP2_CLUSTER3, ROCKCHIP_VOP2_ESMART3
3809
+			},
3810
+		},
3811
+		{/* third  display */},
3812
+		{/* fourth display */},
3813
+	},
3814
+
3815
+	{ /* three display policy */
3816
+		{/* main display */
3817
+			.primary_plane_id = ROCKCHIP_VOP2_ESMART0,
3818
+			.attached_layers_nr = 3,
3819
+			.attached_layers = {
3820
+				  ROCKCHIP_VOP2_CLUSTER0, ROCKCHIP_VOP2_CLUSTER1, ROCKCHIP_VOP2_ESMART0
3821
+			},
3822
+		},
3823
+
3824
+		{/* second display */
3825
+			.primary_plane_id = ROCKCHIP_VOP2_ESMART1,
3826
+			.attached_layers_nr = 3,
3827
+			.attached_layers = {
3828
+				  ROCKCHIP_VOP2_CLUSTER2, ROCKCHIP_VOP2_CLUSTER3, ROCKCHIP_VOP2_ESMART1
3829
+			},
3830
+		},
3831
+
3832
+		{/* third  display */
3833
+			.primary_plane_id = ROCKCHIP_VOP2_ESMART2,
3834
+			.attached_layers_nr = 2,
3835
+			.attached_layers = { ROCKCHIP_VOP2_ESMART2, ROCKCHIP_VOP2_ESMART3 },
3836
+		},
3837
+
3838
+		{/* fourth display */},
3839
+	},
3840
+
3841
+	{ /* four display policy */
3842
+		{/* main display */
3843
+			.primary_plane_id = ROCKCHIP_VOP2_ESMART0,
3844
+			.attached_layers_nr = 2,
3845
+			.attached_layers = { ROCKCHIP_VOP2_CLUSTER0, ROCKCHIP_VOP2_ESMART0 },
3846
+		},
3847
+
3848
+		{/* second display */
3849
+			.primary_plane_id = ROCKCHIP_VOP2_ESMART1,
3850
+			.attached_layers_nr = 2,
3851
+			.attached_layers = { ROCKCHIP_VOP2_CLUSTER1, ROCKCHIP_VOP2_ESMART1 },
3852
+		},
3853
+
3854
+		{/* third  display */
3855
+			.primary_plane_id = ROCKCHIP_VOP2_ESMART2,
3856
+			.attached_layers_nr = 2,
3857
+			.attached_layers = { ROCKCHIP_VOP2_CLUSTER2, ROCKCHIP_VOP2_ESMART2 },
3858
+		},
3859
+
3860
+		{/* fourth display */
3861
+			.primary_plane_id = ROCKCHIP_VOP2_ESMART3,
3862
+			.attached_layers_nr = 2,
3863
+			.attached_layers = { ROCKCHIP_VOP2_CLUSTER3, ROCKCHIP_VOP2_ESMART3 },
3864
+		},
3865
+	},
3866
+
18463867 };
18473868 
18483869 static const struct vop2_data rk3528_vop = {
18493870 	.version = VOP_VERSION_RK3528,
18503871 	.nr_vps = 2,
1851
-	.nr_mixers = 3,
3872
+	.nr_mixers = 4,
18523873 	.nr_layers = 4,
18533874 	.nr_gammas = 2,
18543875 	.esmart_lb_mode = VOP3_ESMART_4K_2K_2K_MODE,
....@@ -1865,32 +3886,98 @@
18653886 	.dump_regs_size = ARRAY_SIZE(rk3528_dump_regs),
18663887 };
18673888 
3889
+static const struct vop2_data rk3562_vop = {
3890
+	.version = VOP_VERSION_RK3562,
3891
+	.nr_vps = ARRAY_SIZE(rk3562_vop_video_ports),
3892
+	.nr_mixers = 3,
3893
+	.nr_layers = 4,
3894
+	.nr_gammas = 2,
3895
+	.esmart_lb_mode = VOP3_ESMART_2K_2K_2K_2K_MODE,
3896
+	.max_input = { 4096, 4096 },
3897
+	.max_output = { 4096, 4096 },
3898
+	.ctrl = &rk3562_vop_ctrl,
3899
+	.sys_grf = &rk3562_sys_grf_ctrl,
3900
+	.axi_intr = rk3528_vop_axi_intr,
3901
+	.nr_axi_intr = ARRAY_SIZE(rk3528_vop_axi_intr),
3902
+	.vp = rk3562_vop_video_ports,
3903
+	.wb = &rk3568_vop_wb_data,
3904
+	.win = rk3562_vop_win_data,
3905
+	.win_size = ARRAY_SIZE(rk3562_vop_win_data),
3906
+	.dump_regs = rk3562_dump_regs,
3907
+	.dump_regs_size = ARRAY_SIZE(rk3562_dump_regs),
3908
+};
3909
+
18683910 static const struct vop2_data rk3568_vop = {
1869
-	.version = VOP_VERSION(0x40, 0x15),
3911
+	.version = VOP_VERSION_RK3568,
18703912 	.nr_vps = 3,
18713913 	.nr_mixers = 5,
3914
+	.nr_layers = 6,
18723915 	.nr_gammas = 1,
1873
-	.max_input = { 4096, 2304 },
1874
-	.max_output = { 4096, 2304 },
3916
+	.max_input = { 4096, 4096 },
3917
+	.max_output = { 4096, 4096 },
18753918 	.ctrl = &rk3568_vop_ctrl,
1876
-	.grf_ctrl = &rk3568_grf_ctrl,
3919
+	.sys_grf = &rk3568_sys_grf_ctrl,
18773920 	.axi_intr = rk3568_vop_axi_intr,
18783921 	.nr_axi_intr = ARRAY_SIZE(rk3568_vop_axi_intr),
18793922 	.vp = rk3568_vop_video_ports,
18803923 	.wb = &rk3568_vop_wb_data,
18813924 	.layer = rk3568_vop_layers,
1882
-	.nr_layers = ARRAY_SIZE(rk3568_vop_layers),
18833925 	.win = rk3568_vop_win_data,
18843926 	.win_size = ARRAY_SIZE(rk3568_vop_win_data),
18853927 	.dump_regs = rk3568_dump_regs,
18863928 	.dump_regs_size = ARRAY_SIZE(rk3568_dump_regs),
3929
+	.plane_mask = rk3568_vp_plane_mask[0],
3930
+	.plane_mask_base = RK3568_PLANE_MASK_BASE,
3931
+};
3932
+
3933
+static const struct vop2_data rk3588_vop = {
3934
+	.version = VOP_VERSION_RK3588,
3935
+	.feature = VOP_FEATURE_SPLICE,
3936
+	.nr_dscs = 2,
3937
+	.nr_dsc_ecw = ARRAY_SIZE(dsc_ecw),
3938
+	.nr_dsc_buffer_flow = ARRAY_SIZE(dsc_buffer_flow),
3939
+	.nr_vps = 4,
3940
+	.nr_mixers = 7,
3941
+	.nr_layers = 8,
3942
+	.nr_gammas = 4,
3943
+	.max_input = { 4096, 4320 },
3944
+	.max_output = { 4096, 4320 },
3945
+	.ctrl = &rk3588_vop_ctrl,
3946
+	.grf = &rk3588_vop_grf_ctrl,
3947
+	.sys_grf = &rk3588_sys_grf_ctrl,
3948
+	.vo1_grf = &rk3588_vo1_grf_ctrl,
3949
+	.axi_intr = rk3568_vop_axi_intr,
3950
+	.nr_axi_intr = ARRAY_SIZE(rk3568_vop_axi_intr),
3951
+	.dsc = rk3588_vop_dsc_data,
3952
+	.dsc_error_ecw = dsc_ecw,
3953
+	.dsc_error_buffer_flow = dsc_buffer_flow,
3954
+	.vp = rk3588_vop_video_ports,
3955
+	.conn = rk3588_conn_if_data,
3956
+	.nr_conns = ARRAY_SIZE(rk3588_conn_if_data),
3957
+	.wb = &rk3568_vop_wb_data,
3958
+	.layer = rk3568_vop_layers,
3959
+	.win = rk3588_vop_win_data,
3960
+	.win_size = ARRAY_SIZE(rk3588_vop_win_data),
3961
+	.pd = rk3588_vop_pd_data,
3962
+	.nr_pds = ARRAY_SIZE(rk3588_vop_pd_data),
3963
+	.mem_pg = rk3588_vop_mem_pg_data,
3964
+	.nr_mem_pgs = ARRAY_SIZE(rk3588_vop_mem_pg_data),
3965
+	.dump_regs = rk3588_dump_regs,
3966
+	.dump_regs_size = ARRAY_SIZE(rk3588_dump_regs),
3967
+	.plane_mask = rk3588_vp_plane_mask[0],
3968
+	.plane_mask_base = RK3588_PLANE_MASK_BASE,
18873969 };
18883970 
18893971 static const struct of_device_id vop2_dt_match[] = {
18903972 	{ .compatible = "rockchip,rk3528-vop",
18913973 	  .data = &rk3528_vop },
3974
+	{ .compatible = "rockchip,rk3562-vop",
3975
+	  .data = &rk3562_vop },
18923976 	{ .compatible = "rockchip,rk3568-vop",
18933977 	  .data = &rk3568_vop },
3978
+	{ .compatible = "rockchip,rk3588-vop",
3979
+	  .data = &rk3588_vop },
3980
+
18943981 	{},
18953982 };
18963983 MODULE_DEVICE_TABLE(of, vop2_dt_match);