default settings GPIO PA4 PA6 PA3 PB5

hc

2024-02-19 890e1df1bec891d9203724541e81f8fbe5183388

 kernel/drivers/gpu/drm/rcar-du/rcar_lvds_regs.h
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@@ -1,13 +1,10 @@
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+/* SPDX-License-Identifier: GPL-2.0 */
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 /*
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  * rcar_lvds_regs.h  --  R-Car LVDS Interface Registers Definitions
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  *
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  * Copyright (C) 2013-2015 Renesas Electronics Corporation
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  *
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  * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2
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- * as published by the Free Software Foundation.
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  */
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 #ifndef __RCAR_LVDS_REGS_H__
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@@ -21,7 +18,7 @@
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 #define LVDCR0_PLLON			(1 << 4)
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 #define LVDCR0_PWD			(1 << 2)		/* Gen3 only */
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 #define LVDCR0_BEN			(1 << 2)		/* Gen2 only */
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-#define LVDCR0_LVEN			(1 << 1)		/* Gen2 only */
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+#define LVDCR0_LVEN			(1 << 1)
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 #define LVDCR0_LVRES			(1 << 0)
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 #define LVDCR1				0x0004
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@@ -30,21 +27,36 @@
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 #define LVDCR1_CLKSTBY			(3 << 0)
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 #define LVDPLLCR			0x0008
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+/* Gen2 & V3M */
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 #define LVDPLLCR_CEEN			(1 << 14)
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 #define LVDPLLCR_FBEN			(1 << 13)
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 #define LVDPLLCR_COSEL			(1 << 12)
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-/* Gen2 */
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 #define LVDPLLCR_PLLDLYCNT_150M		(0x1bf << 0)
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 #define LVDPLLCR_PLLDLYCNT_121M		(0x22c << 0)
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 #define LVDPLLCR_PLLDLYCNT_60M		(0x77b << 0)
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 #define LVDPLLCR_PLLDLYCNT_38M		(0x69a << 0)
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 #define LVDPLLCR_PLLDLYCNT_MASK		(0x7ff << 0)
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-/* Gen3 */
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+/* Gen3 but V3M,D3 and E3 */
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 #define LVDPLLCR_PLLDIVCNT_42M		(0x014cb << 0)
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 #define LVDPLLCR_PLLDIVCNT_85M		(0x00a45 << 0)
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 #define LVDPLLCR_PLLDIVCNT_128M		(0x006c3 << 0)
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 #define LVDPLLCR_PLLDIVCNT_148M		(0x046c1 << 0)
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 #define LVDPLLCR_PLLDIVCNT_MASK		(0x7ffff << 0)
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+/* D3 and E3 */
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+#define LVDPLLCR_PLLON			(1 << 22)
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+#define LVDPLLCR_PLLSEL_PLL0		(0 << 20)
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+#define LVDPLLCR_PLLSEL_LVX		(1 << 20)
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+#define LVDPLLCR_PLLSEL_PLL1		(2 << 20)
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+#define LVDPLLCR_CKSEL_LVX		(1 << 17)
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+#define LVDPLLCR_CKSEL_EXTAL		(3 << 17)
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+#define LVDPLLCR_CKSEL_DU_DOTCLKIN(n)	((5 + (n) * 2) << 17)
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+#define LVDPLLCR_OCKSEL			(1 << 16)
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+#define LVDPLLCR_STP_CLKOUTE		(1 << 14)
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+#define LVDPLLCR_OUTCLKSEL		(1 << 12)
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+#define LVDPLLCR_CLKOUT			(1 << 11)
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+#define LVDPLLCR_PLLE(n)		((n) << 10)
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+#define LVDPLLCR_PLLN(n)		((n) << 3)
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+#define LVDPLLCR_PLLM(n)		((n) << 0)
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 #define LVDCTRCR			0x000c
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 #define LVDCTRCR_CTR3SEL_ZERO		(0 << 12)
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@@ -74,4 +86,26 @@
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 #define LVDCHCR_CHSEL_CH(n, c)		((((c) - (n)) & 3) << ((n) * 4))
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 #define LVDCHCR_CHSEL_MASK(n)		(3 << ((n) * 4))
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+/* All registers below are specific to D3 and E3 */
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+#define LVDSTRIPE			0x0014
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+#define LVDSTRIPE_ST_TRGSEL_DISP	(0 << 2)
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+#define LVDSTRIPE_ST_TRGSEL_HSYNC_R	(1 << 2)
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+#define LVDSTRIPE_ST_TRGSEL_HSYNC_F	(2 << 2)
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+#define LVDSTRIPE_ST_SWAP		(1 << 1)
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+#define LVDSTRIPE_ST_ON			(1 << 0)
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+
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+#define LVDSCR				0x0018
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+#define LVDSCR_DEPTH(n)			(((n) - 1) << 29)
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+#define LVDSCR_BANDSET			(1 << 28)
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+#define LVDSCR_TWGCNT(n)		((((n) - 256) / 16) << 24)
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+#define LVDSCR_SDIV(n)			((n) << 22)
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+#define LVDSCR_MODE			(1 << 21)
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+#define LVDSCR_RSTN			(1 << 20)
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+
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+#define LVDDIV				0x001c
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+#define LVDDIV_DIVSEL			(1 << 8)
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+#define LVDDIV_DIVRESET			(1 << 7)
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+#define LVDDIV_DIVSTP			(1 << 6)
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+#define LVDDIV_DIV(n)			((n) << 0)
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+
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 #endif /* __RCAR_LVDS_REGS_H__ */