~hc/RK356X_SDK_RELEASE.git

..	..	@@ -26,23 +26,36 @@
26	26	#include "core.h"
27	27	#include "head.h"
28	28	#include "wndw.h"
	29	+#include "handles.h"
29	30
30	31	#include <linux/dma-mapping.h>
31	32	#include <linux/hdmi.h>
	33	+#include <linux/component.h>
32	34
33		-#include <drm/drmP.h>
34	35	#include <drm/drm_atomic_helper.h>
35		-#include <drm/drm_crtc_helper.h>
36	36	#include <drm/drm_dp_helper.h>
	37	+#include <drm/drm_edid.h>
37	38	#include <drm/drm_fb_helper.h>
38	39	#include <drm/drm_plane_helper.h>
39		-#include <drm/drm_edid.h>
	40	+#include <drm/drm_probe_helper.h>
	41	+#include <drm/drm_scdc_helper.h>
	42	+#include <drm/drm_vblank.h>
	43	+
	44	+#include <nvif/push507c.h>
40	45
41	46	#include <nvif/class.h>
42	47	#include <nvif/cl0002.h>
43	48	#include <nvif/cl5070.h>
44	49	#include <nvif/cl507d.h>
45	50	#include <nvif/event.h>
	51	+#include <nvif/timer.h>
	52	+
	53	+#include <nvhw/class/cl507c.h>
	54	+#include <nvhw/class/cl507d.h>
	55	+#include <nvhw/class/cl837d.h>
	56	+#include <nvhw/class/cl887d.h>
	57	+#include <nvhw/class/cl907d.h>
	58	+#include <nvhw/class/cl917d.h>
46	59
47	60	#include "nouveau_drv.h"
48	61	#include "nouveau_dma.h"
..	..	@@ -53,24 +66,6 @@
53	66	#include "nouveau_fbcon.h"
54	67
55	68	#include <subdev/bios/dp.h>
56		-
57		-/******************************************************************************
58		- * Atomic state
59		- *****************************************************************************/
60		-
61		-struct nv50_outp_atom {
62		- struct list_head head;
63		-
64		- struct drm_encoder *encoder;
65		- bool flush_disable;
66		-
67		- union nv50_outp_atom_mask {
68		- struct {
69		- bool ctrl:1;
70		- };
71		- u8 mask;
72		- } set, clr;
73		-};
74	69
75	70	/******************************************************************************
76	71	* EVO channel
..	..	@@ -93,8 +88,9 @@
93	88	while (oclass[0]) {
94	89	for (i = 0; i < n; i++) {
95	90	if (sclass[i].oclass == oclass[0]) {
96		- ret = nvif_object_init(disp, 0, oclass[0],
97		- data, size, &chan->user);
	91	+ ret = nvif_object_ctor(disp, "kmsChan", 0,
	92	+ oclass[0], data, size,
	93	+ &chan->user);
98	94	if (ret == 0)
99	95	nvif_object_map(&chan->user, NULL, 0);
100	96	nvif_object_sclass_put(&sclass);
..	..	@@ -111,7 +107,7 @@
111	107	static void
112	108	nv50_chan_destroy(struct nv50_chan *chan)
113	109	{
114		- nvif_object_fini(&chan->user);
	110	+ nvif_object_dtor(&chan->user);
115	111	}
116	112
117	113	/******************************************************************************
..	..	@@ -121,12 +117,106 @@
121	117	void
122	118	nv50_dmac_destroy(struct nv50_dmac *dmac)
123	119	{
124		- nvif_object_fini(&dmac->vram);
125		- nvif_object_fini(&dmac->sync);
	120	+ nvif_object_dtor(&dmac->vram);
	121	+ nvif_object_dtor(&dmac->sync);
126	122
127	123	nv50_chan_destroy(&dmac->base);
128	124
129		- nvif_mem_fini(&dmac->push);
	125	+ nvif_mem_dtor(&dmac->_push.mem);
	126	+}
	127	+
	128	+static void
	129	+nv50_dmac_kick(struct nvif_push *push)
	130	+{
	131	+ struct nv50_dmac dmac = container_of(push, typeof(dmac), _push);
	132	+
	133	+ dmac->cur = push->cur - (u32 *)dmac->_push.mem.object.map.ptr;
	134	+ if (dmac->put != dmac->cur) {
	135	+ /* Push buffer fetches are not coherent with BAR1, we need to ensure
	136	+ * writes have been flushed right through to VRAM before writing PUT.
	137	+ */
	138	+ if (dmac->push->mem.type & NVIF_MEM_VRAM) {
	139	+ struct nvif_device *device = dmac->base.device;
	140	+ nvif_wr32(&device->object, 0x070000, 0x00000001);
	141	+ nvif_msec(device, 2000,
	142	+ if (!(nvif_rd32(&device->object, 0x070000) & 0x00000002))
	143	+ break;
	144	+ );
	145	+ }
	146	+
	147	+ NVIF_WV32(&dmac->base.user, NV507C, PUT, PTR, dmac->cur);
	148	+ dmac->put = dmac->cur;
	149	+ }
	150	+
	151	+ push->bgn = push->cur;
	152	+}
	153	+
	154	+static int
	155	+nv50_dmac_free(struct nv50_dmac *dmac)
	156	+{
	157	+ u32 get = NVIF_RV32(&dmac->base.user, NV507C, GET, PTR);
	158	+ if (get > dmac->cur) /* NVIDIA stay 5 away from GET, do the same. */
	159	+ return get - dmac->cur - 5;
	160	+ return dmac->max - dmac->cur;
	161	+}
	162	+
	163	+static int
	164	+nv50_dmac_wind(struct nv50_dmac *dmac)
	165	+{
	166	+ /* Wait for GET to depart from the beginning of the push buffer to
	167	+ * prevent writing PUT == GET, which would be ignored by HW.
	168	+ */
	169	+ u32 get = NVIF_RV32(&dmac->base.user, NV507C, GET, PTR);
	170	+ if (get == 0) {
	171	+ /* Corner-case, HW idle, but non-committed work pending. */
	172	+ if (dmac->put == 0)
	173	+ nv50_dmac_kick(dmac->push);
	174	+
	175	+ if (nvif_msec(dmac->base.device, 2000,
	176	+ if (NVIF_TV32(&dmac->base.user, NV507C, GET, PTR, >, 0))
	177	+ break;
	178	+ ) < 0)
	179	+ return -ETIMEDOUT;
	180	+ }
	181	+
	182	+ PUSH_RSVD(dmac->push, PUSH_JUMP(dmac->push, 0));
	183	+ dmac->cur = 0;
	184	+ return 0;
	185	+}
	186	+
	187	+static int
	188	+nv50_dmac_wait(struct nvif_push *push, u32 size)
	189	+{
	190	+ struct nv50_dmac dmac = container_of(push, typeof(dmac), _push);
	191	+ int free;
	192	+
	193	+ if (WARN_ON(size > dmac->max))
	194	+ return -EINVAL;
	195	+
	196	+ dmac->cur = push->cur - (u32 *)dmac->_push.mem.object.map.ptr;
	197	+ if (dmac->cur + size >= dmac->max) {
	198	+ int ret = nv50_dmac_wind(dmac);
	199	+ if (ret)
	200	+ return ret;
	201	+
	202	+ push->cur = dmac->_push.mem.object.map.ptr;
	203	+ push->cur = push->cur + dmac->cur;
	204	+ nv50_dmac_kick(push);
	205	+ }
	206	+
	207	+ if (nvif_msec(dmac->base.device, 2000,
	208	+ if ((free = nv50_dmac_free(dmac)) >= size)
	209	+ break;
	210	+ ) < 0) {
	211	+ WARN_ON(1);
	212	+ return -ETIMEDOUT;
	213	+ }
	214	+
	215	+ push->bgn = dmac->_push.mem.object.map.ptr;
	216	+ push->bgn = push->bgn + dmac->cur;
	217	+ push->cur = push->bgn;
	218	+ push->end = push->cur + free;
	219	+ return 0;
130	220	}
131	221
132	222	int
..	..	@@ -153,13 +243,27 @@
153	243	if (device->info.family == NV_DEVICE_INFO_V0_PASCAL)
154	244	type \|= NVIF_MEM_VRAM;
155	245
156		- ret = nvif_mem_init_map(&cli->mmu, type, 0x1000, &dmac->push);
	246	+ ret = nvif_mem_ctor_map(&cli->mmu, "kmsChanPush", type, 0x1000,
	247	+ &dmac->_push.mem);
157	248	if (ret)
158	249	return ret;
159	250
160		- dmac->ptr = dmac->push.object.map.ptr;
	251	+ dmac->ptr = dmac->_push.mem.object.map.ptr;
	252	+ dmac->_push.wait = nv50_dmac_wait;
	253	+ dmac->_push.kick = nv50_dmac_kick;
	254	+ dmac->push = &dmac->_push;
	255	+ dmac->push->bgn = dmac->_push.mem.object.map.ptr;
	256	+ dmac->push->cur = dmac->push->bgn;
	257	+ dmac->push->end = dmac->push->bgn;
	258	+ dmac->max = 0x1000/4 - 1;
161	259
162		- args->pushbuf = nvif_handle(&dmac->push.object);
	260	+ /* EVO channels are affected by a HW bug where the last 12 DWORDs
	261	+ * of the push buffer aren't able to be used safely.
	262	+ */
	263	+ if (disp->oclass < GV100_DISP)
	264	+ dmac->max -= 12;
	265	+
	266	+ args->pushbuf = nvif_handle(&dmac->_push.mem.object);
163	267
164	268	ret = nv50_chan_create(device, disp, oclass, head, data, size,
165	269	&dmac->base);
..	..	@@ -169,7 +273,8 @@
169	273	if (syncbuf < 0)
170	274	return 0;
171	275
172		- ret = nvif_object_init(&dmac->base.user, 0xf0000000, NV_DMA_IN_MEMORY,
	276	+ ret = nvif_object_ctor(&dmac->base.user, "kmsSyncCtxDma", NV50_DISP_HANDLE_SYNCBUF,
	277	+ NV_DMA_IN_MEMORY,
173	278	&(struct nv_dma_v0) {
174	279	.target = NV_DMA_V0_TARGET_VRAM,
175	280	.access = NV_DMA_V0_ACCESS_RDWR,
..	..	@@ -180,7 +285,8 @@
180	285	if (ret)
181	286	return ret;
182	287
183		- ret = nvif_object_init(&dmac->base.user, 0xf0000001, NV_DMA_IN_MEMORY,
	288	+ ret = nvif_object_ctor(&dmac->base.user, "kmsVramCtxDma", NV50_DISP_HANDLE_VRAM,
	289	+ NV_DMA_IN_MEMORY,
184	290	&(struct nv_dma_v0) {
185	291	.target = NV_DMA_V0_TARGET_VRAM,
186	292	.access = NV_DMA_V0_ACCESS_RDWR,
..	..	@@ -192,64 +298,6 @@
192	298	return ret;
193	299
194	300	return ret;
195		-}
196		-
197		-/******************************************************************************
198		- * EVO channel helpers
199		- *****************************************************************************/
200		-static void
201		-evo_flush(struct nv50_dmac *dmac)
202		-{
203		- /* Push buffer fetches are not coherent with BAR1, we need to ensure
204		- * writes have been flushed right through to VRAM before writing PUT.
205		- */
206		- if (dmac->push.type & NVIF_MEM_VRAM) {
207		- struct nvif_device *device = dmac->base.device;
208		- nvif_wr32(&device->object, 0x070000, 0x00000001);
209		- nvif_msec(device, 2000,
210		- if (!(nvif_rd32(&device->object, 0x070000) & 0x00000002))
211		- break;
212		- );
213		- }
214		-}
215		-
216		-u32 *
217		-evo_wait(struct nv50_dmac *evoc, int nr)
218		-{
219		- struct nv50_dmac *dmac = evoc;
220		- struct nvif_device *device = dmac->base.device;
221		- u32 put = nvif_rd32(&dmac->base.user, 0x0000) / 4;
222		-
223		- mutex_lock(&dmac->lock);
224		- if (put + nr >= (PAGE_SIZE / 4) - 8) {
225		- dmac->ptr[put] = 0x20000000;
226		- evo_flush(dmac);
227		-
228		- nvif_wr32(&dmac->base.user, 0x0000, 0x00000000);
229		- if (nvif_msec(device, 2000,
230		- if (!nvif_rd32(&dmac->base.user, 0x0004))
231		- break;
232		- ) < 0) {
233		- mutex_unlock(&dmac->lock);
234		- pr_err("nouveau: evo channel stalled\n");
235		- return NULL;
236		- }
237		-
238		- put = 0;
239		- }
240		-
241		- return dmac->ptr + put;
242		-}
243		-
244		-void
245		-evo_kick(u32 push, struct nv50_dmac evoc)
246		-{
247		- struct nv50_dmac *dmac = evoc;
248		-
249		- evo_flush(dmac);
250		-
251		- nvif_wr32(&dmac->base.user, 0x0000, (push - dmac->ptr) << 2);
252		- mutex_unlock(&dmac->lock);
253	301	}
254	302
255	303	/******************************************************************************
..	..	@@ -274,7 +322,7 @@
274	322	}
275	323
276	324	static int
277		-nv50_outp_acquire(struct nouveau_encoder *nv_encoder)
	325	+nv50_outp_acquire(struct nouveau_encoder *nv_encoder, bool hda)
278	326	{
279	327	struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev);
280	328	struct nv50_disp *disp = nv50_disp(drm->dev);
..	..	@@ -286,6 +334,7 @@
286	334	.base.method = NV50_DISP_MTHD_V1_ACQUIRE,
287	335	.base.hasht = nv_encoder->dcb->hasht,
288	336	.base.hashm = nv_encoder->dcb->hashm,
	337	+ .info.hda = hda,
289	338	};
290	339	int ret;
291	340
..	..	@@ -321,8 +370,13 @@
321	370	switch (connector->connector_type) {
322	371	case DRM_MODE_CONNECTOR_LVDS:
323	372	case DRM_MODE_CONNECTOR_eDP:
324		- /* Force use of scaler for non-EDID modes. */
325		- if (adjusted_mode->type & DRM_MODE_TYPE_DRIVER)
	373	+ /* Don't force scaler for EDID modes with
	374	+ * same size as the native one (e.g. different
	375	+ * refresh rate)
	376	+ */
	377	+ if (mode->hdisplay == native_mode->hdisplay &&
	378	+ mode->vdisplay == native_mode->vdisplay &&
	379	+ mode->type & DRM_MODE_TYPE_DRIVER)
326	380	break;
327	381	mode = native_mode;
328	382	asyc->scaler.full = true;
..	..	@@ -342,42 +396,132 @@
342	396	return 0;
343	397	}
344	398
	399	+static void
	400	+nv50_outp_atomic_fix_depth(struct drm_encoder encoder, struct drm_crtc_state crtc_state)
	401	+{
	402	+ struct nv50_head_atom *asyh = nv50_head_atom(crtc_state);
	403	+ struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
	404	+ struct drm_display_mode *mode = &asyh->state.adjusted_mode;
	405	+ unsigned int max_rate, mode_rate;
	406	+
	407	+ switch (nv_encoder->dcb->type) {
	408	+ case DCB_OUTPUT_DP:
	409	+ max_rate = nv_encoder->dp.link_nr * nv_encoder->dp.link_bw;
	410	+
	411	+ /* we don't support more than 10 anyway */
	412	+ asyh->or.bpc = min_t(u8, asyh->or.bpc, 10);
	413	+
	414	+ /* reduce the bpc until it works out */
	415	+ while (asyh->or.bpc > 6) {
	416	+ mode_rate = DIV_ROUND_UP(mode->clock * asyh->or.bpc * 3, 8);
	417	+ if (mode_rate <= max_rate)
	418	+ break;
	419	+
	420	+ asyh->or.bpc -= 2;
	421	+ }
	422	+ break;
	423	+ default:
	424	+ break;
	425	+ }
	426	+}
	427	+
345	428	static int
346	429	nv50_outp_atomic_check(struct drm_encoder *encoder,
347	430	struct drm_crtc_state *crtc_state,
348	431	struct drm_connector_state *conn_state)
349	432	{
350		- struct nouveau_connector *nv_connector =
351		- nouveau_connector(conn_state->connector);
352		- return nv50_outp_atomic_check_view(encoder, crtc_state, conn_state,
353		- nv_connector->native_mode);
	433	+ struct drm_connector *connector = conn_state->connector;
	434	+ struct nouveau_connector *nv_connector = nouveau_connector(connector);
	435	+ struct nv50_head_atom *asyh = nv50_head_atom(crtc_state);
	436	+ int ret;
	437	+
	438	+ ret = nv50_outp_atomic_check_view(encoder, crtc_state, conn_state,
	439	+ nv_connector->native_mode);
	440	+ if (ret)
	441	+ return ret;
	442	+
	443	+ if (crtc_state->mode_changed \|\| crtc_state->connectors_changed)
	444	+ asyh->or.bpc = connector->display_info.bpc;
	445	+
	446	+ /* We might have to reduce the bpc */
	447	+ nv50_outp_atomic_fix_depth(encoder, crtc_state);
	448	+
	449	+ return 0;
	450	+}
	451	+
	452	+struct nouveau_connector *
	453	+nv50_outp_get_new_connector(struct nouveau_encoder *outp,
	454	+ struct drm_atomic_state *state)
	455	+{
	456	+ struct drm_connector *connector;
	457	+ struct drm_connector_state *connector_state;
	458	+ struct drm_encoder *encoder = to_drm_encoder(outp);
	459	+ int i;
	460	+
	461	+ for_each_new_connector_in_state(state, connector, connector_state, i) {
	462	+ if (connector_state->best_encoder == encoder)
	463	+ return nouveau_connector(connector);
	464	+ }
	465	+
	466	+ return NULL;
	467	+}
	468	+
	469	+struct nouveau_connector *
	470	+nv50_outp_get_old_connector(struct nouveau_encoder *outp,
	471	+ struct drm_atomic_state *state)
	472	+{
	473	+ struct drm_connector *connector;
	474	+ struct drm_connector_state *connector_state;
	475	+ struct drm_encoder *encoder = to_drm_encoder(outp);
	476	+ int i;
	477	+
	478	+ for_each_old_connector_in_state(state, connector, connector_state, i) {
	479	+ if (connector_state->best_encoder == encoder)
	480	+ return nouveau_connector(connector);
	481	+ }
	482	+
	483	+ return NULL;
354	484	}
355	485
356	486	/******************************************************************************
357	487	* DAC
358	488	*****************************************************************************/
359	489	static void
360		-nv50_dac_disable(struct drm_encoder *encoder)
	490	+nv50_dac_disable(struct drm_encoder encoder, struct drm_atomic_state state)
361	491	{
362	492	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
363	493	struct nv50_core *core = nv50_disp(encoder->dev)->core;
	494	+ const u32 ctrl = NVDEF(NV507D, DAC_SET_CONTROL, OWNER, NONE);
364	495	if (nv_encoder->crtc)
365		- core->func->dac->ctrl(core, nv_encoder->or, 0x00000000, NULL);
	496	+ core->func->dac->ctrl(core, nv_encoder->or, ctrl, NULL);
366	497	nv_encoder->crtc = NULL;
367	498	nv50_outp_release(nv_encoder);
368	499	}
369	500
370	501	static void
371		-nv50_dac_enable(struct drm_encoder *encoder)
	502	+nv50_dac_enable(struct drm_encoder encoder, struct drm_atomic_state state)
372	503	{
373	504	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
374	505	struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
375	506	struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state);
376	507	struct nv50_core *core = nv50_disp(encoder->dev)->core;
	508	+ u32 ctrl = 0;
377	509
378		- nv50_outp_acquire(nv_encoder);
	510	+ switch (nv_crtc->index) {
	511	+ case 0: ctrl \|= NVDEF(NV507D, DAC_SET_CONTROL, OWNER, HEAD0); break;
	512	+ case 1: ctrl \|= NVDEF(NV507D, DAC_SET_CONTROL, OWNER, HEAD1); break;
	513	+ case 2: ctrl \|= NVDEF(NV907D, DAC_SET_CONTROL, OWNER_MASK, HEAD2); break;
	514	+ case 3: ctrl \|= NVDEF(NV907D, DAC_SET_CONTROL, OWNER_MASK, HEAD3); break;
	515	+ default:
	516	+ WARN_ON(1);
	517	+ break;
	518	+ }
379	519
380		- core->func->dac->ctrl(core, nv_encoder->or, 1 << nv_crtc->index, asyh);
	520	+ ctrl \|= NVDEF(NV507D, DAC_SET_CONTROL, PROTOCOL, RGB_CRT);
	521	+
	522	+ nv50_outp_acquire(nv_encoder, false);
	523	+
	524	+ core->func->dac->ctrl(core, nv_encoder->or, ctrl, asyh);
381	525	asyh->or.depth = 0;
382	526
383	527	nv_encoder->crtc = encoder->crtc;
..	..	@@ -413,8 +557,8 @@
413	557	static const struct drm_encoder_helper_funcs
414	558	nv50_dac_help = {
415	559	.atomic_check = nv50_outp_atomic_check,
416		- .enable = nv50_dac_enable,
417		- .disable = nv50_dac_disable,
	560	+ .atomic_enable = nv50_dac_enable,
	561	+ .atomic_disable = nv50_dac_disable,
418	562	.detect = nv50_dac_detect
419	563	};
420	564
..	..	@@ -460,12 +604,131 @@
460	604	return 0;
461	605	}
462	606
	607	+/*
	608	+ * audio component binding for ELD notification
	609	+ */
	610	+static void
	611	+nv50_audio_component_eld_notify(struct drm_audio_component *acomp, int port,
	612	+ int dev_id)
	613	+{
	614	+ if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify)
	615	+ acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr,
	616	+ port, dev_id);
	617	+}
	618	+
	619	+static int
	620	+nv50_audio_component_get_eld(struct device *kdev, int port, int dev_id,
	621	+ bool enabled, unsigned char buf, int max_bytes)
	622	+{
	623	+ struct drm_device *drm_dev = dev_get_drvdata(kdev);
	624	+ struct nouveau_drm *drm = nouveau_drm(drm_dev);
	625	+ struct drm_encoder *encoder;
	626	+ struct nouveau_encoder *nv_encoder;
	627	+ struct drm_connector *connector;
	628	+ struct nouveau_crtc *nv_crtc;
	629	+ struct drm_connector_list_iter conn_iter;
	630	+ int ret = 0;
	631	+
	632	+ *enabled = false;
	633	+
	634	+ drm_for_each_encoder(encoder, drm->dev) {
	635	+ struct nouveau_connector *nv_connector = NULL;
	636	+
	637	+ nv_encoder = nouveau_encoder(encoder);
	638	+
	639	+ drm_connector_list_iter_begin(drm_dev, &conn_iter);
	640	+ drm_for_each_connector_iter(connector, &conn_iter) {
	641	+ if (connector->state->best_encoder == encoder) {
	642	+ nv_connector = nouveau_connector(connector);
	643	+ break;
	644	+ }
	645	+ }
	646	+ drm_connector_list_iter_end(&conn_iter);
	647	+ if (!nv_connector)
	648	+ continue;
	649	+
	650	+ nv_crtc = nouveau_crtc(encoder->crtc);
	651	+ if (!nv_crtc \|\| nv_encoder->or != port \|\|
	652	+ nv_crtc->index != dev_id)
	653	+ continue;
	654	+ *enabled = nv_encoder->audio;
	655	+ if (*enabled) {
	656	+ ret = drm_eld_size(nv_connector->base.eld);
	657	+ memcpy(buf, nv_connector->base.eld,
	658	+ min(max_bytes, ret));
	659	+ }
	660	+ break;
	661	+ }
	662	+
	663	+ return ret;
	664	+}
	665	+
	666	+static const struct drm_audio_component_ops nv50_audio_component_ops = {
	667	+ .get_eld = nv50_audio_component_get_eld,
	668	+};
	669	+
	670	+static int
	671	+nv50_audio_component_bind(struct device kdev, struct device hda_kdev,
	672	+ void *data)
	673	+{
	674	+ struct drm_device *drm_dev = dev_get_drvdata(kdev);
	675	+ struct nouveau_drm *drm = nouveau_drm(drm_dev);
	676	+ struct drm_audio_component *acomp = data;
	677	+
	678	+ if (WARN_ON(!device_link_add(hda_kdev, kdev, DL_FLAG_STATELESS)))
	679	+ return -ENOMEM;
	680	+
	681	+ drm_modeset_lock_all(drm_dev);
	682	+ acomp->ops = &nv50_audio_component_ops;
	683	+ acomp->dev = kdev;
	684	+ drm->audio.component = acomp;
	685	+ drm_modeset_unlock_all(drm_dev);
	686	+ return 0;
	687	+}
	688	+
	689	+static void
	690	+nv50_audio_component_unbind(struct device kdev, struct device hda_kdev,
	691	+ void *data)
	692	+{
	693	+ struct drm_device *drm_dev = dev_get_drvdata(kdev);
	694	+ struct nouveau_drm *drm = nouveau_drm(drm_dev);
	695	+ struct drm_audio_component *acomp = data;
	696	+
	697	+ drm_modeset_lock_all(drm_dev);
	698	+ drm->audio.component = NULL;
	699	+ acomp->ops = NULL;
	700	+ acomp->dev = NULL;
	701	+ drm_modeset_unlock_all(drm_dev);
	702	+}
	703	+
	704	+static const struct component_ops nv50_audio_component_bind_ops = {
	705	+ .bind = nv50_audio_component_bind,
	706	+ .unbind = nv50_audio_component_unbind,
	707	+};
	708	+
	709	+static void
	710	+nv50_audio_component_init(struct nouveau_drm *drm)
	711	+{
	712	+ if (!component_add(drm->dev->dev, &nv50_audio_component_bind_ops))
	713	+ drm->audio.component_registered = true;
	714	+}
	715	+
	716	+static void
	717	+nv50_audio_component_fini(struct nouveau_drm *drm)
	718	+{
	719	+ if (drm->audio.component_registered) {
	720	+ component_del(drm->dev->dev, &nv50_audio_component_bind_ops);
	721	+ drm->audio.component_registered = false;
	722	+ }
	723	+}
	724	+
463	725	/******************************************************************************
464	726	* Audio
465	727	*****************************************************************************/
466	728	static void
467	729	nv50_audio_disable(struct drm_encoder encoder, struct nouveau_crtc nv_crtc)
468	730	{
	731	+ struct nouveau_drm *drm = nouveau_drm(encoder->dev);
469	732	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
470	733	struct nv50_disp *disp = nv50_disp(encoder->dev);
471	734	struct {
..	..	@@ -479,12 +742,21 @@
479	742	(0x0100 << nv_crtc->index),
480	743	};
481	744
	745	+ if (!nv_encoder->audio)
	746	+ return;
	747	+
	748	+ nv_encoder->audio = false;
482	749	nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
	750	+
	751	+ nv50_audio_component_eld_notify(drm->audio.component, nv_encoder->or,
	752	+ nv_crtc->index);
483	753	}
484	754
485	755	static void
486		-nv50_audio_enable(struct drm_encoder encoder, struct drm_display_mode mode)
	756	+nv50_audio_enable(struct drm_encoder encoder, struct drm_atomic_state state,
	757	+ struct drm_display_mode *mode)
487	758	{
	759	+ struct nouveau_drm *drm = nouveau_drm(encoder->dev);
488	760	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
489	761	struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
490	762	struct nouveau_connector *nv_connector;
..	..	@@ -503,7 +775,7 @@
503	775	(0x0100 << nv_crtc->index),
504	776	};
505	777
506		- nv_connector = nouveau_encoder_connector_get(nv_encoder);
	778	+ nv_connector = nv50_outp_get_new_connector(nv_encoder, state);
507	779	if (!drm_detect_monitor_audio(nv_connector->edid))
508	780	return;
509	781
..	..	@@ -511,6 +783,10 @@
511	783
512	784	nvif_mthd(&disp->disp->object, 0, &args,
513	785	sizeof(args.base) + drm_eld_size(args.data));
	786	+ nv_encoder->audio = true;
	787	+
	788	+ nv50_audio_component_eld_notify(drm->audio.component, nv_encoder->or,
	789	+ nv_crtc->index);
514	790	}
515	791
516	792	/******************************************************************************
..	..	@@ -536,8 +812,10 @@
536	812	}
537	813
538	814	static void
539		-nv50_hdmi_enable(struct drm_encoder encoder, struct drm_display_mode mode)
	815	+nv50_hdmi_enable(struct drm_encoder encoder, struct drm_atomic_state state,
	816	+ struct drm_display_mode *mode)
540	817	{
	818	+ struct nouveau_drm *drm = nouveau_drm(encoder->dev);
541	819	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
542	820	struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
543	821	struct nv50_disp *disp = nv50_disp(encoder->dev);
..	..	@@ -555,18 +833,23 @@
555	833	.pwr.rekey = 56, /* binary driver, and tegra, constant */
556	834	};
557	835	struct nouveau_connector *nv_connector;
	836	+ struct drm_hdmi_info *hdmi;
558	837	u32 max_ac_packet;
559	838	union hdmi_infoframe avi_frame;
560	839	union hdmi_infoframe vendor_frame;
	840	+ bool high_tmds_clock_ratio = false, scrambling = false;
	841	+ u8 config;
561	842	int ret;
562	843	int size;
563	844
564		- nv_connector = nouveau_encoder_connector_get(nv_encoder);
	845	+ nv_connector = nv50_outp_get_new_connector(nv_encoder, state);
565	846	if (!drm_detect_hdmi_monitor(nv_connector->edid))
566	847	return;
567	848
568		- ret = drm_hdmi_avi_infoframe_from_display_mode(&avi_frame.avi, mode,
569		- false);
	849	+ hdmi = &nv_connector->base.display_info.hdmi;
	850	+
	851	+ ret = drm_hdmi_avi_infoframe_from_display_mode(&avi_frame.avi,
	852	+ &nv_connector->base, mode);
570	853	if (!ret) {
571	854	/* We have an AVI InfoFrame, populate it to the display */
572	855	args.pwr.avi_infoframe_length
..	..	@@ -589,12 +872,42 @@
589	872	max_ac_packet -= 18; /* constant from tegra */
590	873	args.pwr.max_ac_packet = max_ac_packet / 32;
591	874
	875	+ if (hdmi->scdc.scrambling.supported) {
	876	+ high_tmds_clock_ratio = mode->clock > 340000;
	877	+ scrambling = high_tmds_clock_ratio \|\|
	878	+ hdmi->scdc.scrambling.low_rates;
	879	+ }
	880	+
	881	+ args.pwr.scdc =
	882	+ NV50_DISP_SOR_HDMI_PWR_V0_SCDC_SCRAMBLE * scrambling \|
	883	+ NV50_DISP_SOR_HDMI_PWR_V0_SCDC_DIV_BY_4 * high_tmds_clock_ratio;
	884	+
592	885	size = sizeof(args.base)
593	886	+ sizeof(args.pwr)
594	887	+ args.pwr.avi_infoframe_length
595	888	+ args.pwr.vendor_infoframe_length;
596	889	nvif_mthd(&disp->disp->object, 0, &args, size);
597		- nv50_audio_enable(encoder, mode);
	890	+
	891	+ nv50_audio_enable(encoder, state, mode);
	892	+
	893	+ /* If SCDC is supported by the downstream monitor, update
	894	+ * divider / scrambling settings to what we programmed above.
	895	+ */
	896	+ if (!hdmi->scdc.scrambling.supported)
	897	+ return;
	898	+
	899	+ ret = drm_scdc_readb(nv_encoder->i2c, SCDC_TMDS_CONFIG, &config);
	900	+ if (ret < 0) {
	901	+ NV_ERROR(drm, "Failure to read SCDC_TMDS_CONFIG: %d\n", ret);
	902	+ return;
	903	+ }
	904	+ config &= ~(SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 \| SCDC_SCRAMBLING_ENABLE);
	905	+ config \|= SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 * high_tmds_clock_ratio;
	906	+ config \|= SCDC_SCRAMBLING_ENABLE * scrambling;
	907	+ ret = drm_scdc_writeb(nv_encoder->i2c, SCDC_TMDS_CONFIG, config);
	908	+ if (ret < 0)
	909	+ NV_ERROR(drm, "Failure to write SCDC_TMDS_CONFIG = 0x%02x: %d\n",
	910	+ config, ret);
598	911	}
599	912
600	913	/******************************************************************************
..	..	@@ -604,17 +917,6 @@
604	917	#define nv50_mstc(p) container_of((p), struct nv50_mstc, connector)
605	918	#define nv50_msto(p) container_of((p), struct nv50_msto, encoder)
606	919
607		-struct nv50_mstm {
608		- struct nouveau_encoder *outp;
609		-
610		- struct drm_dp_mst_topology_mgr mgr;
611		- struct nv50_msto *msto[4];
612		-
613		- bool modified;
614		- bool disabled;
615		- int links;
616		-};
617		-
618	920	struct nv50_mstc {
619	921	struct nv50_mstm *mstm;
620	922	struct drm_dp_mst_port *port;
..	..	@@ -622,8 +924,6 @@
622	924
623	925	struct drm_display_mode *native;
624	926	struct edid *edid;
625		-
626		- int pbn;
627	927	};
628	928
629	929	struct nv50_msto {
..	..	@@ -634,6 +934,19 @@
634	934	bool disabled;
635	935	};
636	936
	937	+struct nouveau_encoder nv50_real_outp(struct drm_encoder encoder)
	938	+{
	939	+ struct nv50_msto *msto;
	940	+
	941	+ if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST)
	942	+ return nouveau_encoder(encoder);
	943	+
	944	+ msto = nv50_msto(encoder);
	945	+ if (!msto->mstc)
	946	+ return NULL;
	947	+ return msto->mstc->mstm->outp;
	948	+}
	949	+
637	950	static struct drm_dp_payload *
638	951	nv50_msto_payload(struct nv50_msto *msto)
639	952	{
..	..	@@ -641,6 +954,8 @@
641	954	struct nv50_mstc *mstc = msto->mstc;
642	955	struct nv50_mstm *mstm = mstc->mstm;
643	956	int vcpi = mstc->port->vcpi.vcpi, i;
	957	+
	958	+ WARN_ON(!mutex_is_locked(&mstm->mgr.payload_lock));
644	959
645	960	NV_ATOMIC(drm, "%s: vcpi %d\n", msto->encoder.name, vcpi);
646	961	for (i = 0; i < mstm->mgr.max_payloads; i++) {
..	..	@@ -666,14 +981,15 @@
666	981	struct nv50_mstc *mstc = msto->mstc;
667	982	struct nv50_mstm *mstm = mstc->mstm;
668	983
	984	+ if (!msto->disabled)
	985	+ return;
	986	+
669	987	NV_ATOMIC(drm, "%s: msto cleanup\n", msto->encoder.name);
670		- if (mstc->port && mstc->port->vcpi.vcpi > 0 && !nv50_msto_payload(msto))
671		- drm_dp_mst_deallocate_vcpi(&mstm->mgr, mstc->port);
672		- if (msto->disabled) {
673		- msto->mstc = NULL;
674		- msto->head = NULL;
675		- msto->disabled = false;
676		- }
	988	+
	989	+ drm_dp_mst_deallocate_vcpi(&mstm->mgr, mstc->port);
	990	+
	991	+ msto->mstc = NULL;
	992	+ msto->disabled = false;
677	993	}
678	994
679	995	static void
..	..	@@ -693,8 +1009,10 @@
693	1009	(0x0100 << msto->head->base.index),
694	1010	};
695	1011
	1012	+ mutex_lock(&mstm->mgr.payload_lock);
	1013	+
696	1014	NV_ATOMIC(drm, "%s: msto prepare\n", msto->encoder.name);
697		- if (mstc->port && mstc->port->vcpi.vcpi > 0) {
	1015	+ if (mstc->port->vcpi.vcpi > 0) {
698	1016	struct drm_dp_payload *payload = nv50_msto_payload(msto);
699	1017	if (payload) {
700	1018	args.vcpi.start_slot = payload->start_slot;
..	..	@@ -708,7 +1026,9 @@
708	1026	msto->encoder.name, msto->head->base.base.name,
709	1027	args.vcpi.start_slot, args.vcpi.num_slots,
710	1028	args.vcpi.pbn, args.vcpi.aligned_pbn);
	1029	+
711	1030	nvif_mthd(&drm->display->disp.object, 0, &args, sizeof(args));
	1031	+ mutex_unlock(&mstm->mgr.payload_lock);
712	1032	}
713	1033
714	1034	static int
..	..	@@ -716,32 +1036,67 @@
716	1036	struct drm_crtc_state *crtc_state,
717	1037	struct drm_connector_state *conn_state)
718	1038	{
719		- struct nv50_mstc *mstc = nv50_mstc(conn_state->connector);
	1039	+ struct drm_atomic_state *state = crtc_state->state;
	1040	+ struct drm_connector *connector = conn_state->connector;
	1041	+ struct nv50_mstc *mstc = nv50_mstc(connector);
720	1042	struct nv50_mstm *mstm = mstc->mstm;
721		- int bpp = conn_state->connector->display_info.bpc * 3;
	1043	+ struct nv50_head_atom *asyh = nv50_head_atom(crtc_state);
722	1044	int slots;
	1045	+ int ret;
723	1046
724		- mstc->pbn = drm_dp_calc_pbn_mode(crtc_state->adjusted_mode.clock, bpp);
	1047	+ ret = nv50_outp_atomic_check_view(encoder, crtc_state, conn_state,
	1048	+ mstc->native);
	1049	+ if (ret)
	1050	+ return ret;
725	1051
726		- slots = drm_dp_find_vcpi_slots(&mstm->mgr, mstc->pbn);
	1052	+ if (!crtc_state->mode_changed && !crtc_state->connectors_changed)
	1053	+ return 0;
	1054	+
	1055	+ /*
	1056	+ * When restoring duplicated states, we need to make sure that the bw
	1057	+ * remains the same and avoid recalculating it, as the connector's bpc
	1058	+ * may have changed after the state was duplicated
	1059	+ */
	1060	+ if (!state->duplicated) {
	1061	+ const int clock = crtc_state->adjusted_mode.clock;
	1062	+
	1063	+ asyh->or.bpc = connector->display_info.bpc;
	1064	+ asyh->dp.pbn = drm_dp_calc_pbn_mode(clock, asyh->or.bpc * 3,
	1065	+ false);
	1066	+ }
	1067	+
	1068	+ slots = drm_dp_atomic_find_vcpi_slots(state, &mstm->mgr, mstc->port,
	1069	+ asyh->dp.pbn, 0);
727	1070	if (slots < 0)
728	1071	return slots;
729	1072
730		- return nv50_outp_atomic_check_view(encoder, crtc_state, conn_state,
731		- mstc->native);
	1073	+ asyh->dp.tu = slots;
	1074	+
	1075	+ return 0;
	1076	+}
	1077	+
	1078	+static u8
	1079	+nv50_dp_bpc_to_depth(unsigned int bpc)
	1080	+{
	1081	+ switch (bpc) {
	1082	+ case 6: return NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_18_444;
	1083	+ case 8: return NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_444;
	1084	+ case 10:
	1085	+ default: return NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_30_444;
	1086	+ }
732	1087	}
733	1088
734	1089	static void
735		-nv50_msto_enable(struct drm_encoder *encoder)
	1090	+nv50_msto_enable(struct drm_encoder encoder, struct drm_atomic_state state)
736	1091	{
737	1092	struct nv50_head *head = nv50_head(encoder->crtc);
	1093	+ struct nv50_head_atom *armh = nv50_head_atom(head->base.base.state);
738	1094	struct nv50_msto *msto = nv50_msto(encoder);
739	1095	struct nv50_mstc *mstc = NULL;
740	1096	struct nv50_mstm *mstm = NULL;
741	1097	struct drm_connector *connector;
742	1098	struct drm_connector_list_iter conn_iter;
743		- u8 proto, depth;
744		- int slots;
	1099	+ u8 proto;
745	1100	bool r;
746	1101
747	1102	drm_connector_list_iter_begin(encoder->dev, &conn_iter);
..	..	@@ -757,43 +1112,34 @@
757	1112	if (WARN_ON(!mstc))
758	1113	return;
759	1114
760		- slots = drm_dp_find_vcpi_slots(&mstm->mgr, mstc->pbn);
761		- r = drm_dp_mst_allocate_vcpi(&mstm->mgr, mstc->port, mstc->pbn, slots);
	1115	+ r = drm_dp_mst_allocate_vcpi(&mstm->mgr, mstc->port, armh->dp.pbn,
	1116	+ armh->dp.tu);
762	1117	if (!r)
763	1118	DRM_DEBUG_KMS("Failed to allocate VCPI\n");
764	1119
765	1120	if (!mstm->links++)
766		- nv50_outp_acquire(mstm->outp);
	1121	+ nv50_outp_acquire(mstm->outp, false /XXX: MST audio./);
767	1122
768	1123	if (mstm->outp->link & 1)
769		- proto = 0x8;
	1124	+ proto = NV917D_SOR_SET_CONTROL_PROTOCOL_DP_A;
770	1125	else
771		- proto = 0x9;
	1126	+ proto = NV917D_SOR_SET_CONTROL_PROTOCOL_DP_B;
772	1127
773		- switch (mstc->connector.display_info.bpc) {
774		- case 6: depth = 0x2; break;
775		- case 8: depth = 0x5; break;
776		- case 10:
777		- default: depth = 0x6; break;
778		- }
	1128	+ mstm->outp->update(mstm->outp, head->base.index, armh, proto,
	1129	+ nv50_dp_bpc_to_depth(armh->or.bpc));
779	1130
780		- mstm->outp->update(mstm->outp, head->base.index,
781		- nv50_head_atom(head->base.base.state), proto, depth);
782		-
783		- msto->head = head;
784	1131	msto->mstc = mstc;
785	1132	mstm->modified = true;
786	1133	}
787	1134
788	1135	static void
789		-nv50_msto_disable(struct drm_encoder *encoder)
	1136	+nv50_msto_disable(struct drm_encoder encoder, struct drm_atomic_state state)
790	1137	{
791	1138	struct nv50_msto *msto = nv50_msto(encoder);
792	1139	struct nv50_mstc *mstc = msto->mstc;
793	1140	struct nv50_mstm *mstm = mstc->mstm;
794	1141
795		- if (mstc->port)
796		- drm_dp_mst_reset_vcpi_slots(&mstm->mgr, mstc->port);
	1142	+ drm_dp_mst_reset_vcpi_slots(&mstm->mgr, mstc->port);
797	1143
798	1144	mstm->outp->update(mstm->outp, msto->head->base.index, NULL, 0, 0);
799	1145	mstm->modified = true;
..	..	@@ -804,8 +1150,8 @@
804	1150
805	1151	static const struct drm_encoder_helper_funcs
806	1152	nv50_msto_help = {
807		- .disable = nv50_msto_disable,
808		- .enable = nv50_msto_enable,
	1153	+ .atomic_disable = nv50_msto_disable,
	1154	+ .atomic_enable = nv50_msto_enable,
809	1155	.atomic_check = nv50_msto_atomic_check,
810	1156	};
811	1157
..	..	@@ -822,52 +1168,54 @@
822	1168	.destroy = nv50_msto_destroy,
823	1169	};
824	1170
825		-static int
826		-nv50_msto_new(struct drm_device dev, u32 heads, const char name, int id,
827		- struct nv50_msto **pmsto)
	1171	+static struct nv50_msto *
	1172	+nv50_msto_new(struct drm_device dev, struct nv50_head head, int id)
828	1173	{
829	1174	struct nv50_msto *msto;
830	1175	int ret;
831	1176
832		- if (!(msto = pmsto = kzalloc(sizeof(msto), GFP_KERNEL)))
833		- return -ENOMEM;
	1177	+ msto = kzalloc(sizeof(*msto), GFP_KERNEL);
	1178	+ if (!msto)
	1179	+ return ERR_PTR(-ENOMEM);
834	1180
835	1181	ret = drm_encoder_init(dev, &msto->encoder, &nv50_msto,
836		- DRM_MODE_ENCODER_DPMST, "%s-mst-%d", name, id);
	1182	+ DRM_MODE_ENCODER_DPMST, "mst-%d", id);
837	1183	if (ret) {
838		- kfree(*pmsto);
839		- *pmsto = NULL;
840		- return ret;
	1184	+ kfree(msto);
	1185	+ return ERR_PTR(ret);
841	1186	}
842	1187
843	1188	drm_encoder_helper_add(&msto->encoder, &nv50_msto_help);
844		- msto->encoder.possible_crtcs = heads;
845		- return 0;
	1189	+ msto->encoder.possible_crtcs = drm_crtc_mask(&head->base.base);
	1190	+ msto->head = head;
	1191	+ return msto;
846	1192	}
847	1193
848	1194	static struct drm_encoder *
849	1195	nv50_mstc_atomic_best_encoder(struct drm_connector *connector,
850	1196	struct drm_connector_state *connector_state)
851	1197	{
852		- struct nv50_head *head = nv50_head(connector_state->crtc);
853	1198	struct nv50_mstc *mstc = nv50_mstc(connector);
	1199	+ struct drm_crtc *crtc = connector_state->crtc;
854	1200
855		- return &mstc->mstm->msto[head->base.index]->encoder;
856		-}
	1201	+ if (!(mstc->mstm->outp->dcb->heads & drm_crtc_mask(crtc)))
	1202	+ return NULL;
857	1203
858		-static struct drm_encoder *
859		-nv50_mstc_best_encoder(struct drm_connector *connector)
860		-{
861		- struct nv50_mstc *mstc = nv50_mstc(connector);
862		-
863		- return &mstc->mstm->msto[0]->encoder;
	1204	+ return &nv50_head(crtc)->msto->encoder;
864	1205	}
865	1206
866	1207	static enum drm_mode_status
867	1208	nv50_mstc_mode_valid(struct drm_connector *connector,
868	1209	struct drm_display_mode *mode)
869	1210	{
870		- return MODE_OK;
	1211	+ struct nv50_mstc *mstc = nv50_mstc(connector);
	1212	+ struct nouveau_encoder *outp = mstc->mstm->outp;
	1213	+
	1214	+ /* TODO: calculate the PBN from the dotclock and validate against the
	1215	+ * MSTB's max possible PBN
	1216	+ */
	1217	+
	1218	+ return nv50_dp_mode_valid(connector, outp, mode, NULL);
871	1219	}
872	1220
873	1221	static int
..	..	@@ -881,8 +1229,17 @@
881	1229	if (mstc->edid)
882	1230	ret = drm_add_edid_modes(&mstc->connector, mstc->edid);
883	1231
884		- if (!mstc->connector.display_info.bpc)
885		- mstc->connector.display_info.bpc = 8;
	1232	+ /*
	1233	+ * XXX: Since we don't use HDR in userspace quite yet, limit the bpc
	1234	+ * to 8 to save bandwidth on the topology. In the future, we'll want
	1235	+ * to properly fix this by dynamically selecting the highest possible
	1236	+ * bpc that would fit in the topology
	1237	+ */
	1238	+ if (connector->display_info.bpc)
	1239	+ connector->display_info.bpc =
	1240	+ clamp(connector->display_info.bpc, 6U, 8U);
	1241	+ else
	1242	+ connector->display_info.bpc = 8;
886	1243
887	1244	if (mstc->native)
888	1245	drm_mode_destroy(mstc->connector.dev, mstc->native);
..	..	@@ -890,22 +1247,45 @@
890	1247	return ret;
891	1248	}
892	1249
893		-static const struct drm_connector_helper_funcs
894		-nv50_mstc_help = {
895		- .get_modes = nv50_mstc_get_modes,
896		- .mode_valid = nv50_mstc_mode_valid,
897		- .best_encoder = nv50_mstc_best_encoder,
898		- .atomic_best_encoder = nv50_mstc_atomic_best_encoder,
899		-};
900		-
901		-static enum drm_connector_status
902		-nv50_mstc_detect(struct drm_connector *connector, bool force)
	1250	+static int
	1251	+nv50_mstc_atomic_check(struct drm_connector *connector,
	1252	+ struct drm_atomic_state *state)
903	1253	{
904	1254	struct nv50_mstc *mstc = nv50_mstc(connector);
905		- enum drm_connector_status conn_status;
	1255	+ struct drm_dp_mst_topology_mgr *mgr = &mstc->mstm->mgr;
	1256	+ struct drm_connector_state *new_conn_state =
	1257	+ drm_atomic_get_new_connector_state(state, connector);
	1258	+ struct drm_connector_state *old_conn_state =
	1259	+ drm_atomic_get_old_connector_state(state, connector);
	1260	+ struct drm_crtc_state *crtc_state;
	1261	+ struct drm_crtc *new_crtc = new_conn_state->crtc;
	1262	+
	1263	+ if (!old_conn_state->crtc)
	1264	+ return 0;
	1265	+
	1266	+ /* We only want to free VCPI if this state disables the CRTC on this
	1267	+ * connector
	1268	+ */
	1269	+ if (new_crtc) {
	1270	+ crtc_state = drm_atomic_get_new_crtc_state(state, new_crtc);
	1271	+
	1272	+ if (!crtc_state \|\|
	1273	+ !drm_atomic_crtc_needs_modeset(crtc_state) \|\|
	1274	+ crtc_state->enable)
	1275	+ return 0;
	1276	+ }
	1277	+
	1278	+ return drm_dp_atomic_release_vcpi_slots(state, mgr, mstc->port);
	1279	+}
	1280	+
	1281	+static int
	1282	+nv50_mstc_detect(struct drm_connector *connector,
	1283	+ struct drm_modeset_acquire_ctx *ctx, bool force)
	1284	+{
	1285	+ struct nv50_mstc *mstc = nv50_mstc(connector);
906	1286	int ret;
907	1287
908		- if (!mstc->port)
	1288	+ if (drm_connector_is_unregistered(connector))
909	1289	return connector_status_disconnected;
910	1290
911	1291	ret = pm_runtime_get_sync(connector->dev->dev);
..	..	@@ -914,26 +1294,40 @@
914	1294	return connector_status_disconnected;
915	1295	}
916	1296
917		- conn_status = drm_dp_mst_detect_port(connector, mstc->port->mgr,
918		- mstc->port);
	1297	+ ret = drm_dp_mst_detect_port(connector, ctx, mstc->port->mgr,
	1298	+ mstc->port);
	1299	+ if (ret != connector_status_connected)
	1300	+ goto out;
919	1301
	1302	+out:
920	1303	pm_runtime_mark_last_busy(connector->dev->dev);
921	1304	pm_runtime_put_autosuspend(connector->dev->dev);
922		- return conn_status;
	1305	+ return ret;
923	1306	}
	1307	+
	1308	+static const struct drm_connector_helper_funcs
	1309	+nv50_mstc_help = {
	1310	+ .get_modes = nv50_mstc_get_modes,
	1311	+ .mode_valid = nv50_mstc_mode_valid,
	1312	+ .atomic_best_encoder = nv50_mstc_atomic_best_encoder,
	1313	+ .atomic_check = nv50_mstc_atomic_check,
	1314	+ .detect_ctx = nv50_mstc_detect,
	1315	+};
924	1316
925	1317	static void
926	1318	nv50_mstc_destroy(struct drm_connector *connector)
927	1319	{
928	1320	struct nv50_mstc *mstc = nv50_mstc(connector);
	1321	+
929	1322	drm_connector_cleanup(&mstc->connector);
	1323	+ drm_dp_mst_put_port_malloc(mstc->port);
	1324	+
930	1325	kfree(mstc);
931	1326	}
932	1327
933	1328	static const struct drm_connector_funcs
934	1329	nv50_mstc = {
935	1330	.reset = nouveau_conn_reset,
936		- .detect = nv50_mstc_detect,
937	1331	.fill_modes = drm_helper_probe_single_connector_modes,
938	1332	.destroy = nv50_mstc_destroy,
939	1333	.atomic_duplicate_state = nouveau_conn_atomic_duplicate_state,
..	..	@@ -947,8 +1341,9 @@
947	1341	const char path, struct nv50_mstc *pmstc)
948	1342	{
949	1343	struct drm_device *dev = mstm->outp->base.base.dev;
	1344	+ struct drm_crtc *crtc;
950	1345	struct nv50_mstc *mstc;
951		- int ret, i;
	1346	+ int ret;
952	1347
953	1348	if (!(mstc = pmstc = kzalloc(sizeof(mstc), GFP_KERNEL)))
954	1349	return -ENOMEM;
..	..	@@ -968,12 +1363,18 @@
968	1363	mstc->connector.funcs->reset(&mstc->connector);
969	1364	nouveau_conn_attach_properties(&mstc->connector);
970	1365
971		- for (i = 0; i < ARRAY_SIZE(mstm->msto) && mstm->msto[i]; i++)
972		- drm_connector_attach_encoder(&mstc->connector, &mstm->msto[i]->encoder);
	1366	+ drm_for_each_crtc(crtc, dev) {
	1367	+ if (!(mstm->outp->dcb->heads & drm_crtc_mask(crtc)))
	1368	+ continue;
	1369	+
	1370	+ drm_connector_attach_encoder(&mstc->connector,
	1371	+ &nv50_head(crtc)->msto->encoder);
	1372	+ }
973	1373
974	1374	drm_object_attach_property(&mstc->connector.base, dev->mode_config.path_property, 0);
975	1375	drm_object_attach_property(&mstc->connector.base, dev->mode_config.tile_property, 0);
976	1376	drm_connector_set_path_property(&mstc->connector, path);
	1377	+ drm_dp_mst_get_port_malloc(port);
977	1378	return 0;
978	1379	}
979	1380
..	..	@@ -1027,41 +1428,6 @@
1027	1428	}
1028	1429	}
1029	1430
1030		-static void
1031		-nv50_mstm_hotplug(struct drm_dp_mst_topology_mgr *mgr)
1032		-{
1033		- struct nv50_mstm *mstm = nv50_mstm(mgr);
1034		- drm_kms_helper_hotplug_event(mstm->outp->base.base.dev);
1035		-}
1036		-
1037		-static void
1038		-nv50_mstm_destroy_connector(struct drm_dp_mst_topology_mgr *mgr,
1039		- struct drm_connector *connector)
1040		-{
1041		- struct nouveau_drm *drm = nouveau_drm(connector->dev);
1042		- struct nv50_mstc *mstc = nv50_mstc(connector);
1043		-
1044		- drm_connector_unregister(&mstc->connector);
1045		-
1046		- drm_fb_helper_remove_one_connector(&drm->fbcon->helper, &mstc->connector);
1047		-
1048		- drm_modeset_lock(&drm->dev->mode_config.connection_mutex, NULL);
1049		- mstc->port = NULL;
1050		- drm_modeset_unlock(&drm->dev->mode_config.connection_mutex);
1051		-
1052		- drm_connector_put(&mstc->connector);
1053		-}
1054		-
1055		-static void
1056		-nv50_mstm_register_connector(struct drm_connector *connector)
1057		-{
1058		- struct nouveau_drm *drm = nouveau_drm(connector->dev);
1059		-
1060		- drm_fb_helper_add_one_connector(&drm->fbcon->helper, connector);
1061		-
1062		- drm_connector_register(connector);
1063		-}
1064		-
1065	1431	static struct drm_connector *
1066	1432	nv50_mstm_add_connector(struct drm_dp_mst_topology_mgr *mgr,
1067	1433	struct drm_dp_mst_port port, const char path)
..	..	@@ -1071,11 +1437,8 @@
1071	1437	int ret;
1072	1438
1073	1439	ret = nv50_mstc_new(mstm, port, path, &mstc);
1074		- if (ret) {
1075		- if (mstc)
1076		- mstc->connector.funcs->destroy(&mstc->connector);
	1440	+ if (ret)
1077	1441	return NULL;
1078		- }
1079	1442
1080	1443	return &mstc->connector;
1081	1444	}
..	..	@@ -1083,46 +1446,53 @@
1083	1446	static const struct drm_dp_mst_topology_cbs
1084	1447	nv50_mstm = {
1085	1448	.add_connector = nv50_mstm_add_connector,
1086		- .register_connector = nv50_mstm_register_connector,
1087		- .destroy_connector = nv50_mstm_destroy_connector,
1088		- .hotplug = nv50_mstm_hotplug,
1089	1449	};
1090	1450
1091		-void
1092		-nv50_mstm_service(struct nv50_mstm *mstm)
	1451	+bool
	1452	+nv50_mstm_service(struct nouveau_drm *drm,
	1453	+ struct nouveau_connector *nv_connector,
	1454	+ struct nv50_mstm *mstm)
1093	1455	{
1094		- struct drm_dp_aux *aux = mstm ? mstm->mgr.aux : NULL;
1095		- bool handled = true;
1096		- int ret;
	1456	+ struct drm_dp_aux *aux = &nv_connector->aux;
	1457	+ bool handled = true, ret = true;
	1458	+ int rc;
1097	1459	u8 esi[8] = {};
1098	1460
1099		- if (!aux)
1100		- return;
1101		-
1102	1461	while (handled) {
1103		- ret = drm_dp_dpcd_read(aux, DP_SINK_COUNT_ESI, esi, 8);
1104		- if (ret != 8) {
1105		- drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false);
1106		- return;
	1462	+ rc = drm_dp_dpcd_read(aux, DP_SINK_COUNT_ESI, esi, 8);
	1463	+ if (rc != 8) {
	1464	+ ret = false;
	1465	+ break;
1107	1466	}
1108	1467
1109	1468	drm_dp_mst_hpd_irq(&mstm->mgr, esi, &handled);
1110	1469	if (!handled)
1111	1470	break;
1112	1471
1113		- drm_dp_dpcd_write(aux, DP_SINK_COUNT_ESI + 1, &esi[1], 3);
	1472	+ rc = drm_dp_dpcd_write(aux, DP_SINK_COUNT_ESI + 1, &esi[1],
	1473	+ 3);
	1474	+ if (rc != 3) {
	1475	+ ret = false;
	1476	+ break;
	1477	+ }
1114	1478	}
	1479	+
	1480	+ if (!ret)
	1481	+ NV_DEBUG(drm, "Failed to handle ESI on %s: %d\n",
	1482	+ nv_connector->base.name, rc);
	1483	+
	1484	+ return ret;
1115	1485	}
1116	1486
1117	1487	void
1118	1488	nv50_mstm_remove(struct nv50_mstm *mstm)
1119	1489	{
1120		- if (mstm)
1121		- drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false);
	1490	+ mstm->is_mst = false;
	1491	+ drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false);
1122	1492	}
1123	1493
1124	1494	static int
1125		-nv50_mstm_enable(struct nv50_mstm *mstm, u8 dpcd, int state)
	1495	+nv50_mstm_enable(struct nv50_mstm *mstm, int state)
1126	1496	{
1127	1497	struct nouveau_encoder *outp = mstm->outp;
1128	1498	struct {
..	..	@@ -1137,106 +1507,85 @@
1137	1507	};
1138	1508	struct nouveau_drm *drm = nouveau_drm(outp->base.base.dev);
1139	1509	struct nvif_object *disp = &drm->display->disp.object;
1140		- int ret;
1141		-
1142		- if (dpcd >= 0x12) {
1143		- /* Even if we're enabling MST, start with disabling the
1144		- * branching unit to clear any sink-side MST topology state
1145		- * that wasn't set by us
1146		- */
1147		- ret = drm_dp_dpcd_writeb(mstm->mgr.aux, DP_MSTM_CTRL, 0);
1148		- if (ret < 0)
1149		- return ret;
1150		-
1151		- if (state) {
1152		- /* Now, start initializing */
1153		- ret = drm_dp_dpcd_writeb(mstm->mgr.aux, DP_MSTM_CTRL,
1154		- DP_MST_EN);
1155		- if (ret < 0)
1156		- return ret;
1157		- }
1158		- }
1159	1510
1160	1511	return nvif_mthd(disp, 0, &args, sizeof(args));
1161	1512	}
1162	1513
1163	1514	int
1164		-nv50_mstm_detect(struct nv50_mstm *mstm, u8 dpcd[8], int allow)
	1515	+nv50_mstm_detect(struct nouveau_encoder *outp)
1165	1516	{
	1517	+ struct nv50_mstm *mstm = outp->dp.mstm;
1166	1518	struct drm_dp_aux *aux;
1167	1519	int ret;
1168		- bool old_state, new_state;
1169		- u8 mstm_ctrl;
1170	1520
1171		- if (!mstm)
	1521	+ if (!mstm \|\| !mstm->can_mst)
1172	1522	return 0;
1173	1523
1174		- mutex_lock(&mstm->mgr.lock);
1175		-
1176		- old_state = mstm->mgr.mst_state;
1177		- new_state = old_state;
1178	1524	aux = mstm->mgr.aux;
1179	1525
1180		- if (old_state) {
1181		- /* Just check that the MST hub is still as we expect it */
1182		- ret = drm_dp_dpcd_readb(aux, DP_MSTM_CTRL, &mstm_ctrl);
1183		- if (ret < 0 \|\| !(mstm_ctrl & DP_MST_EN)) {
1184		- DRM_DEBUG_KMS("Hub gone, disabling MST topology\n");
1185		- new_state = false;
1186		- }
1187		- } else if (dpcd[0] >= 0x12) {
1188		- ret = drm_dp_dpcd_readb(aux, DP_MSTM_CAP, &dpcd[1]);
1189		- if (ret < 0)
1190		- goto probe_error;
	1526	+ /* Clear any leftover MST state we didn't set ourselves by first
	1527	+ * disabling MST if it was already enabled
	1528	+ */
	1529	+ ret = drm_dp_dpcd_writeb(aux, DP_MSTM_CTRL, 0);
	1530	+ if (ret < 0)
	1531	+ return ret;
1191	1532
1192		- if (!(dpcd[1] & DP_MST_CAP))
1193		- dpcd[0] = 0x11;
1194		- else
1195		- new_state = allow;
	1533	+ /* And start enabling */
	1534	+ ret = nv50_mstm_enable(mstm, true);
	1535	+ if (ret)
	1536	+ return ret;
	1537	+
	1538	+ ret = drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, true);
	1539	+ if (ret) {
	1540	+ nv50_mstm_enable(mstm, false);
	1541	+ return ret;
1196	1542	}
1197	1543
1198		- if (new_state == old_state) {
1199		- mutex_unlock(&mstm->mgr.lock);
1200		- return new_state;
1201		- }
1202		-
1203		- ret = nv50_mstm_enable(mstm, dpcd[0], new_state);
1204		- if (ret)
1205		- goto probe_error;
1206		-
1207		- mutex_unlock(&mstm->mgr.lock);
1208		-
1209		- ret = drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, new_state);
1210		- if (ret)
1211		- return nv50_mstm_enable(mstm, dpcd[0], 0);
1212		-
1213		- return new_state;
1214		-
1215		-probe_error:
1216		- mutex_unlock(&mstm->mgr.lock);
1217		- return ret;
	1544	+ mstm->is_mst = true;
	1545	+ return 1;
1218	1546	}
1219	1547
1220	1548	static void
1221		-nv50_mstm_fini(struct nv50_mstm *mstm)
	1549	+nv50_mstm_fini(struct nouveau_encoder *outp)
1222	1550	{
1223		- if (mstm && mstm->mgr.mst_state)
	1551	+ struct nv50_mstm *mstm = outp->dp.mstm;
	1552	+
	1553	+ if (!mstm)
	1554	+ return;
	1555	+
	1556	+ /* Don't change the MST state of this connector until we've finished
	1557	+ * resuming, since we can't safely grab hpd_irq_lock in our resume
	1558	+ * path to protect mstm->is_mst without potentially deadlocking
	1559	+ */
	1560	+ mutex_lock(&outp->dp.hpd_irq_lock);
	1561	+ mstm->suspended = true;
	1562	+ mutex_unlock(&outp->dp.hpd_irq_lock);
	1563	+
	1564	+ if (mstm->is_mst)
1224	1565	drm_dp_mst_topology_mgr_suspend(&mstm->mgr);
1225	1566	}
1226	1567
1227	1568	static void
1228		-nv50_mstm_init(struct nv50_mstm *mstm)
	1569	+nv50_mstm_init(struct nouveau_encoder *outp, bool runtime)
1229	1570	{
1230		- int ret;
	1571	+ struct nv50_mstm *mstm = outp->dp.mstm;
	1572	+ int ret = 0;
1231	1573
1232		- if (!mstm \|\| !mstm->mgr.mst_state)
	1574	+ if (!mstm)
1233	1575	return;
1234	1576
1235		- ret = drm_dp_mst_topology_mgr_resume(&mstm->mgr);
1236		- if (ret == -1) {
1237		- drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false);
1238		- drm_kms_helper_hotplug_event(mstm->mgr.dev);
	1577	+ if (mstm->is_mst) {
	1578	+ ret = drm_dp_mst_topology_mgr_resume(&mstm->mgr, !runtime);
	1579	+ if (ret == -1)
	1580	+ nv50_mstm_remove(mstm);
1239	1581	}
	1582	+
	1583	+ mutex_lock(&outp->dp.hpd_irq_lock);
	1584	+ mstm->suspended = false;
	1585	+ mutex_unlock(&outp->dp.hpd_irq_lock);
	1586	+
	1587	+ if (ret == -1)
	1588	+ drm_kms_helper_hotplug_event(mstm->mgr.dev);
1240	1589	}
1241	1590
1242	1591	static void
..	..	@@ -1257,18 +1606,7 @@
1257	1606	const int max_payloads = hweight8(outp->dcb->heads);
1258	1607	struct drm_device *dev = outp->base.base.dev;
1259	1608	struct nv50_mstm *mstm;
1260		- int ret, i;
1261		- u8 dpcd;
1262		-
1263		- /* This is a workaround for some monitors not functioning
1264		- * correctly in MST mode on initial module load. I think
1265		- * some bad interaction with the VBIOS may be responsible.
1266		- *
1267		- * A good ol' off and on again seems to work here ;)
1268		- */
1269		- ret = drm_dp_dpcd_readb(aux, DP_DPCD_REV, &dpcd);
1270		- if (ret >= 0 && dpcd >= 0x12)
1271		- drm_dp_dpcd_writeb(aux, DP_MSTM_CTRL, 0);
	1609	+ int ret;
1272	1610
1273	1611	if (!(mstm = pmstm = kzalloc(sizeof(mstm), GFP_KERNEL)))
1274	1612	return -ENOMEM;
..	..	@@ -1279,13 +1617,6 @@
1279	1617	max_payloads, conn_base_id);
1280	1618	if (ret)
1281	1619	return ret;
1282		-
1283		- for (i = 0; i < max_payloads; i++) {
1284		- ret = nv50_msto_new(dev, outp->dcb->heads, outp->base.base.name,
1285		- i, &mstm->msto[i]);
1286		- if (ret)
1287		- return ret;
1288		- }
1289	1620
1290	1621	return 0;
1291	1622	}
..	..	@@ -1302,10 +1633,10 @@
1302	1633
1303	1634	if (!asyh) {
1304	1635	nv_encoder->ctrl &= ~BIT(head);
1305		- if (!(nv_encoder->ctrl & 0x0000000f))
	1636	+ if (NVDEF_TEST(nv_encoder->ctrl, NV507D, SOR_SET_CONTROL, OWNER, ==, NONE))
1306	1637	nv_encoder->ctrl = 0;
1307	1638	} else {
1308		- nv_encoder->ctrl \|= proto << 8;
	1639	+ nv_encoder->ctrl \|= NVVAL(NV507D, SOR_SET_CONTROL, PROTOCOL, proto);
1309	1640	nv_encoder->ctrl \|= BIT(head);
1310	1641	asyh->or.depth = depth;
1311	1642	}
..	..	@@ -1314,23 +1645,27 @@
1314	1645	}
1315	1646
1316	1647	static void
1317		-nv50_sor_disable(struct drm_encoder *encoder)
	1648	+nv50_sor_disable(struct drm_encoder *encoder,
	1649	+ struct drm_atomic_state *state)
1318	1650	{
1319	1651	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1320	1652	struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc);
	1653	+ struct nouveau_connector *nv_connector =
	1654	+ nv50_outp_get_old_connector(nv_encoder, state);
1321	1655
1322	1656	nv_encoder->crtc = NULL;
1323	1657
1324	1658	if (nv_crtc) {
1325		- struct nvkm_i2c_aux *aux = nv_encoder->aux;
	1659	+ struct drm_dp_aux *aux = &nv_connector->aux;
1326	1660	u8 pwr;
1327	1661
1328		- if (aux) {
1329		- int ret = nvkm_rdaux(aux, DP_SET_POWER, &pwr, 1);
	1662	+ if (nv_encoder->dcb->type == DCB_OUTPUT_DP) {
	1663	+ int ret = drm_dp_dpcd_readb(aux, DP_SET_POWER, &pwr);
	1664	+
1330	1665	if (ret == 0) {
1331	1666	pwr &= ~DP_SET_POWER_MASK;
1332	1667	pwr \|= DP_SET_POWER_D3;
1333		- nvkm_wraux(aux, DP_SET_POWER, &pwr, 1);
	1668	+ drm_dp_dpcd_writeb(aux, DP_SET_POWER, pwr);
1334	1669	}
1335	1670	}
1336	1671
..	..	@@ -1342,7 +1677,7 @@
1342	1677	}
1343	1678
1344	1679	static void
1345		-nv50_sor_enable(struct drm_encoder *encoder)
	1680	+nv50_sor_enable(struct drm_encoder encoder, struct drm_atomic_state state)
1346	1681	{
1347	1682	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1348	1683	struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
..	..	@@ -1362,17 +1697,23 @@
1362	1697	struct nouveau_drm *drm = nouveau_drm(dev);
1363	1698	struct nouveau_connector *nv_connector;
1364	1699	struct nvbios *bios = &drm->vbios;
1365		- u8 proto = 0xf;
1366		- u8 depth = 0x0;
	1700	+ bool hda = false;
	1701	+ u8 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_CUSTOM;
	1702	+ u8 depth = NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_DEFAULT;
1367	1703
1368		- nv_connector = nouveau_encoder_connector_get(nv_encoder);
	1704	+ nv_connector = nv50_outp_get_new_connector(nv_encoder, state);
1369	1705	nv_encoder->crtc = encoder->crtc;
1370		- nv50_outp_acquire(nv_encoder);
	1706	+
	1707	+ if ((disp->disp->object.oclass == GT214_DISP \|\|
	1708	+ disp->disp->object.oclass >= GF110_DISP) &&
	1709	+ drm_detect_monitor_audio(nv_connector->edid))
	1710	+ hda = true;
	1711	+ nv50_outp_acquire(nv_encoder, hda);
1371	1712
1372	1713	switch (nv_encoder->dcb->type) {
1373	1714	case DCB_OUTPUT_TMDS:
1374	1715	if (nv_encoder->link & 1) {
1375		- proto = 0x1;
	1716	+ proto = NV507D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A;
1376	1717	/* Only enable dual-link if:
1377	1718	* - Need to (i.e. rate > 165MHz)
1378	1719	* - DCB says we can
..	..	@@ -1382,15 +1723,15 @@
1382	1723	if (mode->clock >= 165000 &&
1383	1724	nv_encoder->dcb->duallink_possible &&
1384	1725	!drm_detect_hdmi_monitor(nv_connector->edid))
1385		- proto \|= 0x4;
	1726	+ proto = NV507D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS;
1386	1727	} else {
1387		- proto = 0x2;
	1728	+ proto = NV507D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B;
1388	1729	}
1389	1730
1390		- nv50_hdmi_enable(&nv_encoder->base.base, mode);
	1731	+ nv50_hdmi_enable(&nv_encoder->base.base, state, mode);
1391	1732	break;
1392	1733	case DCB_OUTPUT_LVDS:
1393		- proto = 0x0;
	1734	+ proto = NV507D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM;
1394	1735
1395	1736	if (bios->fp_no_ddc) {
1396	1737	if (bios->fp.dual_link)
..	..	@@ -1414,27 +1755,21 @@
1414	1755	lvds.lvds.script \|= 0x0200;
1415	1756	}
1416	1757
1417		- if (nv_connector->base.display_info.bpc == 8)
	1758	+ if (asyh->or.bpc == 8)
1418	1759	lvds.lvds.script \|= 0x0200;
1419	1760	}
1420	1761
1421	1762	nvif_mthd(&disp->disp->object, 0, &lvds, sizeof(lvds));
1422	1763	break;
1423	1764	case DCB_OUTPUT_DP:
1424		- if (nv_connector->base.display_info.bpc == 6)
1425		- depth = 0x2;
1426		- else
1427		- if (nv_connector->base.display_info.bpc == 8)
1428		- depth = 0x5;
1429		- else
1430		- depth = 0x6;
	1765	+ depth = nv50_dp_bpc_to_depth(asyh->or.bpc);
1431	1766
1432	1767	if (nv_encoder->link & 1)
1433		- proto = 0x8;
	1768	+ proto = NV887D_SOR_SET_CONTROL_PROTOCOL_DP_A;
1434	1769	else
1435		- proto = 0x9;
	1770	+ proto = NV887D_SOR_SET_CONTROL_PROTOCOL_DP_B;
1436	1771
1437		- nv50_audio_enable(encoder, mode);
	1772	+ nv50_audio_enable(encoder, state, mode);
1438	1773	break;
1439	1774	default:
1440	1775	BUG();
..	..	@@ -1447,8 +1782,8 @@
1447	1782	static const struct drm_encoder_helper_funcs
1448	1783	nv50_sor_help = {
1449	1784	.atomic_check = nv50_outp_atomic_check,
1450		- .enable = nv50_sor_enable,
1451		- .disable = nv50_sor_disable,
	1785	+ .atomic_enable = nv50_sor_enable,
	1786	+ .atomic_disable = nv50_sor_disable,
1452	1787	};
1453	1788
1454	1789	static void
..	..	@@ -1457,6 +1792,10 @@
1457	1792	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1458	1793	nv50_mstm_del(&nv_encoder->dp.mstm);
1459	1794	drm_encoder_cleanup(encoder);
	1795	+
	1796	+ if (nv_encoder->dcb->type == DCB_OUTPUT_DP)
	1797	+ mutex_destroy(&nv_encoder->dp.hpd_irq_lock);
	1798	+
1460	1799	kfree(encoder);
1461	1800	}
1462	1801
..	..	@@ -1465,17 +1804,25 @@
1465	1804	.destroy = nv50_sor_destroy,
1466	1805	};
1467	1806
	1807	+static bool nv50_has_mst(struct nouveau_drm *drm)
	1808	+{
	1809	+ struct nvkm_bios *bios = nvxx_bios(&drm->client.device);
	1810	+ u32 data;
	1811	+ u8 ver, hdr, cnt, len;
	1812	+
	1813	+ data = nvbios_dp_table(bios, &ver, &hdr, &cnt, &len);
	1814	+ return data && ver >= 0x40 && (nvbios_rd08(bios, data + 0x08) & 0x04);
	1815	+}
	1816	+
1468	1817	static int
1469	1818	nv50_sor_create(struct drm_connector connector, struct dcb_output dcbe)
1470	1819	{
1471	1820	struct nouveau_connector *nv_connector = nouveau_connector(connector);
1472	1821	struct nouveau_drm *drm = nouveau_drm(connector->dev);
1473		- struct nvkm_bios *bios = nvxx_bios(&drm->client.device);
1474	1822	struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
1475	1823	struct nouveau_encoder *nv_encoder;
1476	1824	struct drm_encoder *encoder;
1477		- u8 ver, hdr, cnt, len;
1478		- u32 data;
	1825	+ struct nv50_disp *disp = nv50_disp(connector->dev);
1479	1826	int type, ret;
1480	1827
1481	1828	switch (dcbe->type) {
..	..	@@ -1502,10 +1849,14 @@
1502	1849
1503	1850	drm_connector_attach_encoder(connector, encoder);
1504	1851
	1852	+ disp->core->func->sor->get_caps(disp, nv_encoder, ffs(dcbe->or) - 1);
	1853	+
1505	1854	if (dcbe->type == DCB_OUTPUT_DP) {
1506		- struct nv50_disp *disp = nv50_disp(encoder->dev);
1507	1855	struct nvkm_i2c_aux *aux =
1508	1856	nvkm_i2c_aux_find(i2c, dcbe->i2c_index);
	1857	+
	1858	+ mutex_init(&nv_encoder->dp.hpd_irq_lock);
	1859	+
1509	1860	if (aux) {
1510	1861	if (disp->disp->object.oclass < GF110_DISP) {
1511	1862	/* HW has no support for address-only
..	..	@@ -1520,10 +1871,9 @@
1520	1871	}
1521	1872
1522	1873	if (nv_connector->type != DCB_CONNECTOR_eDP &&
1523		- (data = nvbios_dp_table(bios, &ver, &hdr, &cnt, &len)) &&
1524		- ver >= 0x40 && (nvbios_rd08(bios, data + 0x08) & 0x04)) {
1525		- ret = nv50_mstm_new(nv_encoder, &nv_connector->aux, 16,
1526		- nv_connector->base.base.id,
	1874	+ nv50_has_mst(drm)) {
	1875	+ ret = nv50_mstm_new(nv_encoder, &nv_connector->aux,
	1876	+ 16, nv_connector->base.base.id,
1527	1877	&nv_encoder->dp.mstm);
1528	1878	if (ret)
1529	1879	return ret;
..	..	@@ -1554,56 +1904,62 @@
1554	1904	}
1555	1905
1556	1906	static void
1557		-nv50_pior_disable(struct drm_encoder *encoder)
	1907	+nv50_pior_disable(struct drm_encoder encoder, struct drm_atomic_state state)
1558	1908	{
1559	1909	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1560	1910	struct nv50_core *core = nv50_disp(encoder->dev)->core;
	1911	+ const u32 ctrl = NVDEF(NV507D, PIOR_SET_CONTROL, OWNER, NONE);
1561	1912	if (nv_encoder->crtc)
1562		- core->func->pior->ctrl(core, nv_encoder->or, 0x00000000, NULL);
	1913	+ core->func->pior->ctrl(core, nv_encoder->or, ctrl, NULL);
1563	1914	nv_encoder->crtc = NULL;
1564	1915	nv50_outp_release(nv_encoder);
1565	1916	}
1566	1917
1567	1918	static void
1568		-nv50_pior_enable(struct drm_encoder *encoder)
	1919	+nv50_pior_enable(struct drm_encoder encoder, struct drm_atomic_state state)
1569	1920	{
1570	1921	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1571	1922	struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1572		- struct nouveau_connector *nv_connector;
1573	1923	struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state);
1574	1924	struct nv50_core *core = nv50_disp(encoder->dev)->core;
1575		- u8 owner = 1 << nv_crtc->index;
1576		- u8 proto;
	1925	+ u32 ctrl = 0;
1577	1926
1578		- nv50_outp_acquire(nv_encoder);
	1927	+ switch (nv_crtc->index) {
	1928	+ case 0: ctrl \|= NVDEF(NV507D, PIOR_SET_CONTROL, OWNER, HEAD0); break;
	1929	+ case 1: ctrl \|= NVDEF(NV507D, PIOR_SET_CONTROL, OWNER, HEAD1); break;
	1930	+ default:
	1931	+ WARN_ON(1);
	1932	+ break;
	1933	+ }
1579	1934
1580		- nv_connector = nouveau_encoder_connector_get(nv_encoder);
1581		- switch (nv_connector->base.display_info.bpc) {
1582		- case 10: asyh->or.depth = 0x6; break;
1583		- case 8: asyh->or.depth = 0x5; break;
1584		- case 6: asyh->or.depth = 0x2; break;
1585		- default: asyh->or.depth = 0x0; break;
	1935	+ nv50_outp_acquire(nv_encoder, false);
	1936	+
	1937	+ switch (asyh->or.bpc) {
	1938	+ case 10: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_30_444; break;
	1939	+ case 8: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_444; break;
	1940	+ case 6: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_18_444; break;
	1941	+ default: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_DEFAULT; break;
1586	1942	}
1587	1943
1588	1944	switch (nv_encoder->dcb->type) {
1589	1945	case DCB_OUTPUT_TMDS:
1590	1946	case DCB_OUTPUT_DP:
1591		- proto = 0x0;
	1947	+ ctrl \|= NVDEF(NV507D, PIOR_SET_CONTROL, PROTOCOL, EXT_TMDS_ENC);
1592	1948	break;
1593	1949	default:
1594	1950	BUG();
1595	1951	break;
1596	1952	}
1597	1953
1598		- core->func->pior->ctrl(core, nv_encoder->or, (proto << 8) \| owner, asyh);
1599		- nv_encoder->crtc = encoder->crtc;
	1954	+ core->func->pior->ctrl(core, nv_encoder->or, ctrl, asyh);
	1955	+ nv_encoder->crtc = &nv_crtc->base;
1600	1956	}
1601	1957
1602	1958	static const struct drm_encoder_helper_funcs
1603	1959	nv50_pior_help = {
1604	1960	.atomic_check = nv50_pior_atomic_check,
1605		- .enable = nv50_pior_enable,
1606		- .disable = nv50_pior_disable,
	1961	+ .atomic_enable = nv50_pior_enable,
	1962	+ .atomic_disable = nv50_pior_disable,
1607	1963	};
1608	1964
1609	1965	static void
..	..	@@ -1621,7 +1977,9 @@
1621	1977	static int
1622	1978	nv50_pior_create(struct drm_connector connector, struct dcb_output dcbe)
1623	1979	{
1624		- struct nouveau_drm *drm = nouveau_drm(connector->dev);
	1980	+ struct drm_device *dev = connector->dev;
	1981	+ struct nouveau_drm *drm = nouveau_drm(dev);
	1982	+ struct nv50_disp *disp = nv50_disp(dev);
1625	1983	struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
1626	1984	struct nvkm_i2c_bus *bus = NULL;
1627	1985	struct nvkm_i2c_aux *aux = NULL;
..	..	@@ -1660,6 +2018,9 @@
1660	2018	drm_encoder_helper_add(encoder, &nv50_pior_help);
1661	2019
1662	2020	drm_connector_attach_encoder(connector, encoder);
	2021	+
	2022	+ disp->core->func->pior->get_caps(disp, nv_encoder, ffs(dcbe->or) - 1);
	2023	+
1663	2024	return 0;
1664	2025	}
1665	2026
..	..	@@ -1728,14 +2089,18 @@
1728	2089	struct nouveau_drm *drm = nouveau_drm(dev);
1729	2090	struct nv50_disp *disp = nv50_disp(dev);
1730	2091	struct nv50_atom *atom = nv50_atom(state);
	2092	+ struct nv50_core *core = disp->core;
1731	2093	struct nv50_outp_atom outp, outt;
1732	2094	u32 interlock[NV50_DISP_INTERLOCK__SIZE] = {};
1733	2095	int i;
	2096	+ bool flushed = false;
1734	2097
1735	2098	NV_ATOMIC(drm, "commit %d %d\n", atom->lock_core, atom->flush_disable);
	2099	+ nv50_crc_atomic_stop_reporting(state);
1736	2100	drm_atomic_helper_wait_for_fences(dev, state, false);
1737	2101	drm_atomic_helper_wait_for_dependencies(state);
1738	2102	drm_atomic_helper_update_legacy_modeset_state(dev, state);
	2103	+ drm_atomic_helper_calc_timestamping_constants(state);
1739	2104
1740	2105	if (atom->lock_core)
1741	2106	mutex_lock(&disp->mutex);
..	..	@@ -1747,8 +2112,11 @@
1747	2112
1748	2113	NV_ATOMIC(drm, "%s: clr %04x (set %04x)\n", crtc->name,
1749	2114	asyh->clr.mask, asyh->set.mask);
1750		- if (old_crtc_state->active && !new_crtc_state->active)
	2115	+
	2116	+ if (old_crtc_state->active && !new_crtc_state->active) {
	2117	+ pm_runtime_put_noidle(dev->dev);
1751	2118	drm_crtc_vblank_off(crtc);
	2119	+ }
1752	2120
1753	2121	if (asyh->clr.mask) {
1754	2122	nv50_head_flush_clr(head, asyh, atom->flush_disable);
..	..	@@ -1781,12 +2149,14 @@
1781	2149	outp->clr.mask, outp->set.mask);
1782	2150
1783	2151	if (outp->clr.mask) {
1784		- help->disable(encoder);
	2152	+ help->atomic_disable(encoder, state);
1785	2153	interlock[NV50_DISP_INTERLOCK_CORE] \|= 1;
1786	2154	if (outp->flush_disable) {
1787	2155	nv50_disp_atomic_commit_wndw(state, interlock);
1788	2156	nv50_disp_atomic_commit_core(state, interlock);
1789	2157	memset(interlock, 0x00, sizeof(interlock));
	2158	+
	2159	+ flushed = true;
1790	2160	}
1791	2161	}
1792	2162	}
..	..	@@ -1797,8 +2167,14 @@
1797	2167	nv50_disp_atomic_commit_wndw(state, interlock);
1798	2168	nv50_disp_atomic_commit_core(state, interlock);
1799	2169	memset(interlock, 0x00, sizeof(interlock));
	2170	+
	2171	+ flushed = true;
1800	2172	}
1801	2173	}
	2174	+
	2175	+ if (flushed)
	2176	+ nv50_crc_atomic_release_notifier_contexts(state);
	2177	+ nv50_crc_atomic_init_notifier_contexts(state);
1802	2178
1803	2179	/* Update output path(s). */
1804	2180	list_for_each_entry_safe(outp, outt, &atom->outp, head) {
..	..	@@ -1812,7 +2188,7 @@
1812	2188	outp->set.mask, outp->clr.mask);
1813	2189
1814	2190	if (outp->set.mask) {
1815		- help->enable(encoder);
	2191	+ help->atomic_enable(encoder, state);
1816	2192	interlock[NV50_DISP_INTERLOCK_CORE] = 1;
1817	2193	}
1818	2194
..	..	@@ -1834,10 +2210,54 @@
1834	2210	}
1835	2211
1836	2212	if (new_crtc_state->active) {
1837		- if (!old_crtc_state->active)
	2213	+ if (!old_crtc_state->active) {
1838	2214	drm_crtc_vblank_on(crtc);
	2215	+ pm_runtime_get_noresume(dev->dev);
	2216	+ }
1839	2217	if (new_crtc_state->event)
1840	2218	drm_crtc_vblank_get(crtc);
	2219	+ }
	2220	+ }
	2221	+
	2222	+ /* Update window->head assignment.
	2223	+ *
	2224	+ * This has to happen in an update that's not interlocked with
	2225	+ * any window channels to avoid hitting HW error checks.
	2226	+ *
	2227	+ *TODO: Proper handling of window ownership (Turing apparently
	2228	+ * supports non-fixed mappings).
	2229	+ */
	2230	+ if (core->assign_windows) {
	2231	+ core->func->wndw.owner(core);
	2232	+ nv50_disp_atomic_commit_core(state, interlock);
	2233	+ core->assign_windows = false;
	2234	+ interlock[NV50_DISP_INTERLOCK_CORE] = 0;
	2235	+ }
	2236	+
	2237	+ /* Finish updating head(s)...
	2238	+ *
	2239	+ * NVD is rather picky about both where window assignments can change,
	2240	+ * and about certain core and window channel states matching.
	2241	+ *
	2242	+ * The EFI GOP driver on newer GPUs configures window channels with a
	2243	+ * different output format to what we do, and the core channel update
	2244	+ * in the assign_windows case above would result in a state mismatch.
	2245	+ *
	2246	+ * Delay some of the head update until after that point to workaround
	2247	+ * the issue. This only affects the initial modeset.
	2248	+ *
	2249	+ * TODO: handle this better when adding flexible window mapping
	2250	+ */
	2251	+ for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
	2252	+ struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);
	2253	+ struct nv50_head *head = nv50_head(crtc);
	2254	+
	2255	+ NV_ATOMIC(drm, "%s: set %04x (clr %04x)\n", crtc->name,
	2256	+ asyh->set.mask, asyh->clr.mask);
	2257	+
	2258	+ if (asyh->set.mask) {
	2259	+ nv50_head_flush_set_wndw(head, asyh);
	2260	+ interlock[NV50_DISP_INTERLOCK_CORE] = 1;
1841	2261	}
1842	2262	}
1843	2263
..	..	@@ -1896,10 +2316,17 @@
1896	2316	}
1897	2317	}
1898	2318
	2319	+ nv50_crc_atomic_start_reporting(state);
	2320	+ if (!flushed)
	2321	+ nv50_crc_atomic_release_notifier_contexts(state);
1899	2322	drm_atomic_helper_commit_hw_done(state);
1900	2323	drm_atomic_helper_cleanup_planes(dev, state);
1901	2324	drm_atomic_helper_commit_cleanup_done(state);
1902	2325	drm_atomic_state_put(state);
	2326	+
	2327	+ /* Drop the RPM ref we got from nv50_disp_atomic_commit() */
	2328	+ pm_runtime_mark_last_busy(dev->dev);
	2329	+ pm_runtime_put_autosuspend(dev->dev);
1903	2330	}
1904	2331
1905	2332	static void
..	..	@@ -1914,11 +2341,8 @@
1914	2341	nv50_disp_atomic_commit(struct drm_device *dev,
1915	2342	struct drm_atomic_state *state, bool nonblock)
1916	2343	{
1917		- struct nouveau_drm *drm = nouveau_drm(dev);
1918	2344	struct drm_plane_state *new_plane_state;
1919	2345	struct drm_plane *plane;
1920		- struct drm_crtc *crtc;
1921		- bool active = false;
1922	2346	int ret, i;
1923	2347
1924	2348	ret = pm_runtime_get_sync(dev->dev);
..	..	@@ -1957,26 +2381,16 @@
1957	2381
1958	2382	drm_atomic_state_get(state);
1959	2383
	2384	+ /*
	2385	+ * Grab another RPM ref for the commit tail, which will release the
	2386	+ * ref when it's finished
	2387	+ */
	2388	+ pm_runtime_get_noresume(dev->dev);
	2389	+
1960	2390	if (nonblock)
1961	2391	queue_work(system_unbound_wq, &state->commit_work);
1962	2392	else
1963	2393	nv50_disp_atomic_commit_tail(state);
1964		-
1965		- drm_for_each_crtc(crtc, dev) {
1966		- if (crtc->state->active) {
1967		- if (!drm->have_disp_power_ref) {
1968		- drm->have_disp_power_ref = true;
1969		- return 0;
1970		- }
1971		- active = true;
1972		- break;
1973		- }
1974		- }
1975		-
1976		- if (!active && drm->have_disp_power_ref) {
1977		- pm_runtime_put_autosuspend(dev->dev);
1978		- drm->have_disp_power_ref = false;
1979		- }
1980	2394
1981	2395	err_cleanup:
1982	2396	if (ret)
..	..	@@ -2064,11 +2478,27 @@
2064	2478	nv50_disp_atomic_check(struct drm_device dev, struct drm_atomic_state state)
2065	2479	{
2066	2480	struct nv50_atom *atom = nv50_atom(state);
	2481	+ struct nv50_core *core = nv50_disp(dev)->core;
2067	2482	struct drm_connector_state old_connector_state, new_connector_state;
2068	2483	struct drm_connector *connector;
2069	2484	struct drm_crtc_state *new_crtc_state;
2070	2485	struct drm_crtc *crtc;
	2486	+ struct nv50_head *head;
	2487	+ struct nv50_head_atom *asyh;
2071	2488	int ret, i;
	2489	+
	2490	+ if (core->assign_windows && core->func->head->static_wndw_map) {
	2491	+ drm_for_each_crtc(crtc, dev) {
	2492	+ new_crtc_state = drm_atomic_get_crtc_state(state,
	2493	+ crtc);
	2494	+ if (IS_ERR(new_crtc_state))
	2495	+ return PTR_ERR(new_crtc_state);
	2496	+
	2497	+ head = nv50_head(crtc);
	2498	+ asyh = nv50_head_atom(new_crtc_state);
	2499	+ core->func->head->static_wndw_map(head, asyh);
	2500	+ }
	2501	+ }
2072	2502
2073	2503	/* We need to handle colour management on a per-plane basis. */
2074	2504	for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
..	..	@@ -2092,6 +2522,12 @@
2092	2522	if (ret)
2093	2523	return ret;
2094	2524	}
	2525	+
	2526	+ ret = drm_dp_mst_atomic_check(state);
	2527	+ if (ret)
	2528	+ return ret;
	2529	+
	2530	+ nv50_crc_atomic_check_outp(atom);
2095	2531
2096	2532	return 0;
2097	2533	}
..	..	@@ -2146,60 +2582,50 @@
2146	2582	* Init
2147	2583	*****************************************************************************/
2148	2584
2149		-void
2150		-nv50_display_fini(struct drm_device *dev)
	2585	+static void
	2586	+nv50_display_fini(struct drm_device *dev, bool runtime, bool suspend)
2151	2587	{
2152		- struct nouveau_encoder *nv_encoder;
	2588	+ struct nouveau_drm *drm = nouveau_drm(dev);
2153	2589	struct drm_encoder *encoder;
2154		- struct drm_plane *plane;
2155		-
2156		- drm_for_each_plane(plane, dev) {
2157		- struct nv50_wndw *wndw = nv50_wndw(plane);
2158		- if (plane->funcs != &nv50_wndw)
2159		- continue;
2160		- nv50_wndw_fini(wndw);
2161		- }
2162	2590
2163	2591	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2164		- if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
2165		- nv_encoder = nouveau_encoder(encoder);
2166		- nv50_mstm_fini(nv_encoder->dp.mstm);
2167		- }
	2592	+ if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST)
	2593	+ nv50_mstm_fini(nouveau_encoder(encoder));
2168	2594	}
	2595	+
	2596	+ if (!runtime)
	2597	+ cancel_work_sync(&drm->hpd_work);
2169	2598	}
2170	2599
2171		-int
2172		-nv50_display_init(struct drm_device *dev)
	2600	+static int
	2601	+nv50_display_init(struct drm_device *dev, bool resume, bool runtime)
2173	2602	{
2174	2603	struct nv50_core *core = nv50_disp(dev)->core;
2175	2604	struct drm_encoder *encoder;
2176		- struct drm_plane *plane;
2177	2605
2178		- core->func->init(core);
	2606	+ if (resume \|\| runtime)
	2607	+ core->func->init(core);
2179	2608
2180	2609	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2181	2610	if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
2182	2611	struct nouveau_encoder *nv_encoder =
2183	2612	nouveau_encoder(encoder);
2184		- nv50_mstm_init(nv_encoder->dp.mstm);
	2613	+ nv50_mstm_init(nv_encoder, runtime);
2185	2614	}
2186		- }
2187		-
2188		- drm_for_each_plane(plane, dev) {
2189		- struct nv50_wndw *wndw = nv50_wndw(plane);
2190		- if (plane->funcs != &nv50_wndw)
2191		- continue;
2192		- nv50_wndw_init(wndw);
2193	2615	}
2194	2616
2195	2617	return 0;
2196	2618	}
2197	2619
2198		-void
	2620	+static void
2199	2621	nv50_display_destroy(struct drm_device *dev)
2200	2622	{
2201	2623	struct nv50_disp *disp = nv50_disp(dev);
2202	2624
	2625	+ nv50_audio_component_fini(nouveau_drm(dev));
	2626	+
	2627	+ nvif_object_unmap(&disp->caps);
	2628	+ nvif_object_dtor(&disp->caps);
2203	2629	nv50_core_del(&disp->core);
2204	2630
2205	2631	nouveau_bo_unmap(disp->sync);
..	..	@@ -2221,6 +2647,7 @@
2221	2647	struct nv50_disp *disp;
2222	2648	struct dcb_output *dcbe;
2223	2649	int crtcs, ret, i;
	2650	+ bool has_mst = nv50_has_mst(drm);
2224	2651
2225	2652	disp = kzalloc(sizeof(*disp), GFP_KERNEL);
2226	2653	if (!disp)
..	..	@@ -2234,13 +2661,15 @@
2234	2661	nouveau_display(dev)->fini = nv50_display_fini;
2235	2662	disp->disp = &nouveau_display(dev)->disp;
2236	2663	dev->mode_config.funcs = &nv50_disp_func;
2237		- dev->driver->driver_features \|= DRIVER_PREFER_XBGR_30BPP;
	2664	+ dev->mode_config.quirk_addfb_prefer_xbgr_30bpp = true;
	2665	+ dev->mode_config.normalize_zpos = true;
2238	2666
2239	2667	/* small shared memory area we use for notifiers and semaphores */
2240		- ret = nouveau_bo_new(&drm->client, 4096, 0x1000, TTM_PL_FLAG_VRAM,
	2668	+ ret = nouveau_bo_new(&drm->client, 4096, 0x1000,
	2669	+ NOUVEAU_GEM_DOMAIN_VRAM,
2241	2670	0, 0x0000, NULL, NULL, &disp->sync);
2242	2671	if (!ret) {
2243		- ret = nouveau_bo_pin(disp->sync, TTM_PL_FLAG_VRAM, true);
	2672	+ ret = nouveau_bo_pin(disp->sync, NOUVEAU_GEM_DOMAIN_VRAM, true);
2244	2673	if (!ret) {
2245	2674	ret = nouveau_bo_map(disp->sync);
2246	2675	if (ret)
..	..	@@ -2258,6 +2687,22 @@
2258	2687	if (ret)
2259	2688	goto out;
2260	2689
	2690	+ disp->core->func->init(disp->core);
	2691	+ if (disp->core->func->caps_init) {
	2692	+ ret = disp->core->func->caps_init(drm, disp);
	2693	+ if (ret)
	2694	+ goto out;
	2695	+ }
	2696	+
	2697	+ /* Assign the correct format modifiers */
	2698	+ if (disp->disp->object.oclass >= TU102_DISP)
	2699	+ nouveau_display(dev)->format_modifiers = wndwc57e_modifiers;
	2700	+ else
	2701	+ if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_FERMI)
	2702	+ nouveau_display(dev)->format_modifiers = disp90xx_modifiers;
	2703	+ else
	2704	+ nouveau_display(dev)->format_modifiers = disp50xx_modifiers;
	2705	+
2261	2706	/* create crtc objects to represent the hw heads */
2262	2707	if (disp->disp->object.oclass >= GV100_DISP)
2263	2708	crtcs = nvif_rd32(&device->object, 0x610060) & 0xff;
..	..	@@ -2268,16 +2713,42 @@
2268	2713	crtcs = 0x3;
2269	2714
2270	2715	for (i = 0; i < fls(crtcs); i++) {
	2716	+ struct nv50_head *head;
	2717	+
2271	2718	if (!(crtcs & (1 << i)))
2272	2719	continue;
2273		- ret = nv50_head_create(dev, i);
2274		- if (ret)
	2720	+
	2721	+ head = nv50_head_create(dev, i);
	2722	+ if (IS_ERR(head)) {
	2723	+ ret = PTR_ERR(head);
2275	2724	goto out;
	2725	+ }
	2726	+
	2727	+ if (has_mst) {
	2728	+ head->msto = nv50_msto_new(dev, head, i);
	2729	+ if (IS_ERR(head->msto)) {
	2730	+ ret = PTR_ERR(head->msto);
	2731	+ head->msto = NULL;
	2732	+ goto out;
	2733	+ }
	2734	+
	2735	+ /*
	2736	+ * FIXME: This is a hack to workaround the following
	2737	+ * issues:
	2738	+ *
	2739	+ * https://gitlab.gnome.org/GNOME/mutter/issues/759
	2740	+ * https://gitlab.freedesktop.org/xorg/xserver/merge_requests/277
	2741	+ *
	2742	+ * Once these issues are closed, this should be
	2743	+ * removed
	2744	+ */
	2745	+ head->msto->encoder.possible_crtcs = crtcs;
	2746	+ }
2276	2747	}
2277	2748
2278	2749	/* create encoder/connector objects based on VBIOS DCB table */
2279	2750	for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) {
2280		- connector = nouveau_connector_create(dev, dcbe->connector);
	2751	+ connector = nouveau_connector_create(dev, dcbe);
2281	2752	if (IS_ERR(connector))
2282	2753	continue;
2283	2754
..	..	@@ -2309,7 +2780,7 @@
2309	2780
2310	2781	/* cull any connectors we created that don't have an encoder */
2311	2782	list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) {
2312		- if (connector->encoder_ids[0])
	2783	+ if (connector->possible_encoders)
2313	2784	continue;
2314	2785
2315	2786	NV_WARN(drm, "%s has no encoders, removing\n",
..	..	@@ -2320,8 +2791,60 @@
2320	2791	/* Disable vblank irqs aggressively for power-saving, safe on nv50+ */
2321	2792	dev->vblank_disable_immediate = true;
2322	2793
	2794	+ nv50_audio_component_init(drm);
	2795	+
2323	2796	out:
2324	2797	if (ret)
2325	2798	nv50_display_destroy(dev);
2326	2799	return ret;
2327	2800	}
	2801	+
	2802	+/******************************************************************************
	2803	+ * Format modifiers
	2804	+ *****************************************************************************/
	2805	+
	2806	+/****************************************************************
	2807	+ * Log2(block height) ----------------------------+ *
	2808	+ * Page Kind ----------------------------------+ \| *
	2809	+ * Gob Height/Page Kind Generation ------+ \| \| *
	2810	+ * Sector layout -------+ \| \| \| *
	2811	+ * Compression ------+ \| \| \| \| */
	2812	+const u64 disp50xx_modifiers[] = { /* \| \| \| \| \| */
	2813	+ DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 0),
	2814	+ DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 1),
	2815	+ DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 2),
	2816	+ DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 3),
	2817	+ DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 4),
	2818	+ DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 5),
	2819	+ DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 0),
	2820	+ DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 1),
	2821	+ DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 2),
	2822	+ DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 3),
	2823	+ DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 4),
	2824	+ DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 5),
	2825	+ DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 0),
	2826	+ DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 1),
	2827	+ DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 2),
	2828	+ DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 3),
	2829	+ DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 4),
	2830	+ DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 5),
	2831	+ DRM_FORMAT_MOD_LINEAR,
	2832	+ DRM_FORMAT_MOD_INVALID
	2833	+};
	2834	+
	2835	+/****************************************************************
	2836	+ * Log2(block height) ----------------------------+ *
	2837	+ * Page Kind ----------------------------------+ \| *
	2838	+ * Gob Height/Page Kind Generation ------+ \| \| *
	2839	+ * Sector layout -------+ \| \| \| *
	2840	+ * Compression ------+ \| \| \| \| */
	2841	+const u64 disp90xx_modifiers[] = { /* \| \| \| \| \| */
	2842	+ DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 0),
	2843	+ DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 1),
	2844	+ DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 2),
	2845	+ DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 3),
	2846	+ DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 4),
	2847	+ DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 5),
	2848	+ DRM_FORMAT_MOD_LINEAR,
	2849	+ DRM_FORMAT_MOD_INVALID
	2850	+};