~hc/RK356X_SDK_RELEASE.git

..	..	@@ -1,12 +1,10 @@
	1	+// SPDX-License-Identifier: GPL-2.0-only
1	2	/*
2	3	* GHES/EDAC Linux driver
3	4	*
4		- * This file may be distributed under the terms of the GNU General Public
5		- * License version 2.
6		- *
7	5	* Copyright (c) 2013 by Mauro Carvalho Chehab
8	6	*
9		- * Red Hat Inc. http://www.redhat.com
	7	+ * Red Hat Inc. https://www.redhat.com
10	8	*/
11	9
12	10	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
..	..	@@ -17,19 +15,34 @@
17	15	#include "edac_module.h"
18	16	#include <ras/ras_event.h>
19	17
20		-struct ghes_edac_pvt {
21		- struct list_head list;
22		- struct ghes *ghes;
	18	+struct ghes_pvt {
23	19	struct mem_ctl_info *mci;
24	20
25	21	/* Buffers for the error handling routine */
26		- char detail_location[240];
27		- char other_detail[160];
	22	+ char other_detail[400];
28	23	char msg[80];
29	24	};
30	25
31		-static atomic_t ghes_init = ATOMIC_INIT(0);
32		-static struct ghes_edac_pvt *ghes_pvt;
	26	+static refcount_t ghes_refcount = REFCOUNT_INIT(0);
	27	+
	28	+/*
	29	+ * Access to ghes_pvt must be protected by ghes_lock. The spinlock
	30	+ * also provides the necessary (implicit) memory barrier for the SMP
	31	+ * case to make the pointer visible on another CPU.
	32	+ */
	33	+static struct ghes_pvt *ghes_pvt;
	34	+
	35	+/*
	36	+ * This driver's representation of the system hardware, as collected
	37	+ * from DMI.
	38	+ */
	39	+struct ghes_hw_desc {
	40	+ int num_dimms;
	41	+ struct dimm_info *dimms;
	42	+} ghes_hw;
	43	+
	44	+/* GHES registration mutex */
	45	+static DEFINE_MUTEX(ghes_reg_mutex);
33	46
34	47	/*
35	48	* Sync with other, potentially concurrent callers of
..	..	@@ -41,6 +54,8 @@
41	54	/* "ghes_edac.force_load=1" skips the platform check */
42	55	static bool __read_mostly force_load;
43	56	module_param(force_load, bool, 0);
	57	+
	58	+static bool system_scanned;
44	59
45	60	/* Memory Device - Type 17 of SMBIOS spec */
46	61	struct memdev_dmi_entry {
..	..	@@ -68,131 +83,170 @@
68	83	u16 conf_mem_clk_speed;
69	84	} __attribute__((__packed__));
70	85
71		-struct ghes_edac_dimm_fill {
72		- struct mem_ctl_info *mci;
73		- unsigned count;
74		-};
75		-
76		-static void ghes_edac_count_dimms(const struct dmi_header dh, void arg)
	86	+static struct dimm_info find_dimm_by_handle(struct mem_ctl_info mci, u16 handle)
77	87	{
78		- int *num_dimm = arg;
	88	+ struct dimm_info *dimm;
79	89
80		- if (dh->type == DMI_ENTRY_MEM_DEVICE)
81		- (*num_dimm)++;
	90	+ mci_for_each_dimm(mci, dimm) {
	91	+ if (dimm->smbios_handle == handle)
	92	+ return dimm;
	93	+ }
	94	+
	95	+ return NULL;
82	96	}
83	97
84		-static void ghes_edac_dmidecode(const struct dmi_header dh, void arg)
	98	+static void dimm_setup_label(struct dimm_info *dimm, u16 handle)
85	99	{
86		- struct ghes_edac_dimm_fill *dimm_fill = arg;
87		- struct mem_ctl_info *mci = dimm_fill->mci;
	100	+ const char bank = NULL, device = NULL;
88	101
89		- if (dh->type == DMI_ENTRY_MEM_DEVICE) {
90		- struct memdev_dmi_entry entry = (struct memdev_dmi_entry )dh;
91		- struct dimm_info *dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms,
92		- mci->n_layers,
93		- dimm_fill->count, 0, 0);
94		- u16 rdr_mask = BIT(7) \| BIT(13);
	102	+ dmi_memdev_name(handle, &bank, &device);
95	103
96		- if (entry->size == 0xffff) {
97		- pr_info("Can't get DIMM%i size\n",
98		- dimm_fill->count);
99		- dimm->nr_pages = MiB_TO_PAGES(32);/* Unknown */
100		- } else if (entry->size == 0x7fff) {
101		- dimm->nr_pages = MiB_TO_PAGES(entry->extended_size);
102		- } else {
103		- if (entry->size & BIT(15))
104		- dimm->nr_pages = MiB_TO_PAGES((entry->size & 0x7fff) << 10);
105		- else
106		- dimm->nr_pages = MiB_TO_PAGES(entry->size);
107		- }
	104	+ /*
	105	+ * Set to a NULL string when both bank and device are zero. In this case,
	106	+ * the label assigned by default will be preserved.
	107	+ */
	108	+ snprintf(dimm->label, sizeof(dimm->label), "%s%s%s",
	109	+ (bank && *bank) ? bank : "",
	110	+ (bank && bank && device && device) ? " " : "",
	111	+ (device && *device) ? device : "");
	112	+}
108	113
109		- switch (entry->memory_type) {
110		- case 0x12:
111		- if (entry->type_detail & BIT(13))
112		- dimm->mtype = MEM_RDDR;
113		- else
114		- dimm->mtype = MEM_DDR;
115		- break;
116		- case 0x13:
117		- if (entry->type_detail & BIT(13))
118		- dimm->mtype = MEM_RDDR2;
119		- else
120		- dimm->mtype = MEM_DDR2;
121		- break;
122		- case 0x14:
123		- dimm->mtype = MEM_FB_DDR2;
124		- break;
125		- case 0x18:
126		- if (entry->type_detail & BIT(12))
127		- dimm->mtype = MEM_NVDIMM;
128		- else if (entry->type_detail & BIT(13))
129		- dimm->mtype = MEM_RDDR3;
130		- else
131		- dimm->mtype = MEM_DDR3;
132		- break;
133		- case 0x1a:
134		- if (entry->type_detail & BIT(12))
135		- dimm->mtype = MEM_NVDIMM;
136		- else if (entry->type_detail & BIT(13))
137		- dimm->mtype = MEM_RDDR4;
138		- else
139		- dimm->mtype = MEM_DDR4;
140		- break;
141		- default:
142		- if (entry->type_detail & BIT(6))
143		- dimm->mtype = MEM_RMBS;
144		- else if ((entry->type_detail & rdr_mask) == rdr_mask)
145		- dimm->mtype = MEM_RDR;
146		- else if (entry->type_detail & BIT(7))
147		- dimm->mtype = MEM_SDR;
148		- else if (entry->type_detail & BIT(9))
149		- dimm->mtype = MEM_EDO;
150		- else
151		- dimm->mtype = MEM_UNKNOWN;
152		- }
	114	+static void assign_dmi_dimm_info(struct dimm_info dimm, struct memdev_dmi_entry entry)
	115	+{
	116	+ u16 rdr_mask = BIT(7) \| BIT(13);
153	117
154		- /*
155		- * Actually, we can only detect if the memory has bits for
156		- * checksum or not
157		- */
158		- if (entry->total_width == entry->data_width)
159		- dimm->edac_mode = EDAC_NONE;
	118	+ if (entry->size == 0xffff) {
	119	+ pr_info("Can't get DIMM%i size\n", dimm->idx);
	120	+ dimm->nr_pages = MiB_TO_PAGES(32);/* Unknown */
	121	+ } else if (entry->size == 0x7fff) {
	122	+ dimm->nr_pages = MiB_TO_PAGES(entry->extended_size);
	123	+ } else {
	124	+ if (entry->size & BIT(15))
	125	+ dimm->nr_pages = MiB_TO_PAGES((entry->size & 0x7fff) << 10);
160	126	else
161		- dimm->edac_mode = EDAC_SECDED;
	127	+ dimm->nr_pages = MiB_TO_PAGES(entry->size);
	128	+ }
162	129
163		- dimm->dtype = DEV_UNKNOWN;
164		- dimm->grain = 128; /* Likely, worse case */
	130	+ switch (entry->memory_type) {
	131	+ case 0x12:
	132	+ if (entry->type_detail & BIT(13))
	133	+ dimm->mtype = MEM_RDDR;
	134	+ else
	135	+ dimm->mtype = MEM_DDR;
	136	+ break;
	137	+ case 0x13:
	138	+ if (entry->type_detail & BIT(13))
	139	+ dimm->mtype = MEM_RDDR2;
	140	+ else
	141	+ dimm->mtype = MEM_DDR2;
	142	+ break;
	143	+ case 0x14:
	144	+ dimm->mtype = MEM_FB_DDR2;
	145	+ break;
	146	+ case 0x18:
	147	+ if (entry->type_detail & BIT(12))
	148	+ dimm->mtype = MEM_NVDIMM;
	149	+ else if (entry->type_detail & BIT(13))
	150	+ dimm->mtype = MEM_RDDR3;
	151	+ else
	152	+ dimm->mtype = MEM_DDR3;
	153	+ break;
	154	+ case 0x1a:
	155	+ if (entry->type_detail & BIT(12))
	156	+ dimm->mtype = MEM_NVDIMM;
	157	+ else if (entry->type_detail & BIT(13))
	158	+ dimm->mtype = MEM_RDDR4;
	159	+ else
	160	+ dimm->mtype = MEM_DDR4;
	161	+ break;
	162	+ default:
	163	+ if (entry->type_detail & BIT(6))
	164	+ dimm->mtype = MEM_RMBS;
	165	+ else if ((entry->type_detail & rdr_mask) == rdr_mask)
	166	+ dimm->mtype = MEM_RDR;
	167	+ else if (entry->type_detail & BIT(7))
	168	+ dimm->mtype = MEM_SDR;
	169	+ else if (entry->type_detail & BIT(9))
	170	+ dimm->mtype = MEM_EDO;
	171	+ else
	172	+ dimm->mtype = MEM_UNKNOWN;
	173	+ }
165	174
166		- /*
167		- * FIXME: It shouldn't be hard to also fill the DIMM labels
168		- */
	175	+ /*
	176	+ * Actually, we can only detect if the memory has bits for
	177	+ * checksum or not
	178	+ */
	179	+ if (entry->total_width == entry->data_width)
	180	+ dimm->edac_mode = EDAC_NONE;
	181	+ else
	182	+ dimm->edac_mode = EDAC_SECDED;
169	183
170		- if (dimm->nr_pages) {
171		- edac_dbg(1, "DIMM%i: %s size = %d MB%s\n",
172		- dimm_fill->count, edac_mem_types[dimm->mtype],
173		- PAGES_TO_MiB(dimm->nr_pages),
174		- (dimm->edac_mode != EDAC_NONE) ? "(ECC)" : "");
175		- edac_dbg(2, "\ttype %d, detail 0x%02x, width %d(total %d)\n",
176		- entry->memory_type, entry->type_detail,
177		- entry->total_width, entry->data_width);
	184	+ dimm->dtype = DEV_UNKNOWN;
	185	+ dimm->grain = 128; /* Likely, worse case */
	186	+
	187	+ dimm_setup_label(dimm, entry->handle);
	188	+
	189	+ if (dimm->nr_pages) {
	190	+ edac_dbg(1, "DIMM%i: %s size = %d MB%s\n",
	191	+ dimm->idx, edac_mem_types[dimm->mtype],
	192	+ PAGES_TO_MiB(dimm->nr_pages),
	193	+ (dimm->edac_mode != EDAC_NONE) ? "(ECC)" : "");
	194	+ edac_dbg(2, "\ttype %d, detail 0x%02x, width %d(total %d)\n",
	195	+ entry->memory_type, entry->type_detail,
	196	+ entry->total_width, entry->data_width);
	197	+ }
	198	+
	199	+ dimm->smbios_handle = entry->handle;
	200	+}
	201	+
	202	+static void enumerate_dimms(const struct dmi_header dh, void arg)
	203	+{
	204	+ struct memdev_dmi_entry entry = (struct memdev_dmi_entry )dh;
	205	+ struct ghes_hw_desc hw = (struct ghes_hw_desc )arg;
	206	+ struct dimm_info *d;
	207	+
	208	+ if (dh->type != DMI_ENTRY_MEM_DEVICE)
	209	+ return;
	210	+
	211	+ /* Enlarge the array with additional 16 */
	212	+ if (!hw->num_dimms \|\| !(hw->num_dimms % 16)) {
	213	+ struct dimm_info *new;
	214	+
	215	+ new = krealloc(hw->dimms, (hw->num_dimms + 16) * sizeof(struct dimm_info),
	216	+ GFP_KERNEL);
	217	+ if (!new) {
	218	+ WARN_ON_ONCE(1);
	219	+ return;
178	220	}
179	221
180		- dimm_fill->count++;
	222	+ hw->dimms = new;
181	223	}
	224	+
	225	+ d = &hw->dimms[hw->num_dimms];
	226	+ d->idx = hw->num_dimms;
	227	+
	228	+ assign_dmi_dimm_info(d, entry);
	229	+
	230	+ hw->num_dimms++;
	231	+}
	232	+
	233	+static void ghes_scan_system(void)
	234	+{
	235	+ if (system_scanned)
	236	+ return;
	237	+
	238	+ dmi_walk(enumerate_dimms, &ghes_hw);
	239	+
	240	+ system_scanned = true;
182	241	}
183	242
184	243	void ghes_edac_report_mem_error(int sev, struct cper_sec_mem_err *mem_err)
185	244	{
186		- enum hw_event_mc_err_type type;
187	245	struct edac_raw_error_desc *e;
188	246	struct mem_ctl_info *mci;
189		- struct ghes_edac_pvt *pvt = ghes_pvt;
	247	+ struct ghes_pvt *pvt;
190	248	unsigned long flags;
191	249	char *p;
192		- u8 grain_bits;
193		-
194		- if (!pvt)
195		- return;
196	250
197	251	/*
198	252	* We can do the locking below because GHES defers error processing
..	..	@@ -204,6 +258,10 @@
204	258
205	259	spin_lock_irqsave(&ghes_lock, flags);
206	260
	261	+ pvt = ghes_pvt;
	262	+ if (!pvt)
	263	+ goto unlock;
	264	+
207	265	mci = pvt->mci;
208	266	e = &mci->error_desc;
209	267
..	..	@@ -211,7 +269,6 @@
211	269	memset(e, 0, sizeof (*e));
212	270	e->error_count = 1;
213	271	e->grain = 1;
214		- strcpy(e->label, "unknown label");
215	272	e->msg = pvt->msg;
216	273	e->other_detail = pvt->other_detail;
217	274	e->top_layer = -1;
..	..	@@ -222,17 +279,17 @@
222	279
223	280	switch (sev) {
224	281	case GHES_SEV_CORRECTED:
225		- type = HW_EVENT_ERR_CORRECTED;
	282	+ e->type = HW_EVENT_ERR_CORRECTED;
226	283	break;
227	284	case GHES_SEV_RECOVERABLE:
228		- type = HW_EVENT_ERR_UNCORRECTED;
	285	+ e->type = HW_EVENT_ERR_UNCORRECTED;
229	286	break;
230	287	case GHES_SEV_PANIC:
231		- type = HW_EVENT_ERR_FATAL;
	288	+ e->type = HW_EVENT_ERR_FATAL;
232	289	break;
233	290	default:
234	291	case GHES_SEV_NO:
235		- type = HW_EVENT_ERR_INFO;
	292	+ e->type = HW_EVENT_ERR_INFO;
236	293	}
237	294
238	295	edac_dbg(1, "error validation_bits: 0x%08llx\n",
..	..	@@ -300,8 +357,8 @@
300	357
301	358	/* Error address */
302	359	if (mem_err->validation_bits & CPER_MEM_VALID_PA) {
303		- e->page_frame_number = mem_err->physical_addr >> PAGE_SHIFT;
304		- e->offset_in_page = mem_err->physical_addr & ~PAGE_MASK;
	360	+ e->page_frame_number = PHYS_PFN(mem_err->physical_addr);
	361	+ e->offset_in_page = offset_in_page(mem_err->physical_addr);
305	362	}
306	363
307	364	/* Error grain */
..	..	@@ -320,26 +377,52 @@
320	377	p += sprintf(p, "rank:%d ", mem_err->rank);
321	378	if (mem_err->validation_bits & CPER_MEM_VALID_BANK)
322	379	p += sprintf(p, "bank:%d ", mem_err->bank);
323		- if (mem_err->validation_bits & CPER_MEM_VALID_ROW)
324		- p += sprintf(p, "row:%d ", mem_err->row);
	380	+ if (mem_err->validation_bits & CPER_MEM_VALID_BANK_GROUP)
	381	+ p += sprintf(p, "bank_group:%d ",
	382	+ mem_err->bank >> CPER_MEM_BANK_GROUP_SHIFT);
	383	+ if (mem_err->validation_bits & CPER_MEM_VALID_BANK_ADDRESS)
	384	+ p += sprintf(p, "bank_address:%d ",
	385	+ mem_err->bank & CPER_MEM_BANK_ADDRESS_MASK);
	386	+ if (mem_err->validation_bits & (CPER_MEM_VALID_ROW \| CPER_MEM_VALID_ROW_EXT)) {
	387	+ u32 row = mem_err->row;
	388	+
	389	+ row \|= cper_get_mem_extension(mem_err->validation_bits, mem_err->extended);
	390	+ p += sprintf(p, "row:%d ", row);
	391	+ }
325	392	if (mem_err->validation_bits & CPER_MEM_VALID_COLUMN)
326	393	p += sprintf(p, "col:%d ", mem_err->column);
327	394	if (mem_err->validation_bits & CPER_MEM_VALID_BIT_POSITION)
328	395	p += sprintf(p, "bit_pos:%d ", mem_err->bit_pos);
329	396	if (mem_err->validation_bits & CPER_MEM_VALID_MODULE_HANDLE) {
330	397	const char bank = NULL, device = NULL;
	398	+ struct dimm_info *dimm;
	399	+
331	400	dmi_memdev_name(mem_err->mem_dev_handle, &bank, &device);
332	401	if (bank != NULL && device != NULL)
333	402	p += sprintf(p, "DIMM location:%s %s ", bank, device);
334	403	else
335	404	p += sprintf(p, "DIMM DMI handle: 0x%.4x ",
336	405	mem_err->mem_dev_handle);
	406	+
	407	+ dimm = find_dimm_by_handle(mci, mem_err->mem_dev_handle);
	408	+ if (dimm) {
	409	+ e->top_layer = dimm->idx;
	410	+ strcpy(e->label, dimm->label);
	411	+ }
337	412	}
	413	+ if (mem_err->validation_bits & CPER_MEM_VALID_CHIP_ID)
	414	+ p += sprintf(p, "chipID: %d ",
	415	+ mem_err->extended >> CPER_MEM_CHIP_ID_SHIFT);
338	416	if (p > e->location)
339	417	*(p - 1) = '\0';
340	418
	419	+ if (!*e->label)
	420	+ strcpy(e->label, "unknown memory");
	421	+
341	422	/* All other fields are mapped on e->other_detail */
342	423	p = pvt->other_detail;
	424	+ p += snprintf(p, sizeof(pvt->other_detail),
	425	+ "APEI location: %s ", e->location);
343	426	if (mem_err->validation_bits & CPER_MEM_VALID_ERROR_STATUS) {
344	427	u64 status = mem_err->error_status;
345	428
..	..	@@ -413,21 +496,9 @@
413	496	if (p > pvt->other_detail)
414	497	*(p - 1) = '\0';
415	498
416		- /* Sanity-check driver-supplied grain value. */
417		- if (WARN_ON_ONCE(!e->grain))
418		- e->grain = 1;
	499	+ edac_raw_mc_handle_error(e);
419	500
420		- grain_bits = fls_long(e->grain - 1);
421		-
422		- /* Generate the trace event */
423		- snprintf(pvt->detail_location, sizeof(pvt->detail_location),
424		- "APEI location: %s %s", e->location, e->other_detail);
425		- trace_mc_event(type, e->msg, e->label, e->error_count,
426		- mci->mc_idx, e->top_layer, e->mid_layer, e->low_layer,
427		- (e->page_frame_number << PAGE_SHIFT) \| e->offset_in_page,
428		- grain_bits, e->syndrome, pvt->detail_location);
429		-
430		- edac_raw_mc_handle_error(type, mci, e);
	501	+unlock:
431	502	spin_unlock_irqrestore(&ghes_lock, flags);
432	503	}
433	504
..	..	@@ -442,11 +513,12 @@
442	513	int ghes_edac_register(struct ghes ghes, struct device dev)
443	514	{
444	515	bool fake = false;
445		- int rc, num_dimm = 0;
446	516	struct mem_ctl_info *mci;
	517	+ struct ghes_pvt *pvt;
447	518	struct edac_mc_layer layers[1];
448		- struct ghes_edac_dimm_fill dimm_fill;
	519	+ unsigned long flags;
449	520	int idx = -1;
	521	+ int rc = 0;
450	522
451	523	if (IS_ENABLED(CONFIG_X86)) {
452	524	/* Check if safe to enable on this system */
..	..	@@ -454,37 +526,40 @@
454	526	if (!force_load && idx < 0)
455	527	return -ENODEV;
456	528	} else {
	529	+ force_load = true;
457	530	idx = 0;
458	531	}
	532	+
	533	+ /* finish another registration/unregistration instance first */
	534	+ mutex_lock(&ghes_reg_mutex);
459	535
460	536	/*
461	537	* We have only one logical memory controller to which all DIMMs belong.
462	538	*/
463		- if (atomic_inc_return(&ghes_init) > 1)
464		- return 0;
	539	+ if (refcount_inc_not_zero(&ghes_refcount))
	540	+ goto unlock;
465	541
466		- /* Get the number of DIMMs */
467		- dmi_walk(ghes_edac_count_dimms, &num_dimm);
	542	+ ghes_scan_system();
468	543
469	544	/* Check if we've got a bogus BIOS */
470		- if (num_dimm == 0) {
	545	+ if (!ghes_hw.num_dimms) {
471	546	fake = true;
472		- num_dimm = 1;
	547	+ ghes_hw.num_dimms = 1;
473	548	}
474	549
475	550	layers[0].type = EDAC_MC_LAYER_ALL_MEM;
476		- layers[0].size = num_dimm;
	551	+ layers[0].size = ghes_hw.num_dimms;
477	552	layers[0].is_virt_csrow = true;
478	553
479		- mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(struct ghes_edac_pvt));
	554	+ mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(struct ghes_pvt));
480	555	if (!mci) {
481	556	pr_info("Can't allocate memory for EDAC data\n");
482		- return -ENOMEM;
	557	+ rc = -ENOMEM;
	558	+ goto unlock;
483	559	}
484	560
485		- ghes_pvt = mci->pvt_info;
486		- ghes_pvt->ghes = ghes;
487		- ghes_pvt->mci = mci;
	561	+ pvt = mci->pvt_info;
	562	+ pvt->mci = mci;
488	563
489	564	mci->pdev = dev;
490	565	mci->mtype_cap = MEM_FLAG_EMPTY;
..	..	@@ -504,16 +579,36 @@
504	579	pr_info("So, the end result of using this driver varies from vendor to vendor.\n");
505	580	pr_info("If you find incorrect reports, please contact your hardware vendor\n");
506	581	pr_info("to correct its BIOS.\n");
507		- pr_info("This system has %d DIMM sockets.\n", num_dimm);
	582	+ pr_info("This system has %d DIMM sockets.\n", ghes_hw.num_dimms);
508	583	}
509	584
510	585	if (!fake) {
511		- dimm_fill.count = 0;
512		- dimm_fill.mci = mci;
513		- dmi_walk(ghes_edac_dmidecode, &dimm_fill);
	586	+ struct dimm_info src, dst;
	587	+ int i = 0;
	588	+
	589	+ mci_for_each_dimm(mci, dst) {
	590	+ src = &ghes_hw.dimms[i];
	591	+
	592	+ dst->idx = src->idx;
	593	+ dst->smbios_handle = src->smbios_handle;
	594	+ dst->nr_pages = src->nr_pages;
	595	+ dst->mtype = src->mtype;
	596	+ dst->edac_mode = src->edac_mode;
	597	+ dst->dtype = src->dtype;
	598	+ dst->grain = src->grain;
	599	+
	600	+ /*
	601	+ * If no src->label, preserve default label assigned
	602	+ * from EDAC core.
	603	+ */
	604	+ if (strlen(src->label))
	605	+ memcpy(dst->label, src->label, sizeof(src->label));
	606	+
	607	+ i++;
	608	+ }
	609	+
514	610	} else {
515		- struct dimm_info *dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms,
516		- mci->n_layers, 0, 0, 0);
	611	+ struct dimm_info *dimm = edac_get_dimm(mci, 0, 0, 0);
517	612
518	613	dimm->nr_pages = 1;
519	614	dimm->grain = 128;
..	..	@@ -524,25 +619,61 @@
524	619
525	620	rc = edac_mc_add_mc(mci);
526	621	if (rc < 0) {
527		- pr_info("Can't register at EDAC core\n");
	622	+ pr_info("Can't register with the EDAC core\n");
528	623	edac_mc_free(mci);
529		- return -ENODEV;
	624	+ rc = -ENODEV;
	625	+ goto unlock;
530	626	}
531		- return 0;
	627	+
	628	+ spin_lock_irqsave(&ghes_lock, flags);
	629	+ ghes_pvt = pvt;
	630	+ spin_unlock_irqrestore(&ghes_lock, flags);
	631	+
	632	+ /* only set on success */
	633	+ refcount_set(&ghes_refcount, 1);
	634	+
	635	+unlock:
	636	+
	637	+ /* Not needed anymore */
	638	+ kfree(ghes_hw.dimms);
	639	+ ghes_hw.dimms = NULL;
	640	+
	641	+ mutex_unlock(&ghes_reg_mutex);
	642	+
	643	+ return rc;
532	644	}
533	645
534	646	void ghes_edac_unregister(struct ghes *ghes)
535	647	{
536	648	struct mem_ctl_info *mci;
	649	+ unsigned long flags;
537	650
538		- if (!ghes_pvt)
	651	+ if (!force_load)
539	652	return;
540	653
541		- if (atomic_dec_return(&ghes_init))
542		- return;
	654	+ mutex_lock(&ghes_reg_mutex);
543	655
544		- mci = ghes_pvt->mci;
	656	+ system_scanned = false;
	657	+ memset(&ghes_hw, 0, sizeof(struct ghes_hw_desc));
	658	+
	659	+ if (!refcount_dec_and_test(&ghes_refcount))
	660	+ goto unlock;
	661	+
	662	+ /*
	663	+ * Wait for the irq handler being finished.
	664	+ */
	665	+ spin_lock_irqsave(&ghes_lock, flags);
	666	+ mci = ghes_pvt ? ghes_pvt->mci : NULL;
545	667	ghes_pvt = NULL;
546		- edac_mc_del_mc(mci->pdev);
547		- edac_mc_free(mci);
	668	+ spin_unlock_irqrestore(&ghes_lock, flags);
	669	+
	670	+ if (!mci)
	671	+ goto unlock;
	672	+
	673	+ mci = edac_mc_del_mc(mci->pdev);
	674	+ if (mci)
	675	+ edac_mc_free(mci);
	676	+
	677	+unlock:
	678	+ mutex_unlock(&ghes_reg_mutex);
548	679	}