default settings GPIO PA4 PA6 PA3 PB5

hc

2024-02-19 890e1df1bec891d9203724541e81f8fbe5183388

 kernel/arch/mips/include/asm/sn/intr.h
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@@ -8,15 +8,6 @@
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 #ifndef __ASM_SN_INTR_H
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 #define __ASM_SN_INTR_H
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-/* Number of interrupt levels associated with each interrupt register. */
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-#define N_INTPEND_BITS		64
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-
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-#define INT_PEND0_BASELVL	0
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-#define INT_PEND1_BASELVL	64
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-
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-#define N_INTPENDJUNK_BITS	8
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-#define INTPENDJUNK_CLRBIT	0x80
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-
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 /*
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  * Macros to manipulate the interrupt register on the calling hub chip.
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  */
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@@ -84,14 +75,6 @@
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 #define CPU_RESCHED_B_IRQ	 8
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 #define CPU_CALL_A_IRQ		 9
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 #define CPU_CALL_B_IRQ		10
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-#define MSC_MESG_INTR		11
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-#define BASE_PCI_IRQ		12
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-
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-/*
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- * INT_PEND0 again, bits determined by hardware / hardcoded:
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- */
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-#define SDISK_INTR		63	/* SABLE name */
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-#define IP_PEND0_6_63		63	/* What is this bit? */
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 /*
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  * INT_PEND1 hard-coded bits: