| .. | .. |
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| 1 | +// SPDX-License-Identifier: GPL-2.0-or-later |
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| 1 | 2 | /* |
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| 2 | 3 | * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru> |
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| 3 | | - * |
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| 4 | | - * The code contained herein is licensed under the GNU General Public |
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| 5 | | - * License. You may obtain a copy of the GNU General Public License |
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| 6 | | - * Version 2 or later at the following locations: |
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| 7 | | - * |
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| 8 | | - * http://www.opensource.org/licenses/gpl-license.html |
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| 9 | | - * http://www.gnu.org/copyleft/gpl.html |
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| 10 | 4 | */ |
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| 11 | 5 | |
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| 12 | 6 | /dts-v1/; |
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| .. | .. |
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| 37 | 31 | reg = <0>; |
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| 38 | 32 | interrupt-parent = <&gpio1>; |
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| 39 | 33 | interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; |
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| 40 | | - fsl,mc13xxx-uses-rtc; |
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| 41 | 34 | |
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| 42 | 35 | regulators { |
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| 43 | 36 | sw1_reg: sw1 { |
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| .. | .. |
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| 142 | 135 | pwgt2spi_reg: pwgt2spi { |
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| 143 | 136 | regulator-always-on; |
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| 144 | 137 | }; |
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| 145 | | - |
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| 146 | | - vcoincell_reg: vcoincell { |
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| 147 | | - regulator-min-microvolt = <3000000>; |
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| 148 | | - regulator-max-microvolt = <3000000>; |
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| 149 | | - regulator-always-on; |
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| 150 | | - }; |
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| 151 | 138 | }; |
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| 152 | 139 | }; |
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| 140 | +}; |
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| 141 | + |
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| 142 | +&esdhc1 { |
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| 143 | + pinctrl-names = "default"; |
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| 144 | + pinctrl-0 = <&pinctrl_esdhc1>; |
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| 145 | + max-frequency = <50000000>; |
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| 146 | + bus-width = <1>; |
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| 153 | 147 | }; |
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| 154 | 148 | |
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| 155 | 149 | &esdhc2 { |
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| .. | .. |
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| 174 | 168 | }; |
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| 175 | 169 | |
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| 176 | 170 | &i2c2 { |
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| 177 | | - pinctrl-names = "default"; |
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| 171 | + pinctrl-names = "default", "gpio"; |
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| 178 | 172 | pinctrl-0 = <&pinctrl_i2c2>; |
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| 173 | + pinctrl-1 = <&pinctrl_i2c2_gpio>; |
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| 179 | 174 | clock-frequency = <400000>; |
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| 175 | + scl-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; |
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| 176 | + sda-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; |
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| 180 | 177 | status = "okay"; |
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| 181 | 178 | |
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| 182 | 179 | mma7455l@1d { |
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| .. | .. |
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| 241 | 238 | >; |
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| 242 | 239 | }; |
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| 243 | 240 | |
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| 241 | + pinctrl_esdhc1: esdhc1grp { |
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| 242 | + fsl,pins = < |
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| 243 | + MX51_PAD_SD1_CLK__SD1_CLK 0x400021d5 |
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| 244 | + MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 |
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| 245 | + MX51_PAD_SD1_DATA0__SD1_DATA0 0x400020d5 |
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| 246 | + >; |
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| 247 | + }; |
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| 248 | + |
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| 244 | 249 | pinctrl_esdhc2: esdhc2grp { |
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| 245 | 250 | fsl,pins = < |
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| 246 | 251 | MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5 |
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| .. | .. |
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| 282 | 287 | >; |
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| 283 | 288 | }; |
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| 284 | 289 | |
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| 290 | + pinctrl_i2c2_gpio: i2c2gpiogrp { |
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| 291 | + fsl,pins = < |
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| 292 | + MX51_PAD_GPIO1_2__GPIO1_2 0x400001ed |
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| 293 | + MX51_PAD_GPIO1_3__GPIO1_3 0x400001ed |
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| 294 | + >; |
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| 295 | + }; |
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| 296 | + |
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| 285 | 297 | pinctrl_nfc: nfcgrp { |
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| 286 | 298 | fsl,pins = < |
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| 287 | 299 | MX51_PAD_NANDF_D0__NANDF_D0 0x80000000 |
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