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2023-11-23 7d07b3ae8ddad407913c5301877e694430a3263f

 kernel/drivers/video/rockchip/rga3/include/rga3_reg_info.h
..
..
@@ -4,451 +4,492 @@
4
4
 
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 #include "rga_drv.h"
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6
 
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-//General Registers
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-/* yqw: status和int寄存器尚不明了，无法进行修改。 */
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-//#define RGA2_STATUS			 0x00c
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-//#define RGA2_INT				 0x010
7
+/* sys reg */
8
+#define RGA3_SYS_CTRL				0x000
9
+#define RGA3_CMD_CTRL				0x004
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+#define RGA3_CMD_ADDR				0x008
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+#define RGA3_MI_GROUP_CTRL			0x00c
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+#define RGA3_ARQOS_CTRL				0x010
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+#define RGA3_VERSION_NUM			0x018
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+#define RGA3_VERSION_TIM			0x01c
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+#define RGA3_INT_EN				0x020
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+#define RGA3_INT_RAW				0x024
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+#define RGA3_INT_MSK				0x028
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+#define RGA3_INT_CLR				0x02c
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+#define RGA3_RO_SRST				0x030
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+#define RGA3_STATUS0				0x034
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+#define RGA3_SCAN_CNT				0x038
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+#define RGA3_CMD_STATE				0x040
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23
 
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-#define RGA3_SYS_CTRL			 0x000
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-#define RGA3_CMD_CTRL			 0x004
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-#define RGA3_CMD_ADDR			 0x008
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-#define RGA3_MI_GROUP_CTRL		0x00c
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-#define RGA3_ARQOS_CTRL		 0x010
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-#define RGA3_VERSION_NUM		 0x018
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-#define RGA3_VERSION_TIM		 0x01c
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-#define RGA3_INT_EN			 0x020
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-#define RGA3_INT_RAW			 0x024
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-#define RGA3_INT_MSK			 0x028
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-#define RGA3_INT_CLR			 0x02c
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-#define RGA3_RO_SRST			 0x030
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-#define RGA3_STATUS0			 0x034
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-#define RGA3_SCAN_CNT			 0x038
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-#define RGA3_STATUS1			 0x03c
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-#define RGA3_CMD_STATE			0x040
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+/* cmd reg */
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+#define RGA3_WIN0_RD_CTRL_OFFSET		0x000
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+#define RGA3_WIN0_Y_BASE_OFFSET			0x010
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+#define RGA3_WIN0_U_BASE_OFFSET			0x014
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+#define RGA3_WIN0_V_BASE_OFFSET			0x018
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+#define RGA3_WIN0_VIR_STRIDE_OFFSET		0x01c
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+#define RGA3_WIN0_FBC_OFF_OFFSET		0x020
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+#define RGA3_WIN0_SRC_SIZE_OFFSET		0x024
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+#define RGA3_WIN0_ACT_OFF_OFFSET		0x028
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+#define RGA3_WIN0_ACT_SIZE_OFFSET		0x02c
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+#define RGA3_WIN0_DST_SIZE_OFFSET		0x030
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+#define RGA3_WIN0_SCL_FAC_OFFSET		0x034
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+#define RGA3_WIN0_UV_VIR_STRIDE_OFFSET		0x038
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+#define RGA3_WIN1_RD_CTRL_OFFSET		0x040
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+#define RGA3_WIN1_Y_BASE_OFFSET			0x050
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+#define RGA3_WIN1_U_BASE_OFFSET			0x054
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+#define RGA3_WIN1_V_BASE_OFFSET			0x058
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+#define RGA3_WIN1_VIR_STRIDE_OFFSET		0x05c
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+#define RGA3_WIN1_FBC_OFF_OFFSET		0x060
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+#define RGA3_WIN1_SRC_SIZE_OFFSET		0x064
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+#define RGA3_WIN1_ACT_OFF_OFFSET		0x068
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+#define RGA3_WIN1_ACT_SIZE_OFFSET		0x06c
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+#define RGA3_WIN1_DST_SIZE_OFFSET		0x070
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+#define RGA3_WIN1_SCL_FAC_OFFSET		0x074
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+#define RGA3_WIN1_UV_VIR_STRIDE_OFFSET		0x078
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+#define RGA3_OVLP_CTRL_OFFSET			0x080
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+#define RGA3_OVLP_OFF_OFFSET			0x084
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+#define RGA3_OVLP_TOP_KEY_MIN_OFFSET		0x088
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+#define RGA3_OVLP_TOP_KEY_MAX_OFFSET		0x08c
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+#define RGA3_OVLP_TOP_CTRL_OFFSET		0x090
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+#define RGA3_OVLP_BOT_CTRL_OFFSET		0x094
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+#define RGA3_OVLP_TOP_ALPHA_OFFSET		0x098
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+#define RGA3_OVLP_BOT_ALPHA_OFFSET		0x09c
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+#define RGA3_WR_CTRL_OFFSET			0x0a0
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+#define RGA3_WR_FBCE_CTRL_OFFSET		0x0a4
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+#define RGA3_WR_VIR_STRIDE_OFFSET		0x0a8
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+#define RGA3_WR_PL_VIR_STRIDE_OFFSET		0x0ac
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+#define RGA3_WR_Y_BASE_OFFSET			0x0b0
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+#define RGA3_WR_U_BASE_OFFSET			0x0b4
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+#define RGA3_WR_V_BASE_OFFSET			0x0b8
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64
 
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-/* TODO: RGA_INT */
65
+/* RGA3_SYS_CTRL */
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+#define m_RGA3_SYS_CTRL_FRMEND_AUTO_RSTN_EN			(0x1 << 11)
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+#define m_RGA3_SYS_CTRL_RGA_BIC_MODE				(0x3 << 9)
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+#define m_RGA3_SYS_CTRL_RGA_RAM_CLK_ON				(0x1 << 8)
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+#define m_RGA3_SYS_CTRL_CCLK_SRESET				(0x1 << 4)
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+#define m_RGA3_SYS_CTRL_ACLK_SRESET				(0x1 << 3)
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+#define m_RGA3_SYS_CTRL_RGA_LGC_CLK_ON				(0x1 << 2)
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+#define m_RGA3_SYS_CTRL_CMD_MODE				(0x1 << 1)
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+#define m_RGA3_SYS_CTRL_RGA_SART				(0x1 << 0)
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+
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+#define s_RGA3_SYS_CTRL_RGA_BIC_MODE(x)				((x & 0x3) << 9)
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+#define s_RGA3_SYS_CTRL_CCLK_SRESET(x)				((x & 0x1) << 4)
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+#define s_RGA3_SYS_CTRL_ACLK_SRESET(x)				((x & 0x1) << 3)
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+#define s_RGA3_SYS_CTRL_CMD_MODE(x)				((x & 0x1) << 1)
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+
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+/* TODO: RGA3_INT_EN/RGA3_INT_RAW/RGA3_INT_MSK/RGA3_INT_CLR */
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+#define m_RGA3_INT_WIN1_VOR_FIFO_REN_ERR			(0x1 << 29)
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+#define m_RGA3_INT_WIN1_VOR_FIFO_WEN_ERR			(0x1 << 28)
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+#define m_RGA3_INT_WIN1_HOR_FIFO_REN_ERR			(0x1 << 27)
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+#define m_RGA3_INT_WIN1_HOR_FIFO_WEN_ERR			(0x1 << 26)
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+#define m_RGA3_INT_WIN1_IN_FIFO_REB_ERR				(0x1 << 25)
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+#define m_RGA3_INT_WIN1_IN_FIFO_WEN_ERR				(0x1 << 24)
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+#define m_RGA3_INT_WIN0_VOR_FIFO_REN_ERR			(0x1 << 21)
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+#define m_RGA3_INT_WIN0_VOR_FIFO_WEN_ERR			(0x1 << 20)
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+#define m_RGA3_INT_WIN0_HOR_FIFO_REN_ERR			(0x1 << 19)
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+#define m_RGA3_INT_WIN0_HOR_FIFO_WEN_ERR			(0x1 << 18)
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+#define m_RGA3_INT_WIN0_IN_FIFO_REB_ERR				(0x1 << 17)
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+#define m_RGA3_INT_WIN0_IN_FIFO_WEN_ERR				(0x1 << 16)
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+#define m_RGA3_INT_RGA_MI_WR_BUS_ERR				(0x1 << 15)
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+#define m_RGA3_INT_RGA_MI_WR_IN_HERR				(0x1 << 14)
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+//The signal is invalid, it will be pulled up every time, no need to care.
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+// #define m_RGA3_INT_RGA_MI_WR_IN_VERR				(0x1 << 13)
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+#define m_RGA3_INT_WIN1_V_ERR					(0x1 << 11)
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+#define m_RGA3_INT_WIN1_H_ERR					(0x1 << 10)
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+#define m_RGA3_INT_WIN1_FBCD_DEC_ERR				(0x1 << 9)
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+#define m_RGA3_INT_WIN1_RD_FRM_END				(0x1 << 8) //not error
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+#define m_RGA3_INT_WIN0_V_ERR					(0x1 << 7)
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+#define m_RGA3_INT_WIN0_H_ERR					(0x1 << 6)
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+#define m_RGA3_INT_WIN0_FBCD_DEC_ERR				(0x1 << 5)
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+#define m_RGA3_INT_WIN0_RD_FRM_END				(0x1 << 4) //not error
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+#define m_RGA3_INT_CMD_LINE_FINISH				(0x1 << 3) //not error
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+#define m_RGA3_INT_RAG_MI_RD_BUS_ERR				(0x1 << 2)
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+#define m_RGA3_INT_RGA_MMU_INTR					(0x1 << 1)
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+#define m_RGA3_INT_FRM_DONE					(0x1 << 0) //not error
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+
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+#define m_RGA3_INT_ERROR_MASK \
111
+	( \
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+		m_RGA3_INT_RGA_MMU_INTR | \
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+		m_RGA3_INT_RAG_MI_RD_BUS_ERR | \
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+		m_RGA3_INT_WIN0_FBCD_DEC_ERR | \
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+		m_RGA3_INT_WIN0_H_ERR | \
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+		m_RGA3_INT_WIN0_V_ERR | \
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+		m_RGA3_INT_WIN1_FBCD_DEC_ERR | \
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+		m_RGA3_INT_WIN1_H_ERR | \
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+		m_RGA3_INT_WIN1_V_ERR | \
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+		m_RGA3_INT_RGA_MI_WR_IN_HERR | \
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+		m_RGA3_INT_RGA_MI_WR_BUS_ERR | \
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+		m_RGA3_INT_WIN0_IN_FIFO_WEN_ERR | \
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+		m_RGA3_INT_WIN0_IN_FIFO_REB_ERR | \
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+		m_RGA3_INT_WIN0_HOR_FIFO_WEN_ERR | \
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+		m_RGA3_INT_WIN0_HOR_FIFO_REN_ERR| \
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+		m_RGA3_INT_WIN0_VOR_FIFO_WEN_ERR | \
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+		m_RGA3_INT_WIN0_VOR_FIFO_REN_ERR | \
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+		m_RGA3_INT_WIN1_IN_FIFO_WEN_ERR | \
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+		m_RGA3_INT_WIN1_IN_FIFO_REB_ERR | \
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+		m_RGA3_INT_WIN1_HOR_FIFO_WEN_ERR | \
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+		m_RGA3_INT_WIN1_HOR_FIFO_REN_ERR| \
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+		m_RGA3_INT_WIN1_VOR_FIFO_WEN_ERR | \
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+		m_RGA3_INT_WIN1_VOR_FIFO_REN_ERR \
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+	)
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+
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+/* RGA3_CMD_CTRL */
137
+#define m_RGA3_CMD_CTRL_CMD_INCR_NUM				(0x3ff << 3)
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+#define m_RGA3_CMD_CTRL_CMD_STOP_MODE				(0x1 << 2)
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+#define m_RGA3_CMD_CTRL_CMD_INCR_VALID_P			(0x1 << 1)
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+#define m_RGA3_CMD_CTRL_CMD_LINE_ST_P				(0x1 << 0)
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+
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+/* RGA3_RO_SRST */
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+#define m_RGA3_RO_SRST_RO_RST_DONE				(0x3f << 0)
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+
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+/* RGA3_CMD_STATE */
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+#define m_RGA3_CMD_STATE_CMD_CNT_CUR				(0xfff << 16)
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+#define m_RGA3_CMD_STATE_CMD_WORKING				(0x1 << 0)
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148
 
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 /* RGA3_WIN0_RD_CTRL */
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-#define m_RGA3_WIN0_RD_CTRL_SW_WIN0_ENABLE			 (0x1 << 0)
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-#define m_RGA3_WIN0_RD_CTRL_SW_WIN0_RD_MODE			 (0x3 << 1)
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-#define m_RGA3_WIN0_RD_CTRL_SW_WIN0_PIC_FORMAT		 (0xf << 4)
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-#define m_RGA3_WIN0_RD_CTRL_SW_WIN0_RD_FORMAT		 (0x3 << 8)
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-#define m_RGA3_WIN0_RD_CTRL_SW_WIN0_YUV10B_COMPACT	 (0x1 << 10)
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-#define m_RGA3_WIN0_RD_CTRL_SW_WIN0_ENDIAN_MODE		 (0x1 << 11)
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+#define m_RGA3_WIN0_RD_CTRL_SW_WIN0_ENABLE			(0x1 << 0)
151
+#define m_RGA3_WIN0_RD_CTRL_SW_WIN0_RD_MODE			(0x3 << 1)
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+#define m_RGA3_WIN0_RD_CTRL_SW_WIN0_PIC_FORMAT			(0xf << 4)
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+#define m_RGA3_WIN0_RD_CTRL_SW_WIN0_RD_FORMAT			(0x3 << 8)
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+#define m_RGA3_WIN0_RD_CTRL_SW_WIN0_YUV10B_COMPACT		(0x1 << 10)
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+#define m_RGA3_WIN0_RD_CTRL_SW_WIN0_ENDIAN_MODE			(0x1 << 11)
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156
 #define m_RGA3_WIN0_RD_CTRL_SW_WIN0_PIX_SWAP			(0x1 << 12)
39
-#define m_RGA3_WIN0_RD_CTRL_SW_WIN0_YC_SWAP			 (0x1 << 13)
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-#define m_RGA3_WIN0_RD_CTRL_SW_WIN0_ROT				 (0x1 << 16)
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-#define m_RGA3_WIN0_RD_CTRL_SW_WIN0_XMIRROR			 (0x1 << 17)
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-#define m_RGA3_WIN0_RD_CTRL_SW_WIN0_YMIRROR			 (0x1 << 18)
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-#define m_RGA3_WIN0_RD_CTRL_SW_WIN0_HOR_BY			 (0x1 << 20)
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-#define m_RGA3_WIN0_RD_CTRL_SW_WIN0_HOR_UP			 (0x1 << 21)
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-#define m_RGA3_WIN0_RD_CTRL_SW_WIN0_VER_BY			 (0x1 << 22)
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-#define m_RGA3_WIN0_RD_CTRL_SW_WIN0_VER_UP			 (0x1 << 23)
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-#define m_RGA3_WIN0_RD_CTRL_SW_WIN0_Y2R_EN			 (0x1 << 24)
48
-#define m_RGA3_WIN0_RD_CTRL_SW_WIN0_R2Y_EN			 (0x1 << 25)
157
+#define m_RGA3_WIN0_RD_CTRL_SW_WIN0_YC_SWAP			(0x1 << 13)
158
+#define m_RGA3_WIN0_RD_CTRL_SW_WIN0_ROT				(0x1 << 16)
159
+#define m_RGA3_WIN0_RD_CTRL_SW_WIN0_XMIRROR			(0x1 << 17)
160
+#define m_RGA3_WIN0_RD_CTRL_SW_WIN0_YMIRROR			(0x1 << 18)
161
+#define m_RGA3_WIN0_RD_CTRL_SW_WIN0_HOR_BY			(0x1 << 20)
162
+#define m_RGA3_WIN0_RD_CTRL_SW_WIN0_HOR_UP			(0x1 << 21)
163
+#define m_RGA3_WIN0_RD_CTRL_SW_WIN0_VER_BY			(0x1 << 22)
164
+#define m_RGA3_WIN0_RD_CTRL_SW_WIN0_VER_UP			(0x1 << 23)
165
+#define m_RGA3_WIN0_RD_CTRL_SW_WIN0_Y2R_EN			(0x1 << 24)
166
+#define m_RGA3_WIN0_RD_CTRL_SW_WIN0_R2Y_EN			(0x1 << 25)
49
167
 #define m_RGA3_WIN0_RD_CTRL_SW_WIN0_CSC_MODE			(0x3 << 26)
50
168
 #define m_RGA3_WIN0_RD_CTRL_SW_WIN0_PERF_OPT_DIS		(0x1 << 29)
51
169
 #define m_RGA3_WIN0_RD_CTRL_SW_WIN0_RD_ALIGN_DIS		(0x1 << 30)
52
170
 
53
-#define s_RGA3_WIN0_RD_CTRL_SW_WIN0_ENABLE(x)		 ((x & 0x1) << 0)
54
-#define s_RGA3_WIN0_RD_CTRL_SW_WIN0_RD_MODE(x)		 ((x & 0x3) << 1)
55
-#define s_RGA3_WIN0_RD_CTRL_SW_WIN0_PIC_FORMAT(x)	 ((x & 0xf) << 4)
171
+#define s_RGA3_WIN0_RD_CTRL_SW_WIN0_ENABLE(x)			((x & 0x1) << 0)
172
+#define s_RGA3_WIN0_RD_CTRL_SW_WIN0_RD_MODE(x)			((x & 0x3) << 1)
173
+#define s_RGA3_WIN0_RD_CTRL_SW_WIN0_PIC_FORMAT(x)		((x & 0xf) << 4)
56
174
 #define s_RGA3_WIN0_RD_CTRL_SW_WIN0_RD_FORMAT(x)		((x & 0x3) << 8)
57
-#define s_RGA3_WIN0_RD_CTRL_SW_WIN0_YUV10B_COMPACT(x) ((x & 0x1) << 10)
58
-#define s_RGA3_WIN0_RD_CTRL_SW_WIN0_ENDIAN_MODE(x)	 ((x & 0x1) << 11)
59
-#define s_RGA3_WIN0_RD_CTRL_SW_WIN0_PIX_SWAP(x)		 ((x & 0x1) << 12)
60
-#define s_RGA3_WIN0_RD_CTRL_SW_WIN0_YC_SWAP(x)		 ((x & 0x1) << 13)
61
-#define s_RGA3_WIN0_RD_CTRL_SW_WIN0_ROT(x)		((x & 0x1) << 16)
62
-#define s_RGA3_WIN0_RD_CTRL_SW_WIN0_XMIRROR(x)		 ((x & 0x1) << 17)
63
-#define s_RGA3_WIN0_RD_CTRL_SW_WIN0_YMIRROR(x)		 ((x & 0x1) << 18)
64
-#define s_RGA3_WIN0_RD_CTRL_SW_WIN0_HOR_BY(x)		 ((x & 0x1) << 20)
65
-#define s_RGA3_WIN0_RD_CTRL_SW_WIN0_HOR_UP(x)		 ((x & 0x1) << 21)
66
-#define s_RGA3_WIN0_RD_CTRL_SW_WIN0_VER_BY(x)		 ((x & 0x1) << 22)
67
-#define s_RGA3_WIN0_RD_CTRL_SW_WIN0_VER_UP(x)		 ((x & 0x1) << 23)
68
-#define s_RGA3_WIN0_RD_CTRL_SW_WIN0_Y2R_EN(x)		 ((x & 0x1) << 24)
69
-#define s_RGA3_WIN0_RD_CTRL_SW_WIN0_R2Y_EN(x)		 ((x & 0x1) << 25)
70
-#define s_RGA3_WIN0_RD_CTRL_SW_WIN0_CSC_MODE(x)		 ((x & 0x3) << 26)
71
-#define s_RGA3_WIN0_RD_CTRL_SW_WIN0_PERF_OPT_DIS(x)	 ((x & 0x1) << 29)
72
-#define s_RGA3_WIN0_RD_CTRL_SW_WIN0_RD_ALIGN_DIS(x)	 ((x & 0x1) << 30)
175
+#define s_RGA3_WIN0_RD_CTRL_SW_WIN0_YUV10B_COMPACT(x)		((x & 0x1) << 10)
176
+#define s_RGA3_WIN0_RD_CTRL_SW_WIN0_ENDIAN_MODE(x)		((x & 0x1) << 11)
177
+#define s_RGA3_WIN0_RD_CTRL_SW_WIN0_PIX_SWAP(x)			((x & 0x1) << 12)
178
+#define s_RGA3_WIN0_RD_CTRL_SW_WIN0_YC_SWAP(x)			((x & 0x1) << 13)
179
+#define s_RGA3_WIN0_RD_CTRL_SW_WIN0_ROT(x)			((x & 0x1) << 16)
180
+#define s_RGA3_WIN0_RD_CTRL_SW_WIN0_XMIRROR(x)			((x & 0x1) << 17)
181
+#define s_RGA3_WIN0_RD_CTRL_SW_WIN0_YMIRROR(x)			((x & 0x1) << 18)
182
+#define s_RGA3_WIN0_RD_CTRL_SW_WIN0_HOR_BY(x)			((x & 0x1) << 20)
183
+#define s_RGA3_WIN0_RD_CTRL_SW_WIN0_HOR_UP(x)			((x & 0x1) << 21)
184
+#define s_RGA3_WIN0_RD_CTRL_SW_WIN0_VER_BY(x)			((x & 0x1) << 22)
185
+#define s_RGA3_WIN0_RD_CTRL_SW_WIN0_VER_UP(x)			((x & 0x1) << 23)
186
+#define s_RGA3_WIN0_RD_CTRL_SW_WIN0_Y2R_EN(x)			((x & 0x1) << 24)
187
+#define s_RGA3_WIN0_RD_CTRL_SW_WIN0_R2Y_EN(x)			((x & 0x1) << 25)
188
+#define s_RGA3_WIN0_RD_CTRL_SW_WIN0_CSC_MODE(x)			((x & 0x3) << 26)
189
+#define s_RGA3_WIN0_RD_CTRL_SW_WIN0_PERF_OPT_DIS(x)		((x & 0x1) << 29)
190
+#define s_RGA3_WIN0_RD_CTRL_SW_WIN0_RD_ALIGN_DIS(x)		((x & 0x1) << 30)
73
191
 
74
192
 /* RGA3_WIN0_FBC_OFF */
75
193
 #define m_RGA3_WIN0_FBC_OFF_SW_WIN0_FBC_XOFF			(0x1fff << 0)
76
194
 #define m_RGA3_WIN0_FBC_OFF_SW_WIN0_FBC_YOFF			(0x1fff << 16)
77
195
 
78
-#define s_RGA3_WIN0_FBC_OFF_SW_WIN0_FBC_XOFF(x)		 ((x & 0x1fff) << 0)
79
-#define s_RGA3_WIN0_FBC_OFF_SW_WIN0_FBC_YOFF(x)		 ((x & 0x1fff) << 16)
196
+#define s_RGA3_WIN0_FBC_OFF_SW_WIN0_FBC_XOFF(x)			((x & 0x1fff) << 0)
197
+#define s_RGA3_WIN0_FBC_OFF_SW_WIN0_FBC_YOFF(x)			((x & 0x1fff) << 16)
80
198
 
81
199
 /* RGA3_WIN0_SRC_SIZE */
82
-#define m_RGA3_WIN0_SRC_SIZE_SW_WIN0_SRC_WIDTH		 (0x1fff << 0)
83
-#define m_RGA3_WIN0_SRC_SIZE_SW_WIN0_SRC_HEIGHT		 (0x1fff << 16)
200
+#define m_RGA3_WIN0_SRC_SIZE_SW_WIN0_SRC_WIDTH			(0x1fff << 0)
201
+#define m_RGA3_WIN0_SRC_SIZE_SW_WIN0_SRC_HEIGHT			(0x1fff << 16)
84
202
 
85
-#define s_RGA3_WIN0_SRC_OFF_SW_WIN0_SRC_WIDTH(x)	((x & 0x1fff) << 0)
86
-#define s_RGA3_WIN0_SRC_OFF_SW_WIN0_SRC_HEIGHT(x)	 ((x & 0x1fff) << 16)
203
+#define s_RGA3_WIN0_SRC_OFF_SW_WIN0_SRC_WIDTH(x)		((x & 0x1fff) << 0)
204
+#define s_RGA3_WIN0_SRC_OFF_SW_WIN0_SRC_HEIGHT(x)		((x & 0x1fff) << 16)
87
205
 
88
206
 /* RGA3_WIN0_ACT_OFF */
89
207
 #define m_RGA3_WIN0_ACT_OFF_SW_WIN0_ACT_XOFF			(0x1fff << 0)
90
208
 #define m_RGA3_WIN0_ACT_OFF_SW_WIN0_ACT_YOFF			(0x1fff << 16)
91
209
 
92
-#define s_RGA3_WIN0_ACT_OFF_SW_WIN0_ACT_XOFF(x)		 ((x & 0x1fff) << 0)
93
-#define s_RGA3_WIN0_ACT_OFF_SW_WIN0_ACT_YOFF(x)		 ((x & 0x1fff) << 16)
210
+#define s_RGA3_WIN0_ACT_OFF_SW_WIN0_ACT_XOFF(x)			((x & 0x1fff) << 0)
211
+#define s_RGA3_WIN0_ACT_OFF_SW_WIN0_ACT_YOFF(x)			((x & 0x1fff) << 16)
94
212
 
95
213
 /* RGA3_WIN0_ACT_SIZE */
96
-#define m_RGA3_WIN0_ACT_SIZE_SW_WIN0_ACT_WIDTH		 (0x1fff << 0)
97
-#define m_RGA3_WIN0_ACT_SIZE_SW_WIN0_ACT_HEIGHT		 (0x1fff << 16)
214
+#define m_RGA3_WIN0_ACT_SIZE_SW_WIN0_ACT_WIDTH			(0x1fff << 0)
215
+#define m_RGA3_WIN0_ACT_SIZE_SW_WIN0_ACT_HEIGHT			(0x1fff << 16)
98
216
 
99
-#define s_RGA3_WIN0_ACT_SIZE_SW_WIN0_ACT_WIDTH(x)	 ((x & 0x1fff) << 0)
100
-#define s_RGA3_WIN0_ACT_SIZE_SW_WIN0_ACT_HEIGHT(x)	 ((x & 0x1fff) << 16)
217
+#define s_RGA3_WIN0_ACT_SIZE_SW_WIN0_ACT_WIDTH(x)		((x & 0x1fff) << 0)
218
+#define s_RGA3_WIN0_ACT_SIZE_SW_WIN0_ACT_HEIGHT(x)		((x & 0x1fff) << 16)
101
219
 
102
220
 /* RGA3_WIN0_DST_SIZE */
103
-#define m_RGA3_WIN0_DST_SIZE_SW_WIN0_DST_WIDTH		 (0x1fff << 0)
104
-#define m_RGA3_WIN0_DST_SIZE_SW_WIN0_DST_HEIGHT		 (0x1fff << 16)
221
+#define m_RGA3_WIN0_DST_SIZE_SW_WIN0_DST_WIDTH			(0x1fff << 0)
222
+#define m_RGA3_WIN0_DST_SIZE_SW_WIN0_DST_HEIGHT			(0x1fff << 16)
105
223
 
106
-#define s_RGA3_WIN0_DST_SIZE_SW_WIN0_DST_WIDTH(x)	 ((x & 0x1fff) << 0)
107
-#define s_RGA3_WIN0_DST_SIZE_SW_WIN0_DST_HEIGHT(x)	 ((x & 0x1fff) << 16)
224
+#define s_RGA3_WIN0_DST_SIZE_SW_WIN0_DST_WIDTH(x)		((x & 0x1fff) << 0)
225
+#define s_RGA3_WIN0_DST_SIZE_SW_WIN0_DST_HEIGHT(x)		((x & 0x1fff) << 16)
108
226
 
109
227
 /* RGA3_WIN0_SCL_FAC */
110
-#define m_RGA3_WIN0_SCL_FAC_SW_WIN0_VER_FAC			 (0xffff << 0)
111
-#define m_RGA3_WIN0_SCL_FAC_SW_WIN0_HOR_FAC			 (0xffff << 16)
228
+#define m_RGA3_WIN0_SCL_FAC_SW_WIN0_VER_FAC			(0xffff << 0)
229
+#define m_RGA3_WIN0_SCL_FAC_SW_WIN0_HOR_FAC			(0xffff << 16)
112
230
 
113
-#define s_RGA3_WIN0_SCL_FAC_SW_WIN0_VER_FAC(x)		 ((x & 0xffff) << 0)
114
-#define s_RGA3_WIN0_SCL_FAC_SW_WIN0_HOR_FAC(x)		 ((x & 0xffff) << 16)
231
+#define s_RGA3_WIN0_SCL_FAC_SW_WIN0_VER_FAC(x)			((x & 0xffff) << 0)
232
+#define s_RGA3_WIN0_SCL_FAC_SW_WIN0_HOR_FAC(x)			((x & 0xffff) << 16)
115
233
 
116
234
 /* RGA3_WIN1_RD_CTRL */
117
-#define m_RGA3_WIN1_RD_CTRL_SW_WIN1_ENABLE			 (0x1 << 0)
118
-#define m_RGA3_WIN1_RD_CTRL_SW_WIN1_RD_MODE			 (0x3 << 1)
119
-#define m_RGA3_WIN1_RD_CTRL_SW_WIN1_PIC_FORMAT		 (0xf << 4)
120
-#define m_RGA3_WIN1_RD_CTRL_SW_WIN1_RD_FORMAT		 (0x3 << 8)
121
-#define m_RGA3_WIN1_RD_CTRL_SW_WIN1_YUV10B_COMPACT	 (0x1 << 10)
122
-#define m_RGA3_WIN1_RD_CTRL_SW_WIN1_ENDIAN_MODE		 (0x1 << 11)
235
+#define m_RGA3_WIN1_RD_CTRL_SW_WIN1_ENABLE			(0x1 << 0)
236
+#define m_RGA3_WIN1_RD_CTRL_SW_WIN1_RD_MODE			(0x3 << 1)
237
+#define m_RGA3_WIN1_RD_CTRL_SW_WIN1_PIC_FORMAT			(0xf << 4)
238
+#define m_RGA3_WIN1_RD_CTRL_SW_WIN1_RD_FORMAT			(0x3 << 8)
239
+#define m_RGA3_WIN1_RD_CTRL_SW_WIN1_YUV10B_COMPACT		(0x1 << 10)
240
+#define m_RGA3_WIN1_RD_CTRL_SW_WIN1_ENDIAN_MODE			(0x1 << 11)
123
241
 #define m_RGA3_WIN1_RD_CTRL_SW_WIN1_PIX_SWAP			(0x1 << 12)
124
-#define m_RGA3_WIN1_RD_CTRL_SW_WIN1_YC_SWAP			 (0x1 << 13)
125
-#define m_RGA3_WIN1_RD_CTRL_SW_WIN1_ROT				 (0x1 << 16)
126
-#define m_RGA3_WIN1_RD_CTRL_SW_WIN1_XMIRROR			 (0x1 << 17)
127
-#define m_RGA3_WIN1_RD_CTRL_SW_WIN1_YMIRROR			 (0x1 << 18)
128
-#define m_RGA3_WIN1_RD_CTRL_SW_WIN1_HOR_BY			 (0x1 << 20)
129
-#define m_RGA3_WIN1_RD_CTRL_SW_WIN1_HOR_UP			 (0x1 << 21)
130
-#define m_RGA3_WIN1_RD_CTRL_SW_WIN1_VER_BY			 (0x1 << 22)
131
-#define m_RGA3_WIN1_RD_CTRL_SW_WIN1_VER_UP			 (0x1 << 23)
132
-#define m_RGA3_WIN1_RD_CTRL_SW_WIN1_Y2R_EN			 (0x1 << 24)
133
-#define m_RGA3_WIN1_RD_CTRL_SW_WIN1_R2Y_EN			 (0x1 << 25)
242
+#define m_RGA3_WIN1_RD_CTRL_SW_WIN1_YC_SWAP			(0x1 << 13)
243
+#define m_RGA3_WIN1_RD_CTRL_SW_WIN1_ROT				(0x1 << 16)
244
+#define m_RGA3_WIN1_RD_CTRL_SW_WIN1_XMIRROR			(0x1 << 17)
245
+#define m_RGA3_WIN1_RD_CTRL_SW_WIN1_YMIRROR			(0x1 << 18)
246
+#define m_RGA3_WIN1_RD_CTRL_SW_WIN1_HOR_BY			(0x1 << 20)
247
+#define m_RGA3_WIN1_RD_CTRL_SW_WIN1_HOR_UP			(0x1 << 21)
248
+#define m_RGA3_WIN1_RD_CTRL_SW_WIN1_VER_BY			(0x1 << 22)
249
+#define m_RGA3_WIN1_RD_CTRL_SW_WIN1_VER_UP			(0x1 << 23)
250
+#define m_RGA3_WIN1_RD_CTRL_SW_WIN1_Y2R_EN			(0x1 << 24)
251
+#define m_RGA3_WIN1_RD_CTRL_SW_WIN1_R2Y_EN			(0x1 << 25)
134
252
 #define m_RGA3_WIN1_RD_CTRL_SW_WIN1_CSC_MODE			(0x3 << 26)
135
253
 #define m_RGA3_WIN1_RD_CTRL_SW_WIN1_PERF_OPT_DIS		(0x1 << 29)
136
254
 #define m_RGA3_WIN1_RD_CTRL_SW_WIN1_RD_ALIGN_DIS		(0x1 << 30)
137
255
 
138
-#define s_RGA3_WIN1_RD_CTRL_SW_WIN1_ENABLE(x)		 ((x & 0x1) << 0)
139
-#define s_RGA3_WIN1_RD_CTRL_SW_WIN1_RD_MODE(x)		 ((x & 0x3) << 1)
140
-#define s_RGA3_WIN1_RD_CTRL_SW_WIN1_PIC_FORMAT(x)	 ((x & 0xf) << 4)
256
+#define s_RGA3_WIN1_RD_CTRL_SW_WIN1_ENABLE(x)			((x & 0x1) << 0)
257
+#define s_RGA3_WIN1_RD_CTRL_SW_WIN1_RD_MODE(x)			((x & 0x3) << 1)
258
+#define s_RGA3_WIN1_RD_CTRL_SW_WIN1_PIC_FORMAT(x)		((x & 0xf) << 4)
141
259
 #define s_RGA3_WIN1_RD_CTRL_SW_WIN1_RD_FORMAT(x)		((x & 0x3) << 8)
142
-#define s_RGA3_WIN1_RD_CTRL_SW_WIN1_YUV10B_COMPACT(x) ((x & 0x1) << 10)
143
-#define s_RGA3_WIN1_RD_CTRL_SW_WIN1_ENDIAN_MODE(x)	 ((x & 0x1) << 11)
144
-#define s_RGA3_WIN1_RD_CTRL_SW_WIN1_PIX_SWAP(x)		 ((x & 0x1) << 12)
145
-#define s_RGA3_WIN1_RD_CTRL_SW_WIN1_YC_SWAP(x)		 ((x & 0x1) << 13)
146
-#define s_RGA3_WIN1_RD_CTRL_SW_WIN1_ROT(x)		((x & 0x1) << 16)
147
-#define s_RGA3_WIN1_RD_CTRL_SW_WIN1_XMIRROR(x)		 ((x & 0x1) << 17)
148
-#define s_RGA3_WIN1_RD_CTRL_SW_WIN1_YMIRROR(x)		 ((x & 0x1) << 18)
149
-#define s_RGA3_WIN1_RD_CTRL_SW_WIN1_HOR_BY(x)		 ((x & 0x1) << 20)
150
-#define s_RGA3_WIN1_RD_CTRL_SW_WIN1_HOR_UP(x)		 ((x & 0x1) << 21)
151
-#define s_RGA3_WIN1_RD_CTRL_SW_WIN1_VER_BY(x)		 ((x & 0x1) << 22)
152
-#define s_RGA3_WIN1_RD_CTRL_SW_WIN1_VER_UP(x)		 ((x & 0x1) << 23)
153
-#define s_RGA3_WIN1_RD_CTRL_SW_WIN1_Y2R_EN(x)		 ((x & 0x1) << 24)
154
-#define s_RGA3_WIN1_RD_CTRL_SW_WIN1_R2Y_EN(x)		 ((x & 0x1) << 25)
155
-#define s_RGA3_WIN1_RD_CTRL_SW_WIN1_CSC_MODE(x)		 ((x & 0x3) << 26)
156
-#define s_RGA3_WIN1_RD_CTRL_SW_WIN1_PERF_OPT_DIS(x)	 ((x & 0x1) << 29)
157
-#define s_RGA3_WIN1_RD_CTRL_SW_WIN1_RD_ALIGN_DIS(x)	 ((x & 0x1) << 30)
260
+#define s_RGA3_WIN1_RD_CTRL_SW_WIN1_YUV10B_COMPACT(x)		((x & 0x1) << 10)
261
+#define s_RGA3_WIN1_RD_CTRL_SW_WIN1_ENDIAN_MODE(x)		((x & 0x1) << 11)
262
+#define s_RGA3_WIN1_RD_CTRL_SW_WIN1_PIX_SWAP(x)			((x & 0x1) << 12)
263
+#define s_RGA3_WIN1_RD_CTRL_SW_WIN1_YC_SWAP(x)			((x & 0x1) << 13)
264
+#define s_RGA3_WIN1_RD_CTRL_SW_WIN1_ROT(x)			((x & 0x1) << 16)
265
+#define s_RGA3_WIN1_RD_CTRL_SW_WIN1_XMIRROR(x)			((x & 0x1) << 17)
266
+#define s_RGA3_WIN1_RD_CTRL_SW_WIN1_YMIRROR(x)			((x & 0x1) << 18)
267
+#define s_RGA3_WIN1_RD_CTRL_SW_WIN1_HOR_BY(x)			((x & 0x1) << 20)
268
+#define s_RGA3_WIN1_RD_CTRL_SW_WIN1_HOR_UP(x)			((x & 0x1) << 21)
269
+#define s_RGA3_WIN1_RD_CTRL_SW_WIN1_VER_BY(x)			((x & 0x1) << 22)
270
+#define s_RGA3_WIN1_RD_CTRL_SW_WIN1_VER_UP(x)			((x & 0x1) << 23)
271
+#define s_RGA3_WIN1_RD_CTRL_SW_WIN1_Y2R_EN(x)			((x & 0x1) << 24)
272
+#define s_RGA3_WIN1_RD_CTRL_SW_WIN1_R2Y_EN(x)			((x & 0x1) << 25)
273
+#define s_RGA3_WIN1_RD_CTRL_SW_WIN1_CSC_MODE(x)			((x & 0x3) << 26)
274
+#define s_RGA3_WIN1_RD_CTRL_SW_WIN1_PERF_OPT_DIS(x)		((x & 0x1) << 29)
275
+#define s_RGA3_WIN1_RD_CTRL_SW_WIN1_RD_ALIGN_DIS(x)		((x & 0x1) << 30)
158
276
 
159
277
 /* RGA3_WIN1_FBC_OFF */
160
278
 #define m_RGA3_WIN1_FBC_OFF_SW_WIN1_FBC_XOFF			(0x1fff << 0)
161
279
 #define m_RGA3_WIN1_FBC_OFF_SW_WIN1_FBC_YOFF			(0x1fff << 16)
162
280
 
163
-#define s_RGA3_WIN1_FBC_OFF_SW_WIN1_FBC_XOFF(x)		 ((x & 0x1fff) << 0)
164
-#define s_RGA3_WIN1_FBC_OFF_SW_WIN1_FBC_YOFF(x)		 ((x & 0x1fff) << 16)
281
+#define s_RGA3_WIN1_FBC_OFF_SW_WIN1_FBC_XOFF(x)			((x & 0x1fff) << 0)
282
+#define s_RGA3_WIN1_FBC_OFF_SW_WIN1_FBC_YOFF(x)			((x & 0x1fff) << 16)
165
283
 
166
284
 /* RGA3_WIN1_SRC_SIZE */
167
-#define m_RGA3_WIN1_SRC_SIZE_SW_WIN1_SRC_WIDTH		 (0x1fff << 0)
168
-#define m_RGA3_WIN1_SRC_SIZE_SW_WIN1_SRC_HEIGHT		 (0x1fff << 16)
285
+#define m_RGA3_WIN1_SRC_SIZE_SW_WIN1_SRC_WIDTH			(0x1fff << 0)
286
+#define m_RGA3_WIN1_SRC_SIZE_SW_WIN1_SRC_HEIGHT			(0x1fff << 16)
169
287
 
170
-#define s_RGA3_WIN1_SRC_OFF_SW_WIN1_SRC_WIDTH(x)	((x & 0x1fff) << 0)
171
-#define s_RGA3_WIN1_SRC_OFF_SW_WIN1_SRC_HEIGHT(x)	 ((x & 0x1fff) << 16)
288
+#define s_RGA3_WIN1_SRC_OFF_SW_WIN1_SRC_WIDTH(x)		((x & 0x1fff) << 0)
289
+#define s_RGA3_WIN1_SRC_OFF_SW_WIN1_SRC_HEIGHT(x)		((x & 0x1fff) << 16)
172
290
 
173
291
 /* RGA3_WIN1_ACT_OFF */
174
292
 #define m_RGA3_WIN1_ACT_OFF_SW_WIN1_ACT_XOFF			(0x1fff << 0)
175
293
 #define m_RGA3_WIN1_ACT_OFF_SW_WIN1_ACT_YOFF			(0x1fff << 16)
176
294
 
177
-#define s_RGA3_WIN1_ACT_OFF_SW_WIN1_ACT_XOFF(x)		 ((x & 0x1fff) << 0)
178
-#define s_RGA3_WIN1_ACT_OFF_SW_WIN1_ACT_YOFF(x)		 ((x & 0x1fff) << 16)
295
+#define s_RGA3_WIN1_ACT_OFF_SW_WIN1_ACT_XOFF(x)			((x & 0x1fff) << 0)
296
+#define s_RGA3_WIN1_ACT_OFF_SW_WIN1_ACT_YOFF(x)			((x & 0x1fff) << 16)
179
297
 
180
298
 /* RGA3_WIN1_ACT_SIZE */
181
-#define m_RGA3_WIN1_ACT_SIZE_SW_WIN1_ACT_WIDTH		 (0x1fff << 0)
182
-#define m_RGA3_WIN1_ACT_SIZE_SW_WIN1_ACT_HEIGHT		 (0x1fff << 16)
299
+#define m_RGA3_WIN1_ACT_SIZE_SW_WIN1_ACT_WIDTH			(0x1fff << 0)
300
+#define m_RGA3_WIN1_ACT_SIZE_SW_WIN1_ACT_HEIGHT			(0x1fff << 16)
183
301
 
184
-#define s_RGA3_WIN1_ACT_SIZE_SW_WIN1_ACT_WIDTH(x)	 ((x & 0x1fff) << 0)
185
-#define s_RGA3_WIN1_ACT_SIZE_SW_WIN1_ACT_HEIGHT(x)	 ((x & 0x1fff) << 16)
302
+#define s_RGA3_WIN1_ACT_SIZE_SW_WIN1_ACT_WIDTH(x)		((x & 0x1fff) << 0)
303
+#define s_RGA3_WIN1_ACT_SIZE_SW_WIN1_ACT_HEIGHT(x)		((x & 0x1fff) << 16)
186
304
 
187
305
 /* RGA3_WIN1_DST_SIZE */
188
-#define m_RGA3_WIN1_DST_SIZE_SW_WIN1_DST_WIDTH		 (0x1fff << 0)
189
-#define m_RGA3_WIN1_DST_SIZE_SW_WIN1_DST_HEIGHT		 (0x1fff << 16)
306
+#define m_RGA3_WIN1_DST_SIZE_SW_WIN1_DST_WIDTH			(0x1fff << 0)
307
+#define m_RGA3_WIN1_DST_SIZE_SW_WIN1_DST_HEIGHT			(0x1fff << 16)
190
308
 
191
-#define s_RGA3_WIN1_DST_SIZE_SW_WIN1_DST_WIDTH(x)	 ((x & 0x1fff) << 0)
192
-#define s_RGA3_WIN1_DST_SIZE_SW_WIN1_DST_HEIGHT(x)	 ((x & 0x1fff) << 16)
309
+#define s_RGA3_WIN1_DST_SIZE_SW_WIN1_DST_WIDTH(x)		((x & 0x1fff) << 0)
310
+#define s_RGA3_WIN1_DST_SIZE_SW_WIN1_DST_HEIGHT(x)		((x & 0x1fff) << 16)
193
311
 
194
312
 /* RGA3_WIN1_SCL_FAC */
195
-#define m_RGA3_WIN1_SCL_FAC_SW_WIN1_VER_FAC			 (0xffff << 0)
196
-#define m_RGA3_WIN1_SCL_FAC_SW_WIN1_HOR_FAC			 (0xffff << 16)
313
+#define m_RGA3_WIN1_SCL_FAC_SW_WIN1_VER_FAC			(0xffff << 0)
314
+#define m_RGA3_WIN1_SCL_FAC_SW_WIN1_HOR_FAC			(0xffff << 16)
197
315
 
198
-#define s_RGA3_WIN1_SCL_FAC_SW_WIN1_VER_FAC(x)		 ((x & 0xffff) << 0)
199
-#define s_RGA3_WIN1_SCL_FAC_SW_WIN1_HOR_FAC(x)		 ((x & 0xffff) << 16)
316
+#define s_RGA3_WIN1_SCL_FAC_SW_WIN1_VER_FAC(x)			((x & 0xffff) << 0)
317
+#define s_RGA3_WIN1_SCL_FAC_SW_WIN1_HOR_FAC(x)			((x & 0xffff) << 16)
200
318
 
201
319
 /* RGA3_OVLP_CTRL */
202
-#define m_RGA3_OVLP_CTRL_SW_OVLP_MODE				 (0x3 << 0)
203
-#define m_RGA3_OVLP_CTRL_SW_OVLP_FIELD				 (0x1 << 2)
204
-#define m_RGA3_OVLP_CTRL_SW_TOP_SWAP			(0x1 << 3)
205
-#define m_RGA3_OVLP_CTRL_SW_TOP_ALPHA_EN		(0x1 << 4)
206
-#define m_RGA3_OVLP_CTRL_SW_TOP_KEY_EN				 (0x7FFF << 5)
207
-#define m_RGA3_OVLP_CTRL_SW_OVLP_Y2R_EN				 (0x1 << 20)
208
-#define m_RGA3_OVLP_CTRL_SW_OVLP_R2Y_EN				 (0x1 << 21)
209
-#define m_RGA3_OVLP_CTRL_SW_OVLP_CSC_MODE			 (0x3 << 22)
320
+#define m_RGA3_OVLP_CTRL_SW_OVLP_MODE				(0x3 << 0)
321
+#define m_RGA3_OVLP_CTRL_SW_OVLP_FIELD				(0x1 << 2)
322
+#define m_RGA3_OVLP_CTRL_SW_TOP_SWAP				(0x1 << 3)
323
+#define m_RGA3_OVLP_CTRL_SW_TOP_ALPHA_EN			(0x1 << 4)
324
+#define m_RGA3_OVLP_CTRL_SW_TOP_KEY_EN				(0x7FFF << 5)
325
+#define m_RGA3_OVLP_CTRL_SW_OVLP_Y2R_EN				(0x1 << 20)
326
+#define m_RGA3_OVLP_CTRL_SW_OVLP_R2Y_EN				(0x1 << 21)
327
+#define m_RGA3_OVLP_CTRL_SW_OVLP_CSC_MODE			(0x3 << 22)
210
328
 
211
-#define s_RGA3_OVLP_CTRL_SW_OVLP_MODE(x)		((x & 0x3) << 0)
212
-#define s_RGA3_OVLP_CTRL_SW_OVLP_FIELD(x)		((x & 0x1) << 2)
213
-#define s_RGA3_OVLP_CTRL_SW_TOP_SWAP(x)			((x & 0x1) << 3)
214
-#define s_RGA3_OVLP_CTRL_SW_TOP_ALPHA_EN(x)		((x & 0x1) << 4)
215
-#define s_RGA3_OVLP_CTRL_SW_TOP_KEY_EN(x)		((x & 0x7FFF) << 5)
216
-#define s_RGA3_OVLP_CTRL_SW_OVLP_Y2R_EN(x)		((x & 0x1) << 20)
217
-#define s_RGA3_OVLP_CTRL_SW_OVLP_R2Y_EN(x)		((x & 0x1) << 21)
218
-#define s_RGA3_OVLP_CTRL_SW_OVLP_CSC_MODE(x)	((x & 0x3) << 22)
329
+#define s_RGA3_OVLP_CTRL_SW_OVLP_MODE(x)			((x & 0x3) << 0)
330
+#define s_RGA3_OVLP_CTRL_SW_OVLP_FIELD(x)			((x & 0x1) << 2)
331
+#define s_RGA3_OVLP_CTRL_SW_TOP_SWAP(x)				((x & 0x1) << 3)
332
+#define s_RGA3_OVLP_CTRL_SW_TOP_ALPHA_EN(x)			((x & 0x1) << 4)
333
+#define s_RGA3_OVLP_CTRL_SW_TOP_KEY_EN(x)			((x & 0x7FFF) << 5)
334
+#define s_RGA3_OVLP_CTRL_SW_OVLP_Y2R_EN(x)			((x & 0x1) << 20)
335
+#define s_RGA3_OVLP_CTRL_SW_OVLP_R2Y_EN(x)			((x & 0x1) << 21)
336
+#define s_RGA3_OVLP_CTRL_SW_OVLP_CSC_MODE(x)			((x & 0x3) << 22)
219
337
 
220
338
 /* RGA3_OVLP_OFF */
221
-#define m_RGA3_OVLP_OFF_SW_OVLP_XOFF		(0x1fff << 0)
222
-#define m_RGA3_OVLP_OFF_SW_OVLP_YOFF		(0x1fff << 16)
339
+#define m_RGA3_OVLP_OFF_SW_OVLP_XOFF				(0x1fff << 0)
340
+#define m_RGA3_OVLP_OFF_SW_OVLP_YOFF				(0x1fff << 16)
223
341
 
224
-#define s_RGA3_OVLP_OFF_SW_OVLP_XOFF(x)		((x & 0x1fff) << 0)
225
-#define s_RGA3_OVLP_OFF_SW_OVLP_YOFF(x)		((x & 0x1fff) << 16)
342
+#define s_RGA3_OVLP_OFF_SW_OVLP_XOFF(x)				((x & 0x1fff) << 0)
343
+#define s_RGA3_OVLP_OFF_SW_OVLP_YOFF(x)				((x & 0x1fff) << 16)
226
344
 
227
345
 /* RGA3_OVLP_TOP_KEY_MIN */
228
-#define m_RGA3_OVLP_TOP_KEY_MIN_SW_TOP_KEY_YG_MIN	 (0x3ff << 0)
229
-#define m_RGA3_OVLP_TOP_KEY_MIN_SW_TOP_KEY_UB_MIN	 (0x3ff << 10)
230
-#define m_RGA3_OVLP_TOP_KEY_MIN_SW_TOP_KEY_VR_MIN	 (0x3ff << 20)
346
+#define m_RGA3_OVLP_TOP_KEY_MIN_SW_TOP_KEY_YG_MIN		(0x3ff << 0)
347
+#define m_RGA3_OVLP_TOP_KEY_MIN_SW_TOP_KEY_UB_MIN		(0x3ff << 10)
348
+#define m_RGA3_OVLP_TOP_KEY_MIN_SW_TOP_KEY_VR_MIN		(0x3ff << 20)
231
349
 
232
-#define s_RGA3_OVLP_TOP_KEY_MIN_SW_TOP_KEY_YG_MIN(x)	((x & 0x3f)f << 0)
233
-#define s_RGA3_OVLP_TOP_KEY_MIN_SW_TOP_KEY_UB_MIN(x)	((x & 0x3ff) << 10)
234
-#define s_RGA3_OVLP_TOP_KEY_MIN_SW_TOP_KEY_VR_MIN(x)	((x & 0x3ff) << 20)
350
+#define s_RGA3_OVLP_TOP_KEY_MIN_SW_TOP_KEY_YG_MIN(x)		((x & 0x3f)f << 0)
351
+#define s_RGA3_OVLP_TOP_KEY_MIN_SW_TOP_KEY_UB_MIN(x)		((x & 0x3ff) << 10)
352
+#define s_RGA3_OVLP_TOP_KEY_MIN_SW_TOP_KEY_VR_MIN(x)		((x & 0x3ff) << 20)
235
353
 
236
354
 /* RGA3_OVLP_TOP_KEY_MAX */
237
-#define m_RGA3_OVLP_TOP_KEY_MAX_SW_TOP_KEY_YG_MAX	 (0x3ff << 0)
238
-#define m_RGA3_OVLP_TOP_KEY_MAX_SW_TOP_KEY_UB_MAX	 (0x3ff << 10)
239
-#define m_RGA3_OVLP_TOP_KEY_MAX_SW_TOP_KEY_VR_MAX	 (0x3ff << 20)
355
+#define m_RGA3_OVLP_TOP_KEY_MAX_SW_TOP_KEY_YG_MAX		(0x3ff << 0)
356
+#define m_RGA3_OVLP_TOP_KEY_MAX_SW_TOP_KEY_UB_MAX		(0x3ff << 10)
357
+#define m_RGA3_OVLP_TOP_KEY_MAX_SW_TOP_KEY_VR_MAX		(0x3ff << 20)
240
358
 
241
-#define s_RGA3_OVLP_TOP_KEY_MAX_SW_TOP_KEY_YG_MAX(x)	((x & 0x3ff) << 0)
242
-#define s_RGA3_OVLP_TOP_KEY_MAX_SW_TOP_KEY_UB_MAX(x)	((x & 0x3ff) << 10)
243
-#define s_RGA3_OVLP_TOP_KEY_MAX_SW_TOP_KEY_VR_MAX(x)	((x & 0x3ff) << 20)
359
+#define s_RGA3_OVLP_TOP_KEY_MAX_SW_TOP_KEY_YG_MAX(x)		((x & 0x3ff) << 0)
360
+#define s_RGA3_OVLP_TOP_KEY_MAX_SW_TOP_KEY_UB_MAX(x)		((x & 0x3ff) << 10)
361
+#define s_RGA3_OVLP_TOP_KEY_MAX_SW_TOP_KEY_VR_MAX(x)		((x & 0x3ff) << 20)
244
362
 
245
363
 /* RGA3_OVLP_TOP_CTRL */
246
364
 #define m_RGA3_OVLP_TOP_CTRL_SW_TOP_COLOR_M0			(0x1 << 0)
247
365
 #define m_RGA3_OVLP_TOP_CTRL_SW_TOP_ALPHA_M0			(0x1 << 1)
248
366
 #define m_RGA3_OVLP_TOP_CTRL_SW_TOP_BLEND_M0			(0x3 << 2)
249
367
 #define m_RGA3_OVLP_TOP_CTRL_SW_TOP_ALPHA_CAL_M0		(0x1 << 4)
250
-#define m_RGA3_OVLP_TOP_CTRL_SW_TOP_FACTOR_M0		 (0x7 << 5)
368
+#define m_RGA3_OVLP_TOP_CTRL_SW_TOP_FACTOR_M0			(0x7 << 5)
251
369
 #define m_RGA3_OVLP_TOP_CTRL_SW_TOP_GLOBAL_ALPHA		(0xff << 16)
252
370
 
253
-#define s_RGA3_OVLP_TOP_CTRL_SW_TOP_COLOR_M0(x)		 ((x & 0x1) << 0)
254
-#define s_RGA3_OVLP_TOP_CTRL_SW_TOP_ALPHA_M0(x)		 ((x & 0x1) << 1)
255
-#define s_RGA3_OVLP_TOP_CTRL_SW_TOP_BLEND_M0(x)		 ((x & 0x3) << 2)
256
-#define s_RGA3_OVLP_TOP_CTRL_SW_TOP_ALPHA_CAL_M0(x)	 ((x & 0x1) << 4)
371
+#define s_RGA3_OVLP_TOP_CTRL_SW_TOP_COLOR_M0(x)			((x & 0x1) << 0)
372
+#define s_RGA3_OVLP_TOP_CTRL_SW_TOP_ALPHA_M0(x)			((x & 0x1) << 1)
373
+#define s_RGA3_OVLP_TOP_CTRL_SW_TOP_BLEND_M0(x)			((x & 0x3) << 2)
374
+#define s_RGA3_OVLP_TOP_CTRL_SW_TOP_ALPHA_CAL_M0(x)		((x & 0x1) << 4)
257
375
 #define s_RGA3_OVLP_TOP_CTRL_SW_TOP_FACTOR_M0(x)		((x & 0x7) << 5)
258
-#define s_RGA3_OVLP_TOP_CTRL_SW_TOP_GLOBAL_ALPHA(x)	 ((x & 0xff) << 16)
376
+#define s_RGA3_OVLP_TOP_CTRL_SW_TOP_GLOBAL_ALPHA(x)		((x & 0xff) << 16)
259
377
 
260
378
 /* RGA3_OVLP_BOT_CTRL */
261
379
 #define m_RGA3_OVLP_BOT_CTRL_SW_BOT_COLOR_M0			(0x1 << 0)
262
380
 #define m_RGA3_OVLP_BOT_CTRL_SW_BOT_ALPHA_M0			(0x1 << 1)
263
381
 #define m_RGA3_OVLP_BOT_CTRL_SW_BOT_BLEND_M0			(0x3 << 2)
264
382
 #define m_RGA3_OVLP_BOT_CTRL_SW_BOT_ALPHA_CAL_M0		(0x1 << 4)
265
-#define m_RGA3_OVLP_BOT_CTRL_SW_BOT_FACTOR_M0		 (0x7 << 5)
383
+#define m_RGA3_OVLP_BOT_CTRL_SW_BOT_FACTOR_M0			(0x7 << 5)
266
384
 #define m_RGA3_OVLP_BOT_CTRL_SW_BOT_GLOBAL_ALPHA		(0xff << 16)
267
385
 
268
-#define s_RGA3_OVLP_BOT_CTRL_SW_BOT_COLOR_M0(x)		 ((x & 0x1) << 0)
269
-#define s_RGA3_OVLP_BOT_CTRL_SW_BOT_ALPHA_M0(x)		 ((x & 0x1) << 1)
270
-#define s_RGA3_OVLP_BOT_CTRL_SW_BOT_BLEND_M0(x)		 ((x & 0x3) << 2)
271
-#define s_RGA3_OVLP_BOT_CTRL_SW_BOT_ALPHA_CAL_M0(x)	 ((x & 0x1) << 4)
386
+#define s_RGA3_OVLP_BOT_CTRL_SW_BOT_COLOR_M0(x)			((x & 0x1) << 0)
387
+#define s_RGA3_OVLP_BOT_CTRL_SW_BOT_ALPHA_M0(x)			((x & 0x1) << 1)
388
+#define s_RGA3_OVLP_BOT_CTRL_SW_BOT_BLEND_M0(x)			((x & 0x3) << 2)
389
+#define s_RGA3_OVLP_BOT_CTRL_SW_BOT_ALPHA_CAL_M0(x)		((x & 0x1) << 4)
272
390
 #define s_RGA3_OVLP_BOT_CTRL_SW_BOT_FACTOR_M0(x)		((x & 0x7) << 5)
273
-#define s_RGA3_OVLP_BOT_CTRL_SW_BOT_GLOBAL_ALPHA(x)	 ((x & 0xff) << 16)
391
+#define s_RGA3_OVLP_BOT_CTRL_SW_BOT_GLOBAL_ALPHA(x)		((x & 0xff) << 16)
274
392
 
275
393
 /* RGA3_OVLP_TOP_ALPHA */
276
-#define m_RGA3_OVLP_TOP_ALPHA_SW_TOP_ALPHA_M1		 (0x1 << 1)
277
-#define m_RGA3_OVLP_TOP_ALPHA_SW_TOP_BLEND_M1		 (0x3 << 2)
278
-#define m_RGA3_OVLP_TOP_ALPHA_SW_TOP_ALPHA_CAL_M1	 (0x1 << 4)
279
-#define m_RGA3_OVLP_TOP_ALPHA_SW_TOP_FACTOR_M1		 (0x7 << 5)
394
+#define m_RGA3_OVLP_TOP_ALPHA_SW_TOP_ALPHA_M1			(0x1 << 1)
395
+#define m_RGA3_OVLP_TOP_ALPHA_SW_TOP_BLEND_M1			(0x3 << 2)
396
+#define m_RGA3_OVLP_TOP_ALPHA_SW_TOP_ALPHA_CAL_M1		(0x1 << 4)
397
+#define m_RGA3_OVLP_TOP_ALPHA_SW_TOP_FACTOR_M1			(0x7 << 5)
280
398
 
281
399
 #define s_RGA3_OVLP_TOP_ALPHA_SW_TOP_ALPHA_M1(x)		((x & 0x1) << 1)
282
400
 #define s_RGA3_OVLP_TOP_ALPHA_SW_TOP_BLEND_M1(x)		((x & 0x3) << 2)
283
-#define s_RGA3_OVLP_TOP_ALPHA_SW_TOP_ALPHA_CAL_M1(x)	((x & 0x1) << 4)
284
-#define s_RGA3_OVLP_TOP_ALPHA_SW_TOP_FACTOR_M1(x)	 ((x & 0x7) << 5)
401
+#define s_RGA3_OVLP_TOP_ALPHA_SW_TOP_ALPHA_CAL_M1(x)		((x & 0x1) << 4)
402
+#define s_RGA3_OVLP_TOP_ALPHA_SW_TOP_FACTOR_M1(x)		((x & 0x7) << 5)
285
403
 
286
404
 /* RGA3_OVLP_BOT_ALPHA */
287
-#define m_RGA3_OVLP_BOT_ALPHA_SW_BOT_ALPHA_M1		 (0x1 << 1)
288
-#define m_RGA3_OVLP_BOT_ALPHA_SW_BOT_BLEND_M1		 (0x3 << 2)
289
-#define m_RGA3_OVLP_BOT_ALPHA_SW_BOT_ALPHA_CAL_M1	 (0x1 << 4)
290
-#define m_RGA3_OVLP_BOT_ALPHA_SW_BOT_FACTOR_M1		 (0x7 << 5)
405
+#define m_RGA3_OVLP_BOT_ALPHA_SW_BOT_ALPHA_M1			(0x1 << 1)
406
+#define m_RGA3_OVLP_BOT_ALPHA_SW_BOT_BLEND_M1			(0x3 << 2)
407
+#define m_RGA3_OVLP_BOT_ALPHA_SW_BOT_ALPHA_CAL_M1		(0x1 << 4)
408
+#define m_RGA3_OVLP_BOT_ALPHA_SW_BOT_FACTOR_M1			(0x7 << 5)
291
409
 
292
410
 #define s_RGA3_OVLP_BOT_ALPHA_SW_BOT_ALPHA_M1(x)		((x & 0x1) << 1)
293
411
 #define s_RGA3_OVLP_BOT_ALPHA_SW_BOT_BLEND_M1(x)		((x & 0x3) << 2)
294
-#define s_RGA3_OVLP_BOT_ALPHA_SW_BOT_ALPHA_CAL_M1(x)	((x & 0x1) << 4)
295
-#define s_RGA3_OVLP_BOT_ALPHA_SW_BOT_FACTOR_M1(x)	 ((x & 0x7) << 5)
412
+#define s_RGA3_OVLP_BOT_ALPHA_SW_BOT_ALPHA_CAL_M1(x)		((x & 0x1) << 4)
413
+#define s_RGA3_OVLP_BOT_ALPHA_SW_BOT_FACTOR_M1(x)		((x & 0x7) << 5)
296
414
 
297
415
 /* RGA3_WR_CTRL */
298
-#define m_RGA3_WR_CTRL_SW_WR_MODE			(0x3 << 0)
299
-#define m_RGA3_WR_CTRL_SW_WR_FBCE_SPARSE_EN			 (0x1 << 2)
300
-#define m_RGA3_WR_CTRL_SW_WR_PIC_FORMAT				 (0xf << 4)
416
+#define m_RGA3_WR_CTRL_SW_WR_MODE				(0x3 << 0)
417
+#define m_RGA3_WR_CTRL_SW_WR_FBCE_SPARSE_EN			(0x1 << 2)
418
+#define m_RGA3_WR_CTRL_SW_WR_PIC_FORMAT				(0xf << 4)
301
419
 #define m_RGA3_WR_CTRL_SW_WR_FORMAT				(0x3 << 8)
302
-#define m_RGA3_WR_CTRL_SW_WR_YUV10B_COMPACT			 (0x1 << 10)
303
-#define m_RGA3_WR_CTRL_SW_WR_ENDIAN_MODE		(0x1 << 11)
304
-#define m_RGA3_WR_CTRL_SW_WR_PIX_SWAP				 (0x1 << 12)
305
-#define m_RGA3_WR_CTRL_SW_OUTSTANDING_MAX			 (0x3f << 13)
306
-#define m_RGA3_WR_CTRL_SW_WR_YC_SWAP			(0x1 << 20)
420
+#define m_RGA3_WR_CTRL_SW_WR_YUV10B_COMPACT			(0x1 << 10)
421
+#define m_RGA3_WR_CTRL_SW_WR_ENDIAN_MODE			(0x1 << 11)
422
+#define m_RGA3_WR_CTRL_SW_WR_PIX_SWAP				(0x1 << 12)
423
+#define m_RGA3_WR_CTRL_SW_OUTSTANDING_MAX			(0x3f << 13)
424
+#define m_RGA3_WR_CTRL_SW_WR_YC_SWAP				(0x1 << 20)
307
425
 
308
-#define s_RGA3_WR_CTRL_SW_WR_MODE(x)			((x & 0x3) << 0)
309
-#define s_RGA3_WR_CTRL_SW_WR_FBCE_SPARSE_EN(x)		 ((x & 0x1) << 2)
310
-#define s_RGA3_WR_CTRL_SW_WR_PIC_FORMAT(x)		((x & 0xf) << 4)
311
-#define s_RGA3_WR_CTRL_SW_WR_FORMAT(x)			((x & 0x3) << 8)
312
-#define s_RGA3_WR_CTRL_SW_WR_YUV10B_COMPACT(x)		 ((x & 0x1) << 10)
313
-#define s_RGA3_WR_CTRL_SW_WR_ENDIAN_MODE(x)		((x & 0x1) << 11)
314
-#define s_RGA3_WR_CTRL_SW_WR_PIX_SWAP(x)		((x & 0x1) << 12)
315
-#define s_RGA3_WR_CTRL_SW_OUTSTANDING_MAX(x)	((x & 0x3f) << 13)
316
-#define s_RGA3_WR_CTRL_SW_WR_YC_SWAP(x)			((x & 0x1) << 20)
426
+#define s_RGA3_WR_CTRL_SW_WR_MODE(x)				((x & 0x3) << 0)
427
+#define s_RGA3_WR_CTRL_SW_WR_FBCE_SPARSE_EN(x)			((x & 0x1) << 2)
428
+#define s_RGA3_WR_CTRL_SW_WR_PIC_FORMAT(x)			((x & 0xf) << 4)
429
+#define s_RGA3_WR_CTRL_SW_WR_FORMAT(x)				((x & 0x3) << 8)
430
+#define s_RGA3_WR_CTRL_SW_WR_YUV10B_COMPACT(x)			((x & 0x1) << 10)
431
+#define s_RGA3_WR_CTRL_SW_WR_ENDIAN_MODE(x)			((x & 0x1) << 11)
432
+#define s_RGA3_WR_CTRL_SW_WR_PIX_SWAP(x)			((x & 0x1) << 12)
433
+#define s_RGA3_WR_CTRL_SW_OUTSTANDING_MAX(x)			((x & 0x3f) << 13)
434
+#define s_RGA3_WR_CTRL_SW_WR_YC_SWAP(x)				((x & 0x1) << 20)
317
435
 
318
436
 /* RGA3_WR_FBCE_CTRL */
319
-#define m_RGA3_WR_FBCE_CTRL_SW_WR_FBCE_BLKBD_OPT_DIS	(0x1 << 0)
437
+#define m_RGA3_WR_FBCE_CTRL_SW_WR_FBCE_BLKBD_OPT_DIS		(0x1 << 0)
320
438
 #define m_RGA3_WR_FBCE_CTRL_SW_WR_FBCE_HOFF_DISS		(0x1 << 1)
321
-#define m_RGA3_WR_FBCE_CTRL_SW_WR_FBCE_PL_FIFO0_WATERMARK	 (0x3f << 2)
322
-#define m_RGA3_WR_FBCE_CTRL_SW_WR_FBCE_PL_FIFO1_WATERMARK	 (0x3f << 8)
323
-#define m_RGA3_WR_FBCE_CTRL_SW_WR_FBCE_SIZE_ALIGN_DIS		 (0x1 << 31)
439
+#define m_RGA3_WR_FBCE_CTRL_SW_WR_FBCE_PL_FIFO0_WATERMARK	(0x3f << 2)
440
+#define m_RGA3_WR_FBCE_CTRL_SW_WR_FBCE_PL_FIFO1_WATERMARK	(0x3f << 8)
441
+#define m_RGA3_WR_FBCE_CTRL_SW_WR_FBCE_SIZE_ALIGN_DIS		(0x1 << 31)
324
442
 
325
-#define s_RGA3_WR_FBCE_CTRL_SW_WR_FBCE_BLKBD_OPT_DIS(x)	((x & 0x1) << 0)
443
+#define s_RGA3_WR_FBCE_CTRL_SW_WR_FBCE_BLKBD_OPT_DIS(x)		((x & 0x1) << 0)
326
444
 #define s_RGA3_WR_FBCE_CTRL_SW_WR_FBCE_HOFF_DISS(x)		((x & 0x1) << 1)
327
-#define s_RGA3_WR_FBCE_CTRL_SW_WR_FBCE_PL_FIFO0_WATERMARK(x) ((x & 0x3f) << 2)
328
-#define s_RGA3_WR_FBCE_CTRL_SW_WR_FBCE_PL_FIFO1_WATERMARK(x) ((x & 0x3f) << 8)
329
-#define s_RGA3_WR_FBCE_CTRL_SW_WR_FBCE_SIZE_ALIGN_DIS(x) ((x & 0x1) << 31)
445
+#define s_RGA3_WR_FBCE_CTRL_SW_WR_FBCE_PL_FIFO0_WATERMARK(x)	((x & 0x3f) << 2)
446
+#define s_RGA3_WR_FBCE_CTRL_SW_WR_FBCE_PL_FIFO1_WATERMARK(x)	((x & 0x3f) << 8)
447
+#define s_RGA3_WR_FBCE_CTRL_SW_WR_FBCE_SIZE_ALIGN_DIS(x)	((x & 0x1) << 31)
330
448
 
331
449
 /* RGA3_MMU_STATUS read_only */
332
-#define m_RGA3_MMU_STATUS_PAGING_ENABLED		(0x1 << 0)
333
-#define m_RGA3_MMU_STATUS_PAGE_FAULT_ACTIVE			 (0x1 << 1)
334
-#define m_RGA3_MMU_STATUS_STAIL_ACTIVE				 (0x1 << 2)
335
-#define m_RGA3_MMU_STATUS_MMU_IDLE			(0x1 << 3)
336
-#define m_RGA3_MMU_STATUS_REPLAY_BUFFER_EMPTY		 (0x1 << 4)
337
-#define m_RGA3_MMU_STATUS_PAGE_FAULT_IS_WRITE		 (0x1 << 5)
338
-#define m_RGA3_MMU_STATUS_PAGE_FAULT_BUS_ID			 (0x1f << 6)
450
+#define m_RGA3_MMU_STATUS_PAGING_ENABLED			(0x1 << 0)
451
+#define m_RGA3_MMU_STATUS_PAGE_FAULT_ACTIVE			(0x1 << 1)
452
+#define m_RGA3_MMU_STATUS_STAIL_ACTIVE				(0x1 << 2)
453
+#define m_RGA3_MMU_STATUS_MMU_IDLE				(0x1 << 3)
454
+#define m_RGA3_MMU_STATUS_REPLAY_BUFFER_EMPTY			(0x1 << 4)
455
+#define m_RGA3_MMU_STATUS_PAGE_FAULT_IS_WRITE			(0x1 << 5)
456
+#define m_RGA3_MMU_STATUS_PAGE_FAULT_BUS_ID			(0x1f << 6)
339
457
 
340
458
 /* RGA3_MMU_INT_RAWSTAT read_only */
341
-#define m_RGA3_MMU_INT_RAWSTAT_READ_BUS_ERROR		 (0x1 << 0)
342
-#define m_RGA3_MMU_INT_RAWSTAT_PAGE_FAULT			 (0x1 << 1)
459
+#define m_RGA3_MMU_INT_RAWSTAT_READ_BUS_ERROR			(0x1 << 0)
460
+#define m_RGA3_MMU_INT_RAWSTAT_PAGE_FAULT			(0x1 << 1)
343
461
 
344
462
 /* RGA3_MMU_INT_CLEAR write_only */
345
-#define m_RGA3_MMU_INT_CLEAR_READ_BUS_ERROR			 (0x1 << 0)
346
-#define m_RGA3_MMU_INT_CLEAR_PAGE_FAULT				 (0x1 << 1)
463
+#define m_RGA3_MMU_INT_CLEAR_READ_BUS_ERROR			(0x1 << 0)
464
+#define m_RGA3_MMU_INT_CLEAR_PAGE_FAULT				(0x1 << 1)
347
465
 
348
-#define s_RGA3_MMU_INT_CLEAR_READ_BUS_ERROR(x)		 ((x & 0x1) << 0)
349
-#define s_RGA3_MMU_INT_CLEAR_PAGE_FAULT(x)		((x & 0x1) << 1)
466
+#define s_RGA3_MMU_INT_CLEAR_READ_BUS_ERROR(x)			((x & 0x1) << 0)
467
+#define s_RGA3_MMU_INT_CLEAR_PAGE_FAULT(x)			((x & 0x1) << 1)
350
468
 
351
469
 /* RGA3_MMU_INT_MASK */
352
-#define m_RGA3_MMU_INT_MASK_READ_BUS_ERROR			 (0x1 << 0)
353
-#define m_RGA3_MMU_INT_MASK_PAGE_FAULT				 (0x1 << 1)
470
+#define m_RGA3_MMU_INT_MASK_READ_BUS_ERROR			(0x1 << 0)
471
+#define m_RGA3_MMU_INT_MASK_PAGE_FAULT				(0x1 << 1)
354
472
 
355
-#define s_RGA3_MMU_INT_MASK_READ_BUS_ERROR(x)		 ((x & 0x1) << 0)
356
-#define s_RGA3_MMU_INT_MASK_PAGE_FAULT(x)		((x & 0x1) << 1)
473
+#define s_RGA3_MMU_INT_MASK_READ_BUS_ERROR(x)			((x & 0x1) << 0)
474
+#define s_RGA3_MMU_INT_MASK_PAGE_FAULT(x)			((x & 0x1) << 1)
357
475
 
358
476
 /* RGA3_MMU_INT_STATUS read_only */
359
-#define m_RGA3_MMU_INT_STATUS_READ_BUS_ERROR		(0x1 << 0)
477
+#define m_RGA3_MMU_INT_STATUS_READ_BUS_ERROR			(0x1 << 0)
360
478
 #define m_RGA3_MMU_INT_STATUS_PAGE_FAULT			(0x1 << 1)
361
479
 
362
480
 /* RGA3_MMU_AUTO_GATING */
363
-#define m_RGA3_MMU_AUTO_GATING_MMU_AUTO_GATING		 (0x1 << 1)
364
-#define m_RGA3_MMU_AUTO_GATING_MMU_CFG_MODE		(0x1 << 1)
365
-#define m_RGA3_MMU_AUTO_GATING_MMU_BUG_FIXED_DISABLE	(0x1 << 31)
481
+#define m_RGA3_MMU_AUTO_GATING_MMU_AUTO_GATING			(0x1 << 1)
482
+#define m_RGA3_MMU_AUTO_GATING_MMU_CFG_MODE			(0x1 << 1)
483
+#define m_RGA3_MMU_AUTO_GATING_MMU_BUG_FIXED_DISABLE		(0x1 << 31)
366
484
 
367
-#define s_RGA3_MMU_AUTO_GATING_MMU_AUTO_GATING(x)	 ((x & 0x1) << 1)
368
-#define s_RGA3_MMU_AUTO_GATING_MMU_BUG_FIXED_DISABLE(x) ((x & 0x1) << 31)
485
+#define s_RGA3_MMU_AUTO_GATING_MMU_AUTO_GATING(x)		((x & 0x1) << 1)
486
+#define s_RGA3_MMU_AUTO_GATING_MMU_BUG_FIXED_DISABLE(x)		((x & 0x1) << 31)
369
487
 
370
-/* sys_reg */
371
-#define RGA3_SYS_CTRL_OFFSET			 0x000
372
-#define RGA3_CMD_CTRL_OFFSET			 0x004
373
-#define RGA3_CMD_ADDR_OFFSET			 0x008
374
-#define RGA3_MI_GROUP_CTRL_OFFSET		 0x00c
375
-#define RGA3_ARQOS_CTRL_OFFSET			 0x010
376
-#define RGA3_VERSION_NUM_OFFSET			 0x018
377
-#define RGA3_VERSION_TIM_OFFSET			 0x01c
378
-#define RGA3_INT_EN_OFFSET				 0x020
379
-#define RGA3_INT_RAW_OFFSET				 0x024
380
-#define RGA3_INT_MSK_OFFSET				 0x028
381
-#define RGA3_INT_CLR_OFFSET				 0x02c
382
-#define RGA3_RO_SRST_OFFSET				 0x030
383
-#define RGA3_STATUS0_OFFSET				 0x034
384
-#define RGA3_SCAN_CNT_OFFSET			 0x038
385
-#define RGA3_STATUS1_OFFSET				 0x03c
386
-#define RGA3_CMD_STATE_OFFSET			 0x040
488
+#define RGA3_ROT_BIT_ROT_90			BIT(0)
489
+#define RGA3_ROT_BIT_X_MIRROR			BIT(1)
490
+#define RGA3_ROT_BIT_Y_MIRROR			BIT(2)
387
491
 
388
-/* op_reg */
389
-#define RGA3_WIN0_RD_CTRL_OFFSET		 0x000
390
-#define RGA3_WIN0_Y_BASE_OFFSET			 0x010
391
-#define RGA3_WIN0_U_BASE_OFFSET			 0x014
392
-#define RGA3_WIN0_V_BASE_OFFSET			 0x018
393
-#define RGA3_WIN0_VIR_STRIDE_OFFSET		 0x01c
394
-#define RGA3_WIN0_FBC_OFF_OFFSET		 0x020
395
-#define RGA3_WIN0_SRC_SIZE_OFFSET		 0x024
396
-#define RGA3_WIN0_ACT_OFF_OFFSET		 0x028
397
-#define RGA3_WIN0_ACT_SIZE_OFFSET		 0x02c
398
-#define RGA3_WIN0_DST_SIZE_OFFSET		 0x030
399
-#define RGA3_WIN0_SCL_FAC_OFFSET		 0x034
400
-#define RGA3_WIN0_UV_VIR_STRIDE_OFFSET	 0x038
401
-#define RGA3_WIN1_RD_CTRL_OFFSET		 0x040
402
-#define RGA3_WIN1_Y_BASE_OFFSET			 0x050
403
-#define RGA3_WIN1_U_BASE_OFFSET			 0x054
404
-#define RGA3_WIN1_V_BASE_OFFSET			 0x058
405
-#define RGA3_WIN1_VIR_STRIDE_OFFSET		 0x05c
406
-#define RGA3_WIN1_FBC_OFF_OFFSET		 0x060
407
-#define RGA3_WIN1_SRC_SIZE_OFFSET		 0x064
408
-#define RGA3_WIN1_ACT_OFF_OFFSET		 0x068
409
-#define RGA3_WIN1_ACT_SIZE_OFFSET		 0x06c
410
-#define RGA3_WIN1_DST_SIZE_OFFSET		 0x070
411
-#define RGA3_WIN1_SCL_FAC_OFFSET		 0x074
412
-#define RGA3_WIN1_UV_VIR_STRIDE_OFFSET	 0x078
413
-#define RGA3_OVLP_CTRL_OFFSET			 0x080
414
-#define RGA3_OVLP_OFF_OFFSET			 0x084
415
-#define RGA3_OVLP_TOP_KEY_MIN_OFFSET	 0x088
416
-#define RGA3_OVLP_TOP_KEY_MAX_OFFSET	 0x08c
417
-#define RGA3_OVLP_TOP_CTRL_OFFSET		 0x090
418
-#define RGA3_OVLP_BOT_CTRL_OFFSET		 0x094
419
-#define RGA3_OVLP_TOP_ALPHA_OFFSET		 0x098
420
-#define RGA3_OVLP_BOT_ALPHA_OFFSET		 0x09c
421
-#define RGA3_WR_CTRL_OFFSET				 0x0a0
422
-#define RGA3_WR_FBCE_CTRL_OFFSET		 0x0a4
423
-#define RGA3_WR_VIR_STRIDE_OFFSET		 0x0a8
424
-#define RGA3_WR_PL_VIR_STRIDE_OFFSET	 0x0ac
425
-#define RGA3_WR_Y_BASE_OFFSET			 0x0b0
426
-#define RGA3_WR_U_BASE_OFFSET			 0x0b4
427
-#define RGA3_WR_V_BASE_OFFSET			 0x0b8
428
-#define RGA3_MMU_DTE_ADDR_OFFSET		 0x0f00
429
-#define RGA3_MMU_STATUS_OFFSET			 0x0f04
430
-#define RGA3_MMU_COMMAND_OFFSET			 0x0f08
431
-#define RGA3_MMU_PAGE_FAULT_ADDR_OFFSET	 0x0f0c
432
-#define RGA3_MMU_ZAP_ONE_LINE_OFFSET	 0x0f10
433
-#define RGA3_MMU_INT_RAWSTAT_OFFSET		 0x0f14
434
-#define RGA3_MMU_INT_CLEAR_OFFSET		 0x0f18
435
-#define RGA3_MMU_INT_MASK_OFFSET		 0x0f1c
436
-#define RGA3_MMU_INT_STATUS_OFFSET		 0x0f20
437
-#define RGA3_MMU_AUTO_GATING_OFFSET		 0x0f24
438
-#define RGA3_MMU_REG_LOAD_EN_OFFSET		 0x0f28
439
-
440
-#define RGA3_ROT_BIT_ROT_90	BIT(0)
441
-#define RGA3_ROT_BIT_X_MIRROR	BIT(1)
442
-#define RGA3_ROT_BIT_Y_MIRROR	BIT(2)
443
-
444
-int rga3_gen_reg_info(unsigned char *base, struct rga3_req *msg);
445
-void rga_cmd_to_rga3_cmd(struct rga_req *req_rga, struct rga3_req *req);
446
-//void RGA_MSG_2_RGA3_MSG_32(struct rga_req_32 *req_rga, struct rga3_req *req);
447
-
448
-void rga3_soft_reset(struct rga_scheduler_t *scheduler);
449
-int rga3_set_reg(struct rga_job *job, struct rga_scheduler_t *scheduler);
450
-int rga3_init_reg(struct rga_job *job);
451
-int rga3_get_version(struct rga_scheduler_t *scheduler);
492
+extern const struct rga_backend_ops rga3_ops;
452
493
 
453
494
 #endif
454
495