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2023-11-23 7d07b3ae8ddad407913c5301877e694430a3263f 
 kernel/drivers/video/rockchip/rga3/include/rga2_reg_info.h
....@@ -4,38 +4,122 @@
44 
55 #include "rga_drv.h"
66 
7
-#define RGA2_USE_MASTER_MODE		1
7
+#define RGA2_SYS_REG_BASE			0x000
8
+#define RGA2_CSC_REG_BASE			0x060
9
+#define RGA2_CMD_REG_BASE			0x100
810 
9
-/* General Registers */
10
-#define RGA2_SYS_CTRL			0x000
11
-#define RGA2_CMD_CTRL			0x004
12
-#define RGA2_CMD_BASE			0x008
13
-#define RGA2_STATUS			0x00c
14
-#define RGA2_INT			0x010
15
-#define RGA2_MMU_CTRL0			0x018
16
-#define RGA2_MMU_CMD_BASE		0x01c
17
-#define RGA2_VERSION_NUM		0x028
11
+/* sys reg */
12
+#define RGA2_SYS_CTRL				0x000
13
+#define RGA2_CMD_CTRL				0x004
14
+#define RGA2_CMD_BASE				0x008
15
+#define RGA2_STATUS1				0x00c
16
+#define RGA2_INT				0x010
17
+#define RGA2_MMU_CTRL0				0x014
18
+#define RGA2_MMU_CMD_BASE			0x018
19
+#define RGA2_STATUS2				0x01c
20
+#define RGA2_VERSION_NUM			0x028
21
+#define RGA2_READ_LINE_CNT			0x030
22
+#define RGA2_WRITE_LINE_CNT			0x034
23
+#define RGA2_LINE_CNT				0x038
24
+#define RGA2_PERF_CTRL0				0x040
1825 
19
-#define rRGA_SYS_CTRL		(*(volatile u32 *)(RGA2_BASE + RGA2_SYS_CTRL_OFFSET))
20
-#define rRGA_CMD_CTRL		(*(volatile u32 *)(RGA2_BASE + RGA2_CMD_CTRL_OFFSET))
21
-#define rRGA_CMD_BASE		(*(volatile u32 *)(RGA2_BASE + RGA2_CMD_BASE_OFFSET))
22
-#define rRGA_STATUS		(*(volatile u32 *)(RGA2_BASE + RGA2_STATUS_OFFSET))
23
-#define rRGA_INT		(*(volatile u32 *)(RGA2_BASE + RGA2_INT_OFFSET))
24
-#define rRGA_MMU_CTRL0		(*(volatile u32 *)(RGA2_BASE + RGA2_MMU_CTRL0_OFFSET))
25
-#define rRGA_MMU_CMD_BASE	(*(volatile u32 *)(RGA2_BASE + RGA2_MMU_CMD_BASE_OFFSET))
26
-#define rRGA_CMD_ADDR		(*(volatile u32 *)(RGA2_BASE + RGA2_CMD_ADDR))
27
-#define rRGA_READ_LINE_CNT_TH	(*(volatile u32 *)(RGA2_BASE + RGA2_READ_LINE_CNT_OFFSET))
28
-#define rRGA_WRITE_LINE_CNT_TH	(*(volatile u32 *)(RGA2_BASE + RGA2_WRITE_LINE_CNT_OFFSET))
29
-#define rRGA_INT_LINE_CNT	(*(volatile u32 *)(RGA2_BASE + RGA2_LINE_CNT_OFFSET))
30
-#define rRGA_PERF_CTRL0		(*(volatile u32 *)(RGA2_BASE + RGA2_PERF_CTRL0_OFFSET))
31
-#define rRGA_OSD_CUR_FLAGS0	(*(volatile u32 *)(RGA2_BASE + RGA2_OSD_CUR_FLAGS0))
32
-#define rRGA_OSD_CUR_FLAGS1	(*(volatile u32 *)(RGA2_BASE + RGA2_OSD_CUR_FLAGS1))
26
+/* full csc reg */
27
+#define RGA2_DST_CSC_00				0x060
28
+#define RGA2_DST_CSC_01				0x064
29
+#define RGA2_DST_CSC_02				0x068
30
+#define RGA2_DST_CSC_OFF0			0x06c
31
+#define RGA2_DST_CSC_10				0x070
32
+#define RGA2_DST_CSC_11				0x074
33
+#define RGA2_DST_CSC_12				0x078
34
+#define RGA2_DST_CSC_OFF1			0x07c
35
+#define RGA2_DST_CSC_20				0x080
36
+#define RGA2_DST_CSC_21				0x084
37
+#define RGA2_DST_CSC_22				0x088
38
+#define RGA2_DST_CSC_OFF2			0x08c
39
+
40
+/* osd read-back reg */
41
+#define RGA2_OSD_CUR_FLAGS0			0x090
42
+#define RGA2_OSD_CUR_FLAGS1			0x09c
43
+
44
+/* mode ctrl */
45
+#define RGA2_MODE_CTRL_OFFSET			0x000
46
+#define RGA2_SRC_INFO_OFFSET			0x004
47
+#define RGA2_SRC_BASE0_OFFSET			0x008
48
+#define RGA2_SRC_BASE1_OFFSET			0x00c
49
+#define RGA2_SRC_BASE2_OFFSET			0x010
50
+#define RGA2_SRC_BASE3_OFFSET			0x014
51
+#define RGA2_SRC_VIR_INFO_OFFSET		0x018
52
+#define RGA2_SRC_ACT_INFO_OFFSET		0x01c
53
+#define RGA2_SRC_X_FACTOR_OFFSET		0x020
54
+#define RGA2_OSD_CTRL0_OFFSET			0x020 // repeat
55
+#define RGA2_SRC_Y_FACTOR_OFFSET		0x024
56
+#define RGA2_OSD_CTRL1_OFFSET			0x024 // repeat
57
+#define RGA2_SRC_BG_COLOR_OFFSET		0x028
58
+#define RGA2_OSD_COLOR0_OFFSET			0x028 // repeat
59
+#define RGA2_SRC_FG_COLOR_OFFSET		0x02c
60
+#define RGA2_OSD_COLOR1_OFFSET			0x02c // repeat
61
+#define RGA2_SRC_TR_COLOR0_OFFSET		0x030
62
+#define RGA2_CF_GR_A_OFFSET			0x030 // repeat
63
+#define RGA2_OSD_LAST_FLAGS0_OFFSET		0x030 // repeat
64
+#define RGA2_MOSAIC_MODE_OFFSET			0x030 // repeat
65
+#define RGA2_SRC_TR_COLOR1_OFFSET		0x034
66
+#define RGA2_CF_GR_B_OFFSET			0x034 // repeat
67
+#define RGA2_OSD_LAST_FLAGS1_OFFSET		0x034 // repeat
68
+#define RGA2_DST_INFO_OFFSET			0x038
69
+#define RGA2_DST_BASE0_OFFSET			0x03c
70
+#define RGA2_DST_BASE1_OFFSET			0x040
71
+#define RGA2_DST_BASE2_OFFSET			0x044
72
+#define RGA2_DST_VIR_INFO_OFFSET		0x048
73
+#define RGA2_DST_ACT_INFO_OFFSET		0x04c
74
+#define RGA2_ALPHA_CTRL0_OFFSET			0x050
75
+#define RGA2_ALPHA_CTRL1_OFFSET			0x054
76
+#define RGA2_FADING_CTRL_OFFSET			0x058
77
+#define RGA2_PAT_CON_OFFSET			0x05c
78
+#define RGA2_ROP_CTRL0_OFFSET			0x060
79
+#define RGA2_CF_GR_G_OFFSET			0x060 // repeat
80
+#define RGA2_DST_Y4MAP_LUT0_OFFSET		0x060 // repeat
81
+#define RGA2_DST_QUANTIZE_SCALE_OFFSET		0x060 // repeat
82
+#define RGA2_OSD_INVERTSION_CAL0_OFFSET		0x060 // repeat
83
+#define RGA2_ROP_CTRL1_OFFSET			0x064
84
+#define RGA2_CF_GR_R_OFFSET			0x064 // repeat
85
+#define RGA2_DST_Y4MAP_LUT1_OFFSET		0x064 // repeat
86
+#define RGA2_DST_QUANTIZE_OFFSET_OFFSET		0x064 // repeat
87
+#define RGA2_OSD_INVERTSION_CAL1_OFFSET		0x064 // repeat
88
+#define RGA2_MASK_BASE_OFFSET			0x068
89
+#define RGA2_MMU_CTRL1_OFFSET			0x06c
90
+#define RGA2_MMU_SRC_BASE_OFFSET		0x070
91
+#define RGA2_MMU_SRC1_BASE_OFFSET		0x074
92
+#define RGA2_MMU_DST_BASE_OFFSET		0x078
93
+#define RGA2_MMU_ELS_BASE_OFFSET		0x07c
3394 
3495 /*RGA_SYS*/
35
-#define m_RGA2_SYS_HOLD_MODE_EN				(1 << 9)
96
+#define m_RGA2_SYS_CTRL_SRC0YUV420SP_RD_OPT_DIS		(0x1 << 12)
97
+#define m_RGA2_SYS_CTRL_DST_WR_OPT_DIS			(0x1 << 11)
98
+#define m_RGA2_SYS_CTRL_CMD_CONTINUE_P			(0x1 << 10)
99
+#define m_RGA2_SYS_CTRL_HOLD_MODE_EN			(0x1 << 9)
100
+#define m_RGA2_SYS_CTRL_RST_HANDSAVE_P			(0x1 << 7)
101
+#define m_RGA2_SYS_CTRL_RST_PROTECT_P			(0x1 << 6)
102
+#define m_RGA2_SYS_CTRL_AUTO_RST			(0x1 << 5)
103
+#define m_RGA2_SYS_CTRL_CCLK_SRESET_P			(0x1 << 4)
104
+#define m_RGA2_SYS_CTRL_ACLK_SRESET_P			(0x1 << 3)
105
+#define m_RGA2_SYS_CTRL_AUTO_CKG			(0x1 << 2)
106
+#define m_RGA2_SYS_CTRL_CMD_MODE			(0x1 << 1)
107
+#define m_RGA2_SYS_CTRL_CMD_OP_ST_P			(0x1 << 0)
36108 
37
-#define s_RGA2_SYS_HOLD_MODE_EN(x)			((x & 0x1) << 9)
38
-#define s_RGA2_SYS_CMD_CONTINUE(x)			((x & 0x1) << 10)
109
+#define s_RGA2_SYS_CTRL_CMD_CONTINUE(x)			((x & 0x1) << 10)
110
+#define s_RGA2_SYS_CTRL_HOLD_MODE_EN(x)			((x & 0x1) << 9)
111
+#define s_RGA2_SYS_CTRL_CMD_MODE(x)			((x & 0x1) << 1)
112
+
113
+/* RGA_CMD_CTRL */
114
+#define m_RGA2_CMD_CTRL_INCR_NUM			(0x3ff << 3)
115
+#define m_RGA2_CMD_CTRL_STOP				(0x1 << 2)
116
+#define m_RGA2_CMD_CTRL_INCR_VALID_P			(0x1 << 1)
117
+#define m_RGA2_CMD_CTRL_CMD_LINE_ST_P			(0x1 << 0)
118
+
119
+/* RGA_STATUS1 */
120
+#define m_RGA2_STATUS1_SW_CMD_TOTAL_NUM			(0xfff << 8)
121
+#define m_RGA2_STATUS1_SW_CMD_CUR_NUM			(0xfff << 8)
122
+#define m_RGA2_STATUS1_SW_RGA_STA			(0x1 << 0)
39123 
40124 /*RGA_INT*/
41125 #define m_RGA2_INT_LINE_WR_CLEAR			(1 << 16)
....@@ -56,6 +140,22 @@
56140 #define m_RGA2_INT_MMU_INT_FLAG				(1 << 1)
57141 #define m_RGA2_INT_ERROR_INT_FLAG			(1 << 0)
58142 
143
+#define m_RGA2_INT_ERROR_FLAG_MASK \
144
+	( \
145
+		m_RGA2_INT_MMU_INT_FLAG | \
146
+		m_RGA2_INT_ERROR_INT_FLAG \
147
+	)
148
+#define m_RGA2_INT_ERROR_CLEAR_MASK \
149
+	( \
150
+	m_RGA2_INT_MMU_INT_CLEAR | \
151
+	m_RGA2_INT_ERROR_INT_CLEAR \
152
+)
153
+#define m_RGA2_INT_ERROR_ENABLE_MASK \
154
+	( \
155
+		m_RGA2_INT_MMU_INT_EN | \
156
+		m_RGA2_INT_ERROR_INT_EN \
157
+	)
158
+
59159 #define s_RGA2_INT_LINE_WR_CLEAR(x)			((x & 0x1) << 16)
60160 #define s_RGA2_INT_LINE_RD_CLEAR(x)			((x & 0x1) << 15)
61161 #define s_RGA2_INT_LINE_WR_EN(x)			((x & 0x1) << 14)
....@@ -67,6 +167,13 @@
67167 #define s_RGA2_INT_ALL_CMD_DONE_INT_CLEAR(x)		((x & 0x1) << 6)
68168 #define s_RGA2_INT_MMU_INT_CLEAR(x)			((x & 0x1) << 5)
69169 #define s_RGA2_INT_ERROR_INT_CLEAR(x)			((x & 0x1) << 4)
170
+
171
+/* RGA_STATUS2 hardware status */
172
+#define m_RGA2_STATUS2_RPP_MKRAM_RREADY			(0x2 << 11)
173
+#define m_RGA2_STATUS2_DSTRPP_OUTBUF_RREADY		(0x1f << 6)
174
+#define m_RGA2_STATUS2_SRCRPP_OUTBUF_RREADY		(0xf << 2)
175
+#define m_RGA2_STATUS2_BUS_ERROR			(0x1 << 1)
176
+#define m_RGA2_STATUS2_RPP_ERROR			(0x1 << 0)
70177 
71178 /* RGA_READ_LINE_CNT_TH */
72179 #define m_RGA2_READ_LINE_SW_INTR_LINE_RD_TH		(0x1fff << 0)
....@@ -325,95 +432,9 @@
325432 #define s_RGA2_MMU_CTRL1_SW_ELS_MMU_EN(x)		((x & 0x1) << 12)
326433 #define s_RGA2_MMU_CTRL1_SW_ELS_MMU_FLUSH(x)		((x & 0x1) << 13)
327434 
328
-/* sys ctrl */
329
-#define RGA2_SYS_CTRL_OFFSET				0x0
330
-#define RGA2_CMD_CTRL_OFFSET				0x4
331
-#define RGA2_CMD_BASE_OFFSET				0x8
332
-#define RGA2_STATUS_OFFSET				0xc
333
-#define RGA2_INT_OFFSET					0x10
334
-#define RGA2_MMU_CTRL0_OFFSET				0x14
335
-#define RGA2_MMU_CMD_BASE_OFFSET			0x18
336
-#define RGA2_READ_LINE_CNT_OFFSET			0x30
337
-#define RGA2_WRITE_LINE_CNT_OFFSET			0x34
338
-#define RGA2_LINE_CNT_OFFSET				0x38
339
-#define RGA2_PERF_CTRL0_OFFSET				0x40
340
-#define RGA2_DST_CSC_00_OFFSET				0x60
341
-#define RGA2_DST_CSC_01_OFFSET				0x64
342
-#define RGA2_DST_CSC_02_OFFSET				0x68
343
-#define RGA2_DST_CSC_OFF0_OFFSET			0x6c
344
-#define RGA2_DST_CSC_10_OFFSET				0x70
345
-#define RGA2_DST_CSC_11_OFFSET				0x74
346
-#define RGA2_DST_CSC_12_OFFSET				0x78
347
-#define RGA2_DST_CSC_OFF1_OFFSET			0x7c
348
-#define RGA2_DST_CSC_20_OFFSET				0x80
349
-#define RGA2_DST_CSC_21_OFFSET				0x84
350
-#define RGA2_DST_CSC_22_OFFSET				0x88
351
-#define RGA2_DST_CSC_OFF2_OFFSET			0x8c
352
-#define RGA2_OSD_CUR_FLAGS0_OFFSET			0x90
353
-#define RGA2_OSD_CUR_FLAGS1_OFFSET			0x9c
435
+#define RGA2_VSP_BICUBIC_LIMIT				1996
354436 
355
-/* mode ctrl */
356
-#define RGA2_MODE_CTRL_OFFSET				0x00
357
-#define RGA2_SRC_INFO_OFFSET				0x04
358
-#define RGA2_SRC_BASE0_OFFSET				0x08
359
-#define RGA2_SRC_BASE1_OFFSET				0x0c
360
-#define RGA2_SRC_BASE2_OFFSET				0x10
361
-#define RGA2_SRC_BASE3_OFFSET				0x14
362
-#define RGA2_SRC_VIR_INFO_OFFSET			0x18
363
-#define RGA2_SRC_ACT_INFO_OFFSET			0x1c
364
-#define RGA2_SRC_X_FACTOR_OFFSET			0x20
365
-#define RGA2_OSD_CTRL0_OFFSET				0x20 // repeat
366
-#define RGA2_SRC_Y_FACTOR_OFFSET			0x24
367
-#define RGA2_OSD_CTRL1_OFFSET				0x24 // repeat
368
-#define RGA2_SRC_BG_COLOR_OFFSET			0x28
369
-#define RGA2_OSD_COLOR0_OFFSET				0x28 // repeat
370
-#define RGA2_SRC_FG_COLOR_OFFSET			0x2c
371
-#define RGA2_OSD_COLOR1_OFFSET				0x2c // repeat
372
-#define RGA2_SRC_TR_COLOR0_OFFSET			0x30
373
-#define RGA2_CF_GR_A_OFFSET				0x30 // repeat
374
-#define RGA2_OSD_LAST_FLAGS0_OFFSET			0x30 // repeat
375
-#define RGA2_MOSAIC_MODE_OFFSET				0x30 // repeat
376
-#define RGA2_SRC_TR_COLOR1_OFFSET			0x34
377
-#define RGA2_CF_GR_B_OFFSET				0x34 // repeat
378
-#define RGA2_OSD_LAST_FLAGS1_OFFSET			0x34 // repeat
379
-#define RGA2_DST_INFO_OFFSET				0x38
380
-#define RGA2_DST_BASE0_OFFSET				0x3c
381
-#define RGA2_DST_BASE1_OFFSET				0x40
382
-#define RGA2_DST_BASE2_OFFSET				0x44
383
-#define RGA2_DST_VIR_INFO_OFFSET			0x48
384
-#define RGA2_DST_ACT_INFO_OFFSET			0x4c
385
-#define RGA2_ALPHA_CTRL0_OFFSET				0x50
386
-#define RGA2_ALPHA_CTRL1_OFFSET				0x54
387
-#define RGA2_FADING_CTRL_OFFSET				0x58
388
-#define RGA2_PAT_CON_OFFSET				0x5c
389
-#define RGA2_ROP_CTRL0_OFFSET				0x60
390
-#define RGA2_CF_GR_G_OFFSET				0x60 // repeat
391
-#define RGA2_DST_Y4MAP_LUT0_OFFSET			0x60 // repeat
392
-#define RGA2_DST_QUANTIZE_SCALE_OFFSET			0x60 // repeat
393
-#define RGA2_OSD_INVERTSION_CAL0_OFFSET			0x60 // repeat
394
-#define RGA2_ROP_CTRL1_OFFSET				0x64
395
-#define RGA2_CF_GR_R_OFFSET				0x64 // repeat
396
-#define RGA2_DST_Y4MAP_LUT1_OFFSET			0x64 // repeat
397
-#define RGA2_DST_QUANTIZE_OFFSET_OFFSET			0x64 // repeat
398
-#define RGA2_OSD_INVERTSION_CAL1_OFFSET			0x64 // repeat
399
-#define RGA2_MASK_BASE_OFFSET				0x68
400
-#define RGA2_MMU_CTRL1_OFFSET				0x6c
401
-#define RGA2_MMU_SRC_BASE_OFFSET			0x70
402
-#define RGA2_MMU_SRC1_BASE_OFFSET			0x74
403
-#define RGA2_MMU_DST_BASE_OFFSET			0x78
404
-#define RGA2_MMU_ELS_BASE_OFFSET			0x7c
405
-
406
-#define RGA2_SYS_REG_BASE				0x0
407
-#define RGA2_CSC_REG_BASE				0x60
408
-#define RGA2_CMD_REG_BASE				0x100
409
-
410
-int rga2_gen_reg_info(unsigned char *base, struct rga2_req *msg);
411
-
412
-void rga2_soft_reset(struct rga_scheduler_t *scheduler);
413
-int rga2_set_reg(struct rga_job *job, struct rga_scheduler_t *scheduler);
414
-int rga2_init_reg(struct rga_job *job);
415
-int rga2_get_version(struct rga_scheduler_t *scheduler);
416
-void rga2_dump_read_back_reg(struct rga_scheduler_t *scheduler);
437
+extern const struct rga_backend_ops rga2_ops;
417438 
418439 #endif
419440