forked from ~ljy/RK356X_SDK_RELEASE
blame | history | patch | commit | commitdiff
hc
2023-11-23 7d07b3ae8ddad407913c5301877e694430a3263f 
 kernel/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
....@@ -24,6 +24,7 @@
2424 #define VOP_MAJOR(version)		((version) >> 8)
2525 #define VOP_MINOR(version)		((version) & 0xff)
2626 
27
+#define VOP_VERSION_RK3528	VOP_VERSION(0x50, 0x17)
2728 #define VOP_VERSION_RK3568	VOP_VERSION(0x40, 0x15)
2829 #define VOP_VERSION_RK3588	VOP_VERSION(0x40, 0x17)
2930 
....@@ -42,6 +43,9 @@
4243 /* a feature to splice two windows and two vps to support resolution > 4096 */
4344 #define VOP_FEATURE_SPLICE		BIT(5)
4445 #define VOP_FEATURE_OVERSCAN		BIT(6)
46
+#define VOP_FEATURE_VIVID_HDR		BIT(7)
47
+#define VOP_FEATURE_POST_ACM		BIT(8)
48
+#define VOP_FEATURE_POST_CSC		BIT(9)
4549 
4650 #define WIN_FEATURE_HDR2SDR		BIT(0)
4751 #define WIN_FEATURE_SDR2HDR		BIT(1)
....@@ -92,10 +96,10 @@
9296 };
9397 
9498 enum vop3_esmart_lb_mode {
95
-	VOP3_ESMART_ONE_8K_MODE,
96
-	VOP3_ESMART_TWO_4K_MODE,
97
-	VOP3_ESMART_ONE_4K_AND_TWO_2K_MODE,
98
-	VOP3_ESMART_FOUR_2K_MODE,
99
+	VOP3_ESMART_8K_MODE,
100
+	VOP3_ESMART_4K_4K_MODE,
101
+	VOP3_ESMART_4K_2K_2K_MODE,
102
+	VOP3_ESMART_2K_2K_2K_2K_MODE,
99103 };
100104 
101105 #define DSP_BG_SWAP		0x1
....@@ -439,6 +443,104 @@
439443 	const uint32_t *sdr2hdr_st2084oetf_xn;
440444 };
441445 
446
+#define RK_HDRVIVID_TONE_SCA_TAB_LENGTH		257
447
+#define RK_HDRVIVID_GAMMA_CURVE_LENGTH		81
448
+#define RK_HDRVIVID_GAMMA_MDFVALUE_LENGTH	9
449
+#define RK_SDR2HDR_INVGAMMA_CURVE_LENGTH	69
450
+#define RK_SDR2HDR_INVGAMMA_S_IDX_LENGTH	6
451
+#define RK_SDR2HDR_INVGAMMA_C_IDX_LENGTH	6
452
+#define RK_SDR2HDR_SMGAIN_LENGTH		64
453
+#define RK_HDRVIVID_TONE_SCA_AXI_TAB_LENGTH	264
454
+
455
+struct hdrvivid_regs {
456
+	uint32_t sdr2hdr_ctrl;
457
+	uint32_t sdr2hdr_coe0;
458
+	uint32_t sdr2hdr_coe1;
459
+	uint32_t sdr2hdr_csc_coe00_01;
460
+	uint32_t sdr2hdr_csc_coe02_10;
461
+	uint32_t sdr2hdr_csc_coe11_12;
462
+	uint32_t sdr2hdr_csc_coe20_21;
463
+	uint32_t sdr2hdr_csc_coe22;
464
+	uint32_t hdrvivid_ctrl;
465
+	uint32_t hdr_pq_gamma;
466
+	uint32_t hlg_rfix_scalefac;
467
+	uint32_t hlg_maxluma;
468
+	uint32_t hlg_r_tm_lin2non;
469
+	uint32_t hdr_csc_coe00_01;
470
+	uint32_t hdr_csc_coe02_10;
471
+	uint32_t hdr_csc_coe11_12;
472
+	uint32_t hdr_csc_coe20_21;
473
+	uint32_t hdr_csc_coe22;
474
+	uint32_t hdr_tone_sca[RK_HDRVIVID_TONE_SCA_TAB_LENGTH];
475
+	uint32_t hdrgamma_curve[RK_HDRVIVID_GAMMA_CURVE_LENGTH];
476
+	uint32_t hdrgamma_mdfvalue[RK_HDRVIVID_GAMMA_MDFVALUE_LENGTH];
477
+	uint32_t sdrinvgamma_curve[RK_SDR2HDR_INVGAMMA_CURVE_LENGTH];
478
+	uint32_t sdrinvgamma_startidx[RK_SDR2HDR_INVGAMMA_S_IDX_LENGTH];
479
+	uint32_t sdrinvgamma_changeidx[RK_SDR2HDR_INVGAMMA_C_IDX_LENGTH];
480
+	uint32_t sdr_smgain[RK_SDR2HDR_SMGAIN_LENGTH];
481
+	uint32_t hdr_mode;
482
+	uint32_t tone_sca_axi_tab[RK_HDRVIVID_TONE_SCA_AXI_TAB_LENGTH];
483
+};
484
+
485
+struct hdr_extend {
486
+	uint32_t hdr_type;
487
+	uint32_t length;
488
+	union {
489
+		struct hdrvivid_regs hdrvivid_data;
490
+	};
491
+};
492
+
493
+enum _vop_hdrvivid_mode {
494
+	PQHDR2HDR_WITH_DYNAMIC = 0,
495
+	PQHDR2SDR_WITH_DYNAMIC,
496
+	HLG2PQHDR_WITH_DYNAMIC,
497
+	HLG2SDR_WITH_DYNAMIC,
498
+	HLG2PQHDR_WITHOUT_DYNAMIC,
499
+	HLG2SDR_WITHOUT_DYNAMIC,
500
+	HDR_BYPASS,
501
+	HDR102SDR,
502
+	SDR2HDR10,
503
+	SDR2HLG,
504
+	SDR2HDR10_USERSPACE = 100,
505
+	SDR2HLG_USERSPACE = 101,
506
+};
507
+
508
+enum vop_hdr_format {
509
+	HDR_NONE = 0,
510
+	HDR_HDR10 = 1,
511
+	HDR_HLGSTATIC = 2,
512
+	RESERVED3 = 3,		/* reserved for more future static hdr format */
513
+	RESERVED4 = 4,		/* reserved for more future static hdr format */
514
+	HDR_HDRVIVID = 5,
515
+	RESERVED6 = 6,		/* reserved for hdr vivid */
516
+	RESERVED7 = 7,		/* reserved for hdr vivid */
517
+	HDR_HDR10PLUS = 8,
518
+	RESERVED9 = 9,		/* reserved for hdr hdr10+ */
519
+	RESERVED10 = 10,	/* reserved for hdr hdr10+ */
520
+	HDR_NEXT = 11,
521
+	RESERVED12 = 12,	/* reserved for other dynamic hdr format */
522
+	RESERVED13 = 13,	/* reserved for other dynamic hdr format */
523
+	HDR_FORMAT_MAX,
524
+};
525
+
526
+struct post_csc_coef {
527
+	s32 csc_coef00;
528
+	s32 csc_coef01;
529
+	s32 csc_coef02;
530
+	s32 csc_coef10;
531
+	s32 csc_coef11;
532
+	s32 csc_coef12;
533
+	s32 csc_coef20;
534
+	s32 csc_coef21;
535
+	s32 csc_coef22;
536
+
537
+	s32 csc_dc0;
538
+	s32 csc_dc1;
539
+	s32 csc_dc2;
540
+
541
+	u32 range_type;
542
+};
543
+
442544 enum {
443545 	VOP_CSC_Y2R_BT601,
444546 	VOP_CSC_Y2R_BT709,
....@@ -509,6 +611,8 @@
509611 	struct vop_reg enable;
510612 	struct vop_reg afbc_enable;
511613 	struct vop_reg lb_mode;
614
+	struct vop_reg scl_lb_mode;
615
+	struct vop_reg frm_reset_en;
512616 
513617 	struct vop_reg src_color_ctrl;
514618 	struct vop_reg dst_color_ctrl;
....@@ -626,6 +730,13 @@
626730 	struct vop_reg hdr_lut_update_en;
627731 	struct vop_reg hdr_lut_mode;
628732 	struct vop_reg hdr_lut_mst;
733
+	struct vop_reg hdr_lut_fetch_done;
734
+	struct vop_reg hdr_vivid_en;
735
+	struct vop_reg hdr_vivid_bypass_en;
736
+	struct vop_reg hdr_vivid_path_mode;
737
+	struct vop_reg hdr_vivid_dstgamut;
738
+	struct vop_reg sdr2hdr_en;
739
+	struct vop_reg sdr2hdr_dstmode;
629740 	struct vop_reg sdr2hdr_eotf_en;
630741 	struct vop_reg sdr2hdr_r2r_en;
631742 	struct vop_reg sdr2hdr_r2r_mode;
....@@ -677,6 +788,25 @@
677788 	struct vop_reg edpi_wms_fs;
678789 	struct vop_reg gamma_update_en;
679790 	struct vop_reg lut_dma_rid;
791
+
792
+	/* CSC */
793
+	struct vop_reg acm_bypass_en;
794
+	struct vop_reg csc_en;
795
+	struct vop_reg acm_r2y_en;
796
+	struct vop_reg csc_mode;
797
+	struct vop_reg acm_r2y_mode;
798
+	struct vop_reg csc_coe00;
799
+	struct vop_reg csc_coe01;
800
+	struct vop_reg csc_coe02;
801
+	struct vop_reg csc_coe10;
802
+	struct vop_reg csc_coe11;
803
+	struct vop_reg csc_coe12;
804
+	struct vop_reg csc_coe20;
805
+	struct vop_reg csc_coe21;
806
+	struct vop_reg csc_coe22;
807
+	struct vop_reg csc_offset0;
808
+	struct vop_reg csc_offset1;
809
+	struct vop_reg csc_offset2;
680810 };
681811 
682812 struct vop2_wb_regs {
....@@ -711,7 +841,6 @@
711841 	uint8_t axi_id;
712842 	uint8_t axi_yrgb_id;
713843 	uint8_t axi_uv_id;
714
-	uint8_t scale_engine_num;
715844 	uint8_t possible_crtcs;
716845 
717846 	uint32_t base;
....@@ -775,6 +904,11 @@
775904 	uint16_t cubic_lut_len;
776905 	struct vop_rect max_output;
777906 	const u8 pre_scan_max_dly[4];
907
+	const u8 hdrvivid_dly[10];
908
+	const u8 sdr2hdr_dly;
909
+	const u8 layer_mix_dly;
910
+	const u8 hdr_mix_dly;
911
+	const u8 win_dly;
778912 	const struct vop_intr *intr;
779913 	const struct vop_hdr_table *hdr_table;
780914 	const struct vop2_video_port_regs *regs;
....@@ -849,6 +983,7 @@
849983 	struct vop_reg version;
850984 	struct vop_reg standby;
851985 	struct vop_reg dma_stop;
986
+	struct vop_reg dsp_vs_t_sel;
852987 	struct vop_reg lut_dma_en;
853988 	struct vop_reg axi_outstanding_max_num;
854989 	struct vop_reg axi_max_outstanding_en;