add gpio led uart

hc

2024-05-10 748e4f3d702def1a4bff191e0cf93b6a05340f01

 kernel/tools/perf/pmu-events/arch/x86/haswell/cache.json
..
..
@@ -63,10 +63,10 @@
63
63
         "CounterHTOff": "0,1,2,3,4,5,6,7"
64
64
     },
65
65
     {
66
-        "PublicDescription": "Demand data read requests that hit L2 cache.",
66
+        "PublicDescription": "Counts the number of demand Data Read requests, initiated by load instructions, that hit L2 cache",
67
67
         "EventCode": "0x24",
68
68
         "Counter": "0,1,2,3",
69
-        "UMask": "0x41",
69
+        "UMask": "0xc1",
70
70
         "Errata": "HSD78",
71
71
         "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",
72
72
         "SampleAfterValue": "200003",
..
..
@@ -77,7 +77,7 @@
77
77
         "PublicDescription": "Counts the number of store RFO requests that hit the L2 cache.",
78
78
         "EventCode": "0x24",
79
79
         "Counter": "0,1,2,3",
80
-        "UMask": "0x42",
80
+        "UMask": "0xc2",
81
81
         "EventName": "L2_RQSTS.RFO_HIT",
82
82
         "SampleAfterValue": "200003",
83
83
         "BriefDescription": "RFO requests that hit L2 cache",
..
..
@@ -87,7 +87,7 @@
87
87
         "PublicDescription": "Number of instruction fetches that hit the L2 cache.",
88
88
         "EventCode": "0x24",
89
89
         "Counter": "0,1,2,3",
90
-        "UMask": "0x44",
90
+        "UMask": "0xc4",
91
91
         "EventName": "L2_RQSTS.CODE_RD_HIT",
92
92
         "SampleAfterValue": "200003",
93
93
         "BriefDescription": "L2 cache hits when fetching instructions, code reads.",
..
..
@@ -97,7 +97,7 @@
97
97
         "PublicDescription": "Counts all L2 HW prefetcher requests that hit L2.",
98
98
         "EventCode": "0x24",
99
99
         "Counter": "0,1,2,3",
100
-        "UMask": "0x50",
100
+        "UMask": "0xd0",
101
101
         "EventName": "L2_RQSTS.L2_PF_HIT",
102
102
         "SampleAfterValue": "200003",
103
103
         "BriefDescription": "L2 prefetch requests that hit L2 cache",
..
..
@@ -610,7 +610,7 @@
610
610
         "Errata": "HSD29, HSD25, HSM26, HSM30",
611
611
         "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT",
612
612
         "SampleAfterValue": "20011",
613
-        "BriefDescription": "Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache. ",
613
+        "BriefDescription": "Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache.",
614
614
         "CounterHTOff": "0,1,2,3",
615
615
         "Data_LA": "1"
616
616
     },
..
..
@@ -623,7 +623,7 @@
623
623
         "Errata": "HSD29, HSD25, HSM26, HSM30",
624
624
         "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM",
625
625
         "SampleAfterValue": "20011",
626
-        "BriefDescription": "Retired load uops which data sources were HitM responses from shared L3. ",
626
+        "BriefDescription": "Retired load uops which data sources were HitM responses from shared L3.",
627
627
         "CounterHTOff": "0,1,2,3",
628
628
         "Data_LA": "1"
629
629
     },
..
..
@@ -792,7 +792,6 @@
792
792
         "CounterHTOff": "0,1,2,3,4,5,6,7"
793
793
     },
794
794
     {
795
-        "PublicDescription": "",
796
795
         "EventCode": "0xf4",
797
796
         "Counter": "0,1,2,3",
798
797
         "UMask": "0x10",
..
..
@@ -802,262 +801,262 @@
802
801
         "CounterHTOff": "0,1,2,3,4,5,6,7"
803
802
     },
804
803
     {
805
-        "PublicDescription": "Counts all requests that hit in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
804
+        "PublicDescription": "Counts all requests hit in the L3",
806
805
         "EventCode": "0xB7, 0xBB",
807
-        "MSRValue": "0x3f803c8fff",
806
+        "MSRValue": "0x3F803C8FFF",
808
807
         "Counter": "0,1,2,3",
809
808
         "UMask": "0x1",
810
809
         "EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.L3_HIT.ANY_RESPONSE",
811
-        "MSRIndex": "0x1a6,0x1a7",
810
+        "MSRIndex": "0x1a6, 0x1a7",
812
811
         "SampleAfterValue": "100003",
813
-        "BriefDescription": "Counts all requests that hit in the L3",
812
+        "BriefDescription": "Counts all requests hit in the L3",
814
813
         "Offcore": "1",
815
814
         "CounterHTOff": "0,1,2,3"
816
815
     },
817
816
     {
818
-        "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
817
+        "PublicDescription": "hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
819
818
         "EventCode": "0xB7, 0xBB",
820
-        "MSRValue": "0x10003c07f7",
819
+        "MSRValue": "0x10003C07F7",
821
820
         "Counter": "0,1,2,3",
822
821
         "UMask": "0x1",
823
822
         "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT.HITM_OTHER_CORE",
824
-        "MSRIndex": "0x1a6,0x1a7",
823
+        "MSRIndex": "0x1a6, 0x1a7",
825
824
         "SampleAfterValue": "100003",
826
-        "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
825
+        "BriefDescription": "hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
827
826
         "Offcore": "1",
828
827
         "CounterHTOff": "0,1,2,3"
829
828
     },
830
829
     {
831
-        "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
830
+        "PublicDescription": "hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
832
831
         "EventCode": "0xB7, 0xBB",
833
-        "MSRValue": "0x04003c07f7",
832
+        "MSRValue": "0x04003C07F7",
834
833
         "Counter": "0,1,2,3",
835
834
         "UMask": "0x1",
836
835
         "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD",
837
-        "MSRIndex": "0x1a6,0x1a7",
836
+        "MSRIndex": "0x1a6, 0x1a7",
838
837
         "SampleAfterValue": "100003",
839
-        "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
838
+        "BriefDescription": "hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
840
839
         "Offcore": "1",
841
840
         "CounterHTOff": "0,1,2,3"
842
841
     },
843
842
     {
844
-        "PublicDescription": "Counts all demand & prefetch code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
843
+        "PublicDescription": "Counts all demand & prefetch code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
845
844
         "EventCode": "0xB7, 0xBB",
846
-        "MSRValue": "0x04003c0244",
845
+        "MSRValue": "0x04003C0244",
847
846
         "Counter": "0,1,2,3",
848
847
         "UMask": "0x1",
849
848
         "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
850
-        "MSRIndex": "0x1a6,0x1a7",
849
+        "MSRIndex": "0x1a6, 0x1a7",
851
850
         "SampleAfterValue": "100003",
852
-        "BriefDescription": "Counts all demand & prefetch code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
851
+        "BriefDescription": "Counts all demand & prefetch code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
853
852
         "Offcore": "1",
854
853
         "CounterHTOff": "0,1,2,3"
855
854
     },
856
855
     {
857
-        "PublicDescription": "Counts all demand & prefetch RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
856
+        "PublicDescription": "Counts all demand & prefetch RFOs hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
858
857
         "EventCode": "0xB7, 0xBB",
859
-        "MSRValue": "0x10003c0122",
858
+        "MSRValue": "0x10003C0122",
860
859
         "Counter": "0,1,2,3",
861
860
         "UMask": "0x1",
862
861
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.HITM_OTHER_CORE",
863
-        "MSRIndex": "0x1a6,0x1a7",
862
+        "MSRIndex": "0x1a6, 0x1a7",
864
863
         "SampleAfterValue": "100003",
865
-        "BriefDescription": "Counts all demand & prefetch RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
864
+        "BriefDescription": "Counts all demand & prefetch RFOs hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
866
865
         "Offcore": "1",
867
866
         "CounterHTOff": "0,1,2,3"
868
867
     },
869
868
     {
870
-        "PublicDescription": "Counts all demand & prefetch RFOs that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
869
+        "PublicDescription": "Counts all demand & prefetch RFOs hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
871
870
         "EventCode": "0xB7, 0xBB",
872
-        "MSRValue": "0x04003c0122",
871
+        "MSRValue": "0x04003C0122",
873
872
         "Counter": "0,1,2,3",
874
873
         "UMask": "0x1",
875
874
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
876
-        "MSRIndex": "0x1a6,0x1a7",
875
+        "MSRIndex": "0x1a6, 0x1a7",
877
876
         "SampleAfterValue": "100003",
878
-        "BriefDescription": "Counts all demand & prefetch RFOs that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
877
+        "BriefDescription": "Counts all demand & prefetch RFOs hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
879
878
         "Offcore": "1",
880
879
         "CounterHTOff": "0,1,2,3"
881
880
     },
882
881
     {
883
-        "PublicDescription": "Counts all demand & prefetch data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
882
+        "PublicDescription": "Counts all demand & prefetch data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
884
883
         "EventCode": "0xB7, 0xBB",
885
-        "MSRValue": "0x10003c0091",
884
+        "MSRValue": "0x10003C0091",
886
885
         "Counter": "0,1,2,3",
887
886
         "UMask": "0x1",
888
887
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE",
889
-        "MSRIndex": "0x1a6,0x1a7",
888
+        "MSRIndex": "0x1a6, 0x1a7",
890
889
         "SampleAfterValue": "100003",
891
-        "BriefDescription": "Counts all demand & prefetch data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
890
+        "BriefDescription": "Counts all demand & prefetch data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
892
891
         "Offcore": "1",
893
892
         "CounterHTOff": "0,1,2,3"
894
893
     },
895
894
     {
896
-        "PublicDescription": "Counts all demand & prefetch data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
895
+        "PublicDescription": "Counts all demand & prefetch data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
897
896
         "EventCode": "0xB7, 0xBB",
898
-        "MSRValue": "0x04003c0091",
897
+        "MSRValue": "0x04003C0091",
899
898
         "Counter": "0,1,2,3",
900
899
         "UMask": "0x1",
901
900
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
902
-        "MSRIndex": "0x1a6,0x1a7",
901
+        "MSRIndex": "0x1a6, 0x1a7",
903
902
         "SampleAfterValue": "100003",
904
-        "BriefDescription": "Counts all demand & prefetch data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
903
+        "BriefDescription": "Counts all demand & prefetch data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
905
904
         "Offcore": "1",
906
905
         "CounterHTOff": "0,1,2,3"
907
906
     },
908
907
     {
909
-        "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads that hit in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
908
+        "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads hit in the L3",
910
909
         "EventCode": "0xB7, 0xBB",
911
-        "MSRValue": "0x3f803c0200",
910
+        "MSRValue": "0x3F803C0200",
912
911
         "Counter": "0,1,2,3",
913
912
         "UMask": "0x1",
914
913
         "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_HIT.ANY_RESPONSE",
915
-        "MSRIndex": "0x1a6,0x1a7",
914
+        "MSRIndex": "0x1a6, 0x1a7",
916
915
         "SampleAfterValue": "100003",
917
-        "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads that hit in the L3",
916
+        "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads hit in the L3",
918
917
         "Offcore": "1",
919
918
         "CounterHTOff": "0,1,2,3"
920
919
     },
921
920
     {
922
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs  that hit in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
921
+        "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs hit in the L3",
923
922
         "EventCode": "0xB7, 0xBB",
924
-        "MSRValue": "0x3f803c0100",
923
+        "MSRValue": "0x3F803C0100",
925
924
         "Counter": "0,1,2,3",
926
925
         "UMask": "0x1",
927
926
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.ANY_RESPONSE",
928
-        "MSRIndex": "0x1a6,0x1a7",
927
+        "MSRIndex": "0x1a6, 0x1a7",
929
928
         "SampleAfterValue": "100003",
930
-        "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs  that hit in the L3",
929
+        "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs hit in the L3",
931
930
         "Offcore": "1",
932
931
         "CounterHTOff": "0,1,2,3"
933
932
     },
934
933
     {
935
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
934
+        "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads hit in the L3",
936
935
         "EventCode": "0xB7, 0xBB",
937
-        "MSRValue": "0x3f803c0080",
936
+        "MSRValue": "0x3F803C0080",
938
937
         "Counter": "0,1,2,3",
939
938
         "UMask": "0x1",
940
939
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.ANY_RESPONSE",
941
-        "MSRIndex": "0x1a6,0x1a7",
940
+        "MSRIndex": "0x1a6, 0x1a7",
942
941
         "SampleAfterValue": "100003",
943
-        "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that hit in the L3",
942
+        "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads hit in the L3",
944
943
         "Offcore": "1",
945
944
         "CounterHTOff": "0,1,2,3"
946
945
     },
947
946
     {
948
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads that hit in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
947
+        "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads hit in the L3",
949
948
         "EventCode": "0xB7, 0xBB",
950
-        "MSRValue": "0x3f803c0040",
949
+        "MSRValue": "0x3F803C0040",
951
950
         "Counter": "0,1,2,3",
952
951
         "UMask": "0x1",
953
952
         "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_HIT.ANY_RESPONSE",
954
-        "MSRIndex": "0x1a6,0x1a7",
953
+        "MSRIndex": "0x1a6, 0x1a7",
955
954
         "SampleAfterValue": "100003",
956
-        "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that hit in the L3",
955
+        "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads hit in the L3",
957
956
         "Offcore": "1",
958
957
         "CounterHTOff": "0,1,2,3"
959
958
     },
960
959
     {
961
-        "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs that hit in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
960
+        "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs hit in the L3",
962
961
         "EventCode": "0xB7, 0xBB",
963
-        "MSRValue": "0x3f803c0020",
962
+        "MSRValue": "0x3F803C0020",
964
963
         "Counter": "0,1,2,3",
965
964
         "UMask": "0x1",
966
965
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.ANY_RESPONSE",
967
-        "MSRIndex": "0x1a6,0x1a7",
966
+        "MSRIndex": "0x1a6, 0x1a7",
968
967
         "SampleAfterValue": "100003",
969
-        "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that hit in the L3",
968
+        "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs hit in the L3",
970
969
         "Offcore": "1",
971
970
         "CounterHTOff": "0,1,2,3"
972
971
     },
973
972
     {
974
-        "PublicDescription": "Counts prefetch (that bring data to L2) data reads that hit in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
973
+        "PublicDescription": "Counts prefetch (that bring data to L2) data reads hit in the L3",
975
974
         "EventCode": "0xB7, 0xBB",
976
-        "MSRValue": "0x3f803c0010",
975
+        "MSRValue": "0x3F803C0010",
977
976
         "Counter": "0,1,2,3",
978
977
         "UMask": "0x1",
979
978
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.ANY_RESPONSE",
980
-        "MSRIndex": "0x1a6,0x1a7",
979
+        "MSRIndex": "0x1a6, 0x1a7",
981
980
         "SampleAfterValue": "100003",
982
-        "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the L3",
981
+        "BriefDescription": "Counts prefetch (that bring data to L2) data reads hit in the L3",
983
982
         "Offcore": "1",
984
983
         "CounterHTOff": "0,1,2,3"
985
984
     },
986
985
     {
987
-        "PublicDescription": "Counts all demand code reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
986
+        "PublicDescription": "Counts all demand code reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
988
987
         "EventCode": "0xB7, 0xBB",
989
-        "MSRValue": "0x10003c0004",
988
+        "MSRValue": "0x10003C0004",
990
989
         "Counter": "0,1,2,3",
991
990
         "UMask": "0x1",
992
991
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE",
993
-        "MSRIndex": "0x1a6,0x1a7",
992
+        "MSRIndex": "0x1a6, 0x1a7",
994
993
         "SampleAfterValue": "100003",
995
-        "BriefDescription": "Counts all demand code reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
994
+        "BriefDescription": "Counts all demand code reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
996
995
         "Offcore": "1",
997
996
         "CounterHTOff": "0,1,2,3"
998
997
     },
999
998
     {
1000
-        "PublicDescription": "Counts all demand code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
999
+        "PublicDescription": "Counts all demand code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
1001
1000
         "EventCode": "0xB7, 0xBB",
1002
-        "MSRValue": "0x04003c0004",
1001
+        "MSRValue": "0x04003C0004",
1003
1002
         "Counter": "0,1,2,3",
1004
1003
         "UMask": "0x1",
1005
1004
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
1006
-        "MSRIndex": "0x1a6,0x1a7",
1005
+        "MSRIndex": "0x1a6, 0x1a7",
1007
1006
         "SampleAfterValue": "100003",
1008
-        "BriefDescription": "Counts all demand code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
1007
+        "BriefDescription": "Counts all demand code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
1009
1008
         "Offcore": "1",
1010
1009
         "CounterHTOff": "0,1,2,3"
1011
1010
     },
1012
1011
     {
1013
-        "PublicDescription": "Counts all demand data writes (RFOs) that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1012
+        "PublicDescription": "Counts all demand data writes (RFOs) hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
1014
1013
         "EventCode": "0xB7, 0xBB",
1015
-        "MSRValue": "0x10003c0002",
1014
+        "MSRValue": "0x10003C0002",
1016
1015
         "Counter": "0,1,2,3",
1017
1016
         "UMask": "0x1",
1018
1017
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE",
1019
-        "MSRIndex": "0x1a6,0x1a7",
1018
+        "MSRIndex": "0x1a6, 0x1a7",
1020
1019
         "SampleAfterValue": "100003",
1021
-        "BriefDescription": "Counts all demand data writes (RFOs) that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
1020
+        "BriefDescription": "Counts all demand data writes (RFOs) hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
1022
1021
         "Offcore": "1",
1023
1022
         "CounterHTOff": "0,1,2,3"
1024
1023
     },
1025
1024
     {
1026
-        "PublicDescription": "Counts all demand data writes (RFOs) that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1025
+        "PublicDescription": "Counts all demand data writes (RFOs) hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
1027
1026
         "EventCode": "0xB7, 0xBB",
1028
-        "MSRValue": "0x04003c0002",
1027
+        "MSRValue": "0x04003C0002",
1029
1028
         "Counter": "0,1,2,3",
1030
1029
         "UMask": "0x1",
1031
1030
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
1032
-        "MSRIndex": "0x1a6,0x1a7",
1031
+        "MSRIndex": "0x1a6, 0x1a7",
1033
1032
         "SampleAfterValue": "100003",
1034
-        "BriefDescription": "Counts all demand data writes (RFOs) that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
1033
+        "BriefDescription": "Counts all demand data writes (RFOs) hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
1035
1034
         "Offcore": "1",
1036
1035
         "CounterHTOff": "0,1,2,3"
1037
1036
     },
1038
1037
     {
1039
-        "PublicDescription": "Counts demand data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1038
+        "PublicDescription": "Counts demand data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
1040
1039
         "EventCode": "0xB7, 0xBB",
1041
-        "MSRValue": "0x10003c0001",
1040
+        "MSRValue": "0x10003C0001",
1042
1041
         "Counter": "0,1,2,3",
1043
1042
         "UMask": "0x1",
1044
1043
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE",
1045
-        "MSRIndex": "0x1a6,0x1a7",
1044
+        "MSRIndex": "0x1a6, 0x1a7",
1046
1045
         "SampleAfterValue": "100003",
1047
-        "BriefDescription": "Counts demand data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
1046
+        "BriefDescription": "Counts demand data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
1048
1047
         "Offcore": "1",
1049
1048
         "CounterHTOff": "0,1,2,3"
1050
1049
     },
1051
1050
     {
1052
-        "PublicDescription": "Counts demand data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1051
+        "PublicDescription": "Counts demand data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
1053
1052
         "EventCode": "0xB7, 0xBB",
1054
-        "MSRValue": "0x04003c0001",
1053
+        "MSRValue": "0x04003C0001",
1055
1054
         "Counter": "0,1,2,3",
1056
1055
         "UMask": "0x1",
1057
1056
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
1058
-        "MSRIndex": "0x1a6,0x1a7",
1057
+        "MSRIndex": "0x1a6, 0x1a7",
1059
1058
         "SampleAfterValue": "100003",
1060
-        "BriefDescription": "Counts demand data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
1059
+        "BriefDescription": "Counts demand data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
1061
1060
         "Offcore": "1",
1062
1061
         "CounterHTOff": "0,1,2,3"
1063
1062
     }