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2024-05-10 748e4f3d702def1a4bff191e0cf93b6a05340f01 
 kernel/drivers/watchdog/dw_wdt.c
....@@ -1,11 +1,7 @@
1
+// SPDX-License-Identifier: GPL-2.0-or-later
12 /*
23  * Copyright 2010-2011 Picochip Ltd., Jamie Iles
3
- * http://www.picochip.com
4
- *
5
- * This program is free software; you can redistribute it and/or
6
- * modify it under the terms of the GNU General Public License
7
- * as published by the Free Software Foundation; either version
8
- * 2 of the License, or (at your option) any later version.
4
+ * https://www.picochip.com
95  *
106  * This file implements a driver for the Synopsys DesignWare watchdog device
117  * in the many subsystems. The watchdog has 16 different timeout periods
....@@ -16,9 +12,9 @@
1612  * heartbeat requests after the watchdog device has been closed.
1713  */
1814 
19
-#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
20
-
2115 #include <linux/bitops.h>
16
+#include <linux/limits.h>
17
+#include <linux/kernel.h>
2218 #include <linux/clk.h>
2319 #include <linux/delay.h>
2420 #include <linux/err.h>
....@@ -26,11 +22,13 @@
2622 #include <linux/kernel.h>
2723 #include <linux/module.h>
2824 #include <linux/moduleparam.h>
25
+#include <linux/interrupt.h>
2926 #include <linux/of.h>
3027 #include <linux/pm.h>
3128 #include <linux/platform_device.h>
3229 #include <linux/reset.h>
3330 #include <linux/watchdog.h>
31
+#include <linux/debugfs.h>
3432 
3533 #define WDOG_CONTROL_REG_OFFSET		    0x00
3634 #define WDOG_CONTROL_REG_WDT_EN_MASK	    0x01
....@@ -40,27 +38,64 @@
4038 #define WDOG_CURRENT_COUNT_REG_OFFSET	    0x08
4139 #define WDOG_COUNTER_RESTART_REG_OFFSET     0x0c
4240 #define WDOG_COUNTER_RESTART_KICK_VALUE	    0x76
41
+#define WDOG_INTERRUPT_STATUS_REG_OFFSET    0x10
42
+#define WDOG_INTERRUPT_CLEAR_REG_OFFSET     0x14
43
+#define WDOG_COMP_PARAMS_5_REG_OFFSET       0xe4
44
+#define WDOG_COMP_PARAMS_4_REG_OFFSET       0xe8
45
+#define WDOG_COMP_PARAMS_3_REG_OFFSET       0xec
46
+#define WDOG_COMP_PARAMS_2_REG_OFFSET       0xf0
47
+#define WDOG_COMP_PARAMS_1_REG_OFFSET       0xf4
48
+#define WDOG_COMP_PARAMS_1_USE_FIX_TOP      BIT(6)
49
+#define WDOG_COMP_VERSION_REG_OFFSET        0xf8
50
+#define WDOG_COMP_TYPE_REG_OFFSET           0xfc
4351 
44
-/* The maximum TOP (timeout period) value that can be set in the watchdog. */
45
-#define DW_WDT_MAX_TOP		15
52
+/* There are sixteen TOPs (timeout periods) that can be set in the watchdog. */
53
+#define DW_WDT_NUM_TOPS		16
54
+#define DW_WDT_FIX_TOP(_idx)	(1U << (16 + _idx))
4655 
4756 #define DW_WDT_DEFAULT_SECONDS	30
57
+
58
+static const u32 dw_wdt_fix_tops[DW_WDT_NUM_TOPS] = {
59
+	DW_WDT_FIX_TOP(0), DW_WDT_FIX_TOP(1), DW_WDT_FIX_TOP(2),
60
+	DW_WDT_FIX_TOP(3), DW_WDT_FIX_TOP(4), DW_WDT_FIX_TOP(5),
61
+	DW_WDT_FIX_TOP(6), DW_WDT_FIX_TOP(7), DW_WDT_FIX_TOP(8),
62
+	DW_WDT_FIX_TOP(9), DW_WDT_FIX_TOP(10), DW_WDT_FIX_TOP(11),
63
+	DW_WDT_FIX_TOP(12), DW_WDT_FIX_TOP(13), DW_WDT_FIX_TOP(14),
64
+	DW_WDT_FIX_TOP(15)
65
+};
4866 
4967 static bool nowayout = WATCHDOG_NOWAYOUT;
5068 module_param(nowayout, bool, 0);
5169 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started "
5270 		 "(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
5371 
72
+enum dw_wdt_rmod {
73
+	DW_WDT_RMOD_RESET = 1,
74
+	DW_WDT_RMOD_IRQ = 2
75
+};
76
+
77
+struct dw_wdt_timeout {
78
+	u32 top_val;
79
+	unsigned int sec;
80
+	unsigned int msec;
81
+};
82
+
5483 struct dw_wdt {
5584 	void __iomem		*regs;
5685 	struct clk		*clk;
5786 	struct clk		*pclk;
5887 	unsigned long		rate;
88
+	enum dw_wdt_rmod	rmod;
89
+	struct dw_wdt_timeout	timeouts[DW_WDT_NUM_TOPS];
5990 	struct watchdog_device	wdd;
6091 	struct reset_control	*rst;
6192 	/* Save/restore */
6293 	u32			control;
6394 	u32			timeout;
95
+
96
+#ifdef CONFIG_DEBUG_FS
97
+	struct dentry		*dbgfs_dir;
98
+#endif
6499 };
65100 
66101 #define to_dw_wdt(wdd)	container_of(wdd, struct dw_wdt, wdd)
....@@ -71,20 +106,91 @@
71106 		WDOG_CONTROL_REG_WDT_EN_MASK;
72107 }
73108 
74
-static inline int dw_wdt_top_in_seconds(struct dw_wdt *dw_wdt, unsigned top)
109
+static void dw_wdt_update_mode(struct dw_wdt *dw_wdt, enum dw_wdt_rmod rmod)
75110 {
76
-	/*
77
-	 * There are 16 possible timeout values in 0..15 where the number of
78
-	 * cycles is 2 ^ (16 + i) and the watchdog counts down.
79
-	 */
80
-	return (1U << (16 + top)) / dw_wdt->rate;
111
+	u32 val;
112
+
113
+	val = readl(dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);
114
+	if (rmod == DW_WDT_RMOD_IRQ)
115
+		val |= WDOG_CONTROL_REG_RESP_MODE_MASK;
116
+	else
117
+		val &= ~WDOG_CONTROL_REG_RESP_MODE_MASK;
118
+	writel(val, dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);
119
+
120
+	dw_wdt->rmod = rmod;
81121 }
82122 
83
-static int dw_wdt_get_top(struct dw_wdt *dw_wdt)
123
+static unsigned int dw_wdt_find_best_top(struct dw_wdt *dw_wdt,
124
+					 unsigned int timeout, u32 *top_val)
84125 {
85
-	int top = readl(dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET) & 0xF;
126
+	int idx;
86127 
87
-	return dw_wdt_top_in_seconds(dw_wdt, top);
128
+	/*
129
+	 * Find a TOP with timeout greater or equal to the requested number.
130
+	 * Note we'll select a TOP with maximum timeout if the requested
131
+	 * timeout couldn't be reached.
132
+	 */
133
+	for (idx = 0; idx < DW_WDT_NUM_TOPS; ++idx) {
134
+		if (dw_wdt->timeouts[idx].sec >= timeout)
135
+			break;
136
+	}
137
+
138
+	if (idx == DW_WDT_NUM_TOPS)
139
+		--idx;
140
+
141
+	*top_val = dw_wdt->timeouts[idx].top_val;
142
+
143
+	return dw_wdt->timeouts[idx].sec;
144
+}
145
+
146
+static unsigned int dw_wdt_get_min_timeout(struct dw_wdt *dw_wdt)
147
+{
148
+	int idx;
149
+
150
+	/*
151
+	 * We'll find a timeout greater or equal to one second anyway because
152
+	 * the driver probe would have failed if there was none.
153
+	 */
154
+	for (idx = 0; idx < DW_WDT_NUM_TOPS; ++idx) {
155
+		if (dw_wdt->timeouts[idx].sec)
156
+			break;
157
+	}
158
+
159
+	/* For Coverity check */
160
+	if (idx == DW_WDT_NUM_TOPS)
161
+		idx = 0;
162
+
163
+	return dw_wdt->timeouts[idx].sec;
164
+}
165
+
166
+static unsigned int dw_wdt_get_max_timeout_ms(struct dw_wdt *dw_wdt)
167
+{
168
+	struct dw_wdt_timeout *timeout = &dw_wdt->timeouts[DW_WDT_NUM_TOPS - 1];
169
+	u64 msec;
170
+
171
+	msec = (u64)timeout->sec * MSEC_PER_SEC + timeout->msec;
172
+
173
+	return msec < UINT_MAX ? msec : UINT_MAX;
174
+}
175
+
176
+static unsigned int dw_wdt_get_timeout(struct dw_wdt *dw_wdt)
177
+{
178
+	int top_val = readl(dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET) & 0xF;
179
+	int idx;
180
+
181
+	for (idx = 0; idx < DW_WDT_NUM_TOPS; ++idx) {
182
+		if (dw_wdt->timeouts[idx].top_val == top_val)
183
+			break;
184
+	}
185
+
186
+	if (idx == DW_WDT_NUM_TOPS)
187
+		idx = 0;
188
+
189
+	/*
190
+	 * In IRQ mode due to the two stages counter, the actual timeout is
191
+	 * twice greater than the TOP setting.
192
+	 */
193
+	return dw_wdt->timeouts[idx].sec * dw_wdt->rmod;
88194 }
89195 
90196 static int dw_wdt_ping(struct watchdog_device *wdd)
....@@ -100,17 +206,23 @@
100206 static int dw_wdt_set_timeout(struct watchdog_device *wdd, unsigned int top_s)
101207 {
102208 	struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
103
-	int i, top_val = DW_WDT_MAX_TOP;
209
+	unsigned int timeout;
210
+	u32 top_val;
104211 
105212 	/*
106
-	 * Iterate over the timeout values until we find the closest match. We
107
-	 * always look for >=.
213
+	 * Note IRQ mode being enabled means having a non-zero pre-timeout
214
+	 * setup. In this case we try to find a TOP as close to the half of the
215
+	 * requested timeout as possible since DW Watchdog IRQ mode is designed
216
+	 * in two stages way - first timeout rises the pre-timeout interrupt,
217
+	 * second timeout performs the system reset. So basically the effective
218
+	 * watchdog-caused reset happens after two watchdog TOPs elapsed.
108219 	 */
109
-	for (i = 0; i <= DW_WDT_MAX_TOP; ++i)
110
-		if (dw_wdt_top_in_seconds(dw_wdt, i) >= top_s) {
111
-			top_val = i;
112
-			break;
113
-		}
220
+	timeout = dw_wdt_find_best_top(dw_wdt, DIV_ROUND_UP(top_s, dw_wdt->rmod),
221
+				       &top_val);
222
+	if (dw_wdt->rmod == DW_WDT_RMOD_IRQ)
223
+		wdd->pretimeout = timeout;
224
+	else
225
+		wdd->pretimeout = 0;
114226 
115227 	/*
116228 	 * Set the new value in the watchdog.  Some versions of dw_wdt
....@@ -121,7 +233,34 @@
121233 	writel(top_val | top_val << WDOG_TIMEOUT_RANGE_TOPINIT_SHIFT,
122234 	       dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET);
123235 
124
-	wdd->timeout = dw_wdt_top_in_seconds(dw_wdt, top_val);
236
+	/* Kick new TOP value into the watchdog counter if activated. */
237
+	if (watchdog_active(wdd))
238
+		dw_wdt_ping(wdd);
239
+
240
+	/*
241
+	 * In case users set bigger timeout value than HW can support,
242
+	 * kernel(watchdog_dev.c) helps to feed watchdog before
243
+	 * wdd->max_hw_heartbeat_ms
244
+	 */
245
+	if (top_s * 1000 <= wdd->max_hw_heartbeat_ms)
246
+		wdd->timeout = timeout * dw_wdt->rmod;
247
+	else
248
+		wdd->timeout = top_s;
249
+
250
+	return 0;
251
+}
252
+
253
+static int dw_wdt_set_pretimeout(struct watchdog_device *wdd, unsigned int req)
254
+{
255
+	struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
256
+
257
+	/*
258
+	 * We ignore actual value of the timeout passed from user-space
259
+	 * using it as a flag whether the pretimeout functionality is intended
260
+	 * to be activated.
261
+	 */
262
+	dw_wdt_update_mode(dw_wdt, req ? DW_WDT_RMOD_IRQ : DW_WDT_RMOD_RESET);
263
+	dw_wdt_set_timeout(wdd, wdd->timeout);
125264 
126265 	return 0;
127266 }
....@@ -130,8 +269,11 @@
130269 {
131270 	u32 val = readl(dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);
132271 
133
-	/* Disable interrupt mode; always perform system reset. */
134
-	val &= ~WDOG_CONTROL_REG_RESP_MODE_MASK;
272
+	/* Disable/enable interrupt mode depending on the RMOD flag. */
273
+	if (dw_wdt->rmod == DW_WDT_RMOD_IRQ)
274
+		val |= WDOG_CONTROL_REG_RESP_MODE_MASK;
275
+	else
276
+		val &= ~WDOG_CONTROL_REG_RESP_MODE_MASK;
135277 	/* Enable watchdog. */
136278 	val |= WDOG_CONTROL_REG_WDT_EN_MASK;
137279 	writel(val, dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);
....@@ -169,6 +311,7 @@
169311 	struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
170312 
171313 	writel(0, dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET);
314
+	dw_wdt_update_mode(dw_wdt, DW_WDT_RMOD_RESET);
172315 	if (dw_wdt_is_enabled(dw_wdt))
173316 		writel(WDOG_COUNTER_RESTART_KICK_VALUE,
174317 		       dw_wdt->regs + WDOG_COUNTER_RESTART_REG_OFFSET);
....@@ -184,14 +327,30 @@
184327 static unsigned int dw_wdt_get_timeleft(struct watchdog_device *wdd)
185328 {
186329 	struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
330
+	unsigned int sec;
331
+	u32 val;
187332 
188
-	return readl(dw_wdt->regs + WDOG_CURRENT_COUNT_REG_OFFSET) /
189
-		dw_wdt->rate;
333
+	val = readl(dw_wdt->regs + WDOG_CURRENT_COUNT_REG_OFFSET);
334
+	sec = val / dw_wdt->rate;
335
+
336
+	if (dw_wdt->rmod == DW_WDT_RMOD_IRQ) {
337
+		val = readl(dw_wdt->regs + WDOG_INTERRUPT_STATUS_REG_OFFSET);
338
+		if (!val)
339
+			sec += wdd->pretimeout;
340
+	}
341
+
342
+	return sec;
190343 }
191344 
192345 static const struct watchdog_info dw_wdt_ident = {
193346 	.options	= WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT |
194347 			  WDIOF_MAGICCLOSE,
348
+	.identity	= "Synopsys DesignWare Watchdog",
349
+};
350
+
351
+static const struct watchdog_info dw_wdt_pt_ident = {
352
+	.options	= WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT |
353
+			  WDIOF_PRETIMEOUT | WDIOF_MAGICCLOSE,
195354 	.identity	= "Synopsys DesignWare Watchdog",
196355 };
197356 
....@@ -201,9 +360,28 @@
201360 	.stop		= dw_wdt_stop,
202361 	.ping		= dw_wdt_ping,
203362 	.set_timeout	= dw_wdt_set_timeout,
363
+	.set_pretimeout	= dw_wdt_set_pretimeout,
204364 	.get_timeleft	= dw_wdt_get_timeleft,
205365 	.restart	= dw_wdt_restart,
206366 };
367
+
368
+static irqreturn_t dw_wdt_irq(int irq, void *devid)
369
+{
370
+	struct dw_wdt *dw_wdt = devid;
371
+	u32 val;
372
+
373
+	/*
374
+	 * We don't clear the IRQ status. It's supposed to be done by the
375
+	 * following ping operations.
376
+	 */
377
+	val = readl(dw_wdt->regs + WDOG_INTERRUPT_STATUS_REG_OFFSET);
378
+	if (!val)
379
+		return IRQ_NONE;
380
+
381
+	watchdog_notify_pretimeout(&dw_wdt->wdd);
382
+
383
+	return IRQ_HANDLED;
384
+}
207385 
208386 #ifdef CONFIG_PM_SLEEP
209387 static int dw_wdt_suspend(struct device *dev)
....@@ -244,20 +422,151 @@
244422 
245423 static SIMPLE_DEV_PM_OPS(dw_wdt_pm_ops, dw_wdt_suspend, dw_wdt_resume);
246424 
425
+/*
426
+ * In case if DW WDT IP core is synthesized with fixed TOP feature disabled the
427
+ * TOPs array can be arbitrary ordered with nearly any sixteen uint numbers
428
+ * depending on the system engineer imagination. The next method handles the
429
+ * passed TOPs array to pre-calculate the effective timeouts and to sort the
430
+ * TOP items out in the ascending order with respect to the timeouts.
431
+ */
432
+
433
+static void dw_wdt_handle_tops(struct dw_wdt *dw_wdt, const u32 *tops)
434
+{
435
+	struct dw_wdt_timeout tout, *dst;
436
+	int val, tidx;
437
+	u64 msec;
438
+
439
+	/*
440
+	 * We walk over the passed TOPs array and calculate corresponding
441
+	 * timeouts in seconds and milliseconds. The milliseconds granularity
442
+	 * is needed to distinguish the TOPs with very close timeouts and to
443
+	 * set the watchdog max heartbeat setting further.
444
+	 */
445
+	for (val = 0; val < DW_WDT_NUM_TOPS; ++val) {
446
+		tout.top_val = val;
447
+		tout.sec = tops[val] / dw_wdt->rate;
448
+		msec = (u64)tops[val] * MSEC_PER_SEC;
449
+		do_div(msec, dw_wdt->rate);
450
+		tout.msec = msec - ((u64)tout.sec * MSEC_PER_SEC);
451
+
452
+		/*
453
+		 * Find a suitable place for the current TOP in the timeouts
454
+		 * array so that the list is remained in the ascending order.
455
+		 */
456
+		for (tidx = 0; tidx < val; ++tidx) {
457
+			dst = &dw_wdt->timeouts[tidx];
458
+			if (tout.sec > dst->sec || (tout.sec == dst->sec &&
459
+			    tout.msec >= dst->msec))
460
+				continue;
461
+			else
462
+				swap(*dst, tout);
463
+		}
464
+
465
+		dw_wdt->timeouts[val] = tout;
466
+	}
467
+}
468
+
469
+static int dw_wdt_init_timeouts(struct dw_wdt *dw_wdt, struct device *dev)
470
+{
471
+	u32 data, of_tops[DW_WDT_NUM_TOPS];
472
+	const u32 *tops;
473
+	int ret;
474
+
475
+	/*
476
+	 * Retrieve custom or fixed counter values depending on the
477
+	 * WDT_USE_FIX_TOP flag found in the component specific parameters
478
+	 * #1 register.
479
+	 */
480
+	data = readl(dw_wdt->regs + WDOG_COMP_PARAMS_1_REG_OFFSET);
481
+	if (data & WDOG_COMP_PARAMS_1_USE_FIX_TOP) {
482
+		tops = dw_wdt_fix_tops;
483
+	} else {
484
+		ret = of_property_read_variable_u32_array(dev_of_node(dev),
485
+			"snps,watchdog-tops", of_tops, DW_WDT_NUM_TOPS,
486
+			DW_WDT_NUM_TOPS);
487
+		if (ret < 0) {
488
+			dev_warn(dev, "No valid TOPs array specified\n");
489
+			tops = dw_wdt_fix_tops;
490
+		} else {
491
+			tops = of_tops;
492
+		}
493
+	}
494
+
495
+	/* Convert the specified TOPs into an array of watchdog timeouts. */
496
+	dw_wdt_handle_tops(dw_wdt, tops);
497
+	if (!dw_wdt->timeouts[DW_WDT_NUM_TOPS - 1].sec) {
498
+		dev_err(dev, "No any valid TOP detected\n");
499
+		return -EINVAL;
500
+	}
501
+
502
+	return 0;
503
+}
504
+
505
+#ifdef CONFIG_DEBUG_FS
506
+
507
+#define DW_WDT_DBGFS_REG(_name, _off) \
508
+{				      \
509
+	.name = _name,		      \
510
+	.offset = _off		      \
511
+}
512
+
513
+static const struct debugfs_reg32 dw_wdt_dbgfs_regs[] = {
514
+	DW_WDT_DBGFS_REG("cr", WDOG_CONTROL_REG_OFFSET),
515
+	DW_WDT_DBGFS_REG("torr", WDOG_TIMEOUT_RANGE_REG_OFFSET),
516
+	DW_WDT_DBGFS_REG("ccvr", WDOG_CURRENT_COUNT_REG_OFFSET),
517
+	DW_WDT_DBGFS_REG("crr", WDOG_COUNTER_RESTART_REG_OFFSET),
518
+	DW_WDT_DBGFS_REG("stat", WDOG_INTERRUPT_STATUS_REG_OFFSET),
519
+	DW_WDT_DBGFS_REG("param5", WDOG_COMP_PARAMS_5_REG_OFFSET),
520
+	DW_WDT_DBGFS_REG("param4", WDOG_COMP_PARAMS_4_REG_OFFSET),
521
+	DW_WDT_DBGFS_REG("param3", WDOG_COMP_PARAMS_3_REG_OFFSET),
522
+	DW_WDT_DBGFS_REG("param2", WDOG_COMP_PARAMS_2_REG_OFFSET),
523
+	DW_WDT_DBGFS_REG("param1", WDOG_COMP_PARAMS_1_REG_OFFSET),
524
+	DW_WDT_DBGFS_REG("version", WDOG_COMP_VERSION_REG_OFFSET),
525
+	DW_WDT_DBGFS_REG("type", WDOG_COMP_TYPE_REG_OFFSET)
526
+};
527
+
528
+static void dw_wdt_dbgfs_init(struct dw_wdt *dw_wdt)
529
+{
530
+	struct device *dev = dw_wdt->wdd.parent;
531
+	struct debugfs_regset32 *regset;
532
+
533
+	regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL);
534
+	if (!regset)
535
+		return;
536
+
537
+	regset->regs = dw_wdt_dbgfs_regs;
538
+	regset->nregs = ARRAY_SIZE(dw_wdt_dbgfs_regs);
539
+	regset->base = dw_wdt->regs;
540
+
541
+	dw_wdt->dbgfs_dir = debugfs_create_dir(dev_name(dev), NULL);
542
+
543
+	debugfs_create_regset32("registers", 0444, dw_wdt->dbgfs_dir, regset);
544
+}
545
+
546
+static void dw_wdt_dbgfs_clear(struct dw_wdt *dw_wdt)
547
+{
548
+	debugfs_remove_recursive(dw_wdt->dbgfs_dir);
549
+}
550
+
551
+#else /* !CONFIG_DEBUG_FS */
552
+
553
+static void dw_wdt_dbgfs_init(struct dw_wdt *dw_wdt) {}
554
+static void dw_wdt_dbgfs_clear(struct dw_wdt *dw_wdt) {}
555
+
556
+#endif /* !CONFIG_DEBUG_FS */
557
+
247558 static int dw_wdt_drv_probe(struct platform_device *pdev)
248559 {
249560 	struct device *dev = &pdev->dev;
250561 	struct watchdog_device *wdd;
251562 	struct dw_wdt *dw_wdt;
252
-	struct resource *mem;
253563 	int ret;
254564 
255565 	dw_wdt = devm_kzalloc(dev, sizeof(*dw_wdt), GFP_KERNEL);
256566 	if (!dw_wdt)
257567 		return -ENOMEM;
258568 
259
-	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
260
-	dw_wdt->regs = devm_ioremap_resource(dev, mem);
569
+	dw_wdt->regs = devm_platform_ioremap_resource(pdev, 0);
261570 	if (IS_ERR(dw_wdt->regs))
262571 		return PTR_ERR(dw_wdt->regs);
263572 
....@@ -307,14 +616,41 @@
307616 		goto out_disable_pclk;
308617 	}
309618 
619
+	/* Enable normal reset without pre-timeout by default. */
620
+	dw_wdt_update_mode(dw_wdt, DW_WDT_RMOD_RESET);
621
+
622
+	/*
623
+	 * Pre-timeout IRQ is optional, since some hardware may lack support
624
+	 * of it. Note we must request rising-edge IRQ, since the lane is left
625
+	 * pending either until the next watchdog kick event or up to the
626
+	 * system reset.
627
+	 */
628
+	ret = platform_get_irq_optional(pdev, 0);
629
+	if (ret > 0) {
630
+		ret = devm_request_irq(dev, ret, dw_wdt_irq,
631
+				       IRQF_SHARED | IRQF_TRIGGER_RISING,
632
+				       pdev->name, dw_wdt);
633
+		if (ret)
634
+			goto out_disable_pclk;
635
+
636
+		dw_wdt->wdd.info = &dw_wdt_pt_ident;
637
+	} else {
638
+		if (ret == -EPROBE_DEFER)
639
+			goto out_disable_pclk;
640
+
641
+		dw_wdt->wdd.info = &dw_wdt_ident;
642
+	}
643
+
310644 	reset_control_deassert(dw_wdt->rst);
311645 
646
+	ret = dw_wdt_init_timeouts(dw_wdt, dev);
647
+	if (ret)
648
+		goto out_assert_rst;
649
+
312650 	wdd = &dw_wdt->wdd;
313
-	wdd->info = &dw_wdt_ident;
314651 	wdd->ops = &dw_wdt_ops;
315
-	wdd->min_timeout = 1;
316
-	wdd->max_hw_heartbeat_ms =
317
-		dw_wdt_top_in_seconds(dw_wdt, DW_WDT_MAX_TOP) * 1000;
652
+	wdd->min_timeout = dw_wdt_get_min_timeout(dw_wdt);
653
+	wdd->max_hw_heartbeat_ms = dw_wdt_get_max_timeout_ms(dw_wdt);
318654 	wdd->parent = dev;
319655 
320656 	watchdog_set_drvdata(wdd, dw_wdt);
....@@ -327,7 +663,7 @@
327663 	 * devicetree.
328664 	 */
329665 	if (dw_wdt_is_enabled(dw_wdt)) {
330
-		wdd->timeout = dw_wdt_get_top(dw_wdt);
666
+		wdd->timeout = dw_wdt_get_timeout(dw_wdt);
331667 		set_bit(WDOG_HW_RUNNING, &wdd->status);
332668 	} else {
333669 		wdd->timeout = DW_WDT_DEFAULT_SECONDS;
....@@ -340,9 +676,14 @@
340676 
341677 	ret = watchdog_register_device(wdd);
342678 	if (ret)
343
-		goto out_disable_pclk;
679
+		goto out_assert_rst;
680
+
681
+	dw_wdt_dbgfs_init(dw_wdt);
344682 
345683 	return 0;
684
+
685
+out_assert_rst:
686
+	reset_control_assert(dw_wdt->rst);
346687 
347688 out_disable_pclk:
348689 	clk_disable_unprepare(dw_wdt->pclk);
....@@ -356,6 +697,8 @@
356697 {
357698 	struct dw_wdt *dw_wdt = platform_get_drvdata(pdev);
358699 
700
+	dw_wdt_dbgfs_clear(dw_wdt);
701
+
359702 	watchdog_unregister_device(&dw_wdt->wdd);
360703 	reset_control_assert(dw_wdt->rst);
361704 	clk_disable_unprepare(dw_wdt->pclk);