forked from ~ljy/RK356X_SDK_RELEASE
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2024-05-10 748e4f3d702def1a4bff191e0cf93b6a05340f01 
 kernel/drivers/regulator/axp20x-regulator.c
....@@ -13,30 +13,262 @@
1313  * GNU General Public License for more details.
1414  */
1515 
16
+#include <linux/bitops.h>
17
+#include <linux/delay.h>
1618 #include <linux/err.h>
1719 #include <linux/init.h>
20
+#include <linux/mfd/axp20x.h>
1821 #include <linux/module.h>
1922 #include <linux/of.h>
2023 #include <linux/of_device.h>
2124 #include <linux/platform_device.h>
2225 #include <linux/regmap.h>
23
-#include <linux/mfd/axp20x.h>
2426 #include <linux/regulator/driver.h>
27
+#include <linux/regulator/machine.h>
2528 #include <linux/regulator/of_regulator.h>
29
+
30
+#define AXP20X_GPIO0_FUNC_MASK		GENMASK(3, 0)
31
+#define AXP20X_GPIO1_FUNC_MASK		GENMASK(3, 0)
2632 
2733 #define AXP20X_IO_ENABLED		0x03
2834 #define AXP20X_IO_DISABLED		0x07
2935 
36
+#define AXP20X_WORKMODE_DCDC2_MASK	BIT_MASK(2)
37
+#define AXP20X_WORKMODE_DCDC3_MASK	BIT_MASK(1)
38
+
39
+#define AXP20X_FREQ_DCDC_MASK		GENMASK(3, 0)
40
+
41
+#define AXP20X_VBUS_IPSOUT_MGMT_MASK	BIT_MASK(2)
42
+
43
+#define AXP20X_DCDC2_V_OUT_MASK		GENMASK(5, 0)
44
+#define AXP20X_DCDC3_V_OUT_MASK		GENMASK(7, 0)
45
+#define AXP20X_LDO2_V_OUT_MASK		GENMASK(7, 4)
46
+#define AXP20X_LDO3_V_OUT_MASK		GENMASK(6, 0)
47
+#define AXP20X_LDO4_V_OUT_MASK		GENMASK(3, 0)
48
+#define AXP20X_LDO5_V_OUT_MASK		GENMASK(7, 4)
49
+
50
+#define AXP20X_PWR_OUT_EXTEN_MASK	BIT_MASK(0)
51
+#define AXP20X_PWR_OUT_DCDC3_MASK	BIT_MASK(1)
52
+#define AXP20X_PWR_OUT_LDO2_MASK	BIT_MASK(2)
53
+#define AXP20X_PWR_OUT_LDO4_MASK	BIT_MASK(3)
54
+#define AXP20X_PWR_OUT_DCDC2_MASK	BIT_MASK(4)
55
+#define AXP20X_PWR_OUT_LDO3_MASK	BIT_MASK(6)
56
+
57
+#define AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_RATE_MASK	BIT_MASK(0)
58
+#define AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_RATE(x) \
59
+	((x) << 0)
60
+#define AXP20X_DCDC2_LDO3_V_RAMP_LDO3_RATE_MASK		BIT_MASK(1)
61
+#define AXP20X_DCDC2_LDO3_V_RAMP_LDO3_RATE(x) \
62
+	((x) << 1)
63
+#define AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_EN_MASK		BIT_MASK(2)
64
+#define AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_EN		BIT(2)
65
+#define AXP20X_DCDC2_LDO3_V_RAMP_LDO3_EN_MASK		BIT_MASK(3)
66
+#define AXP20X_DCDC2_LDO3_V_RAMP_LDO3_EN		BIT(3)
67
+
68
+#define AXP20X_LDO4_V_OUT_1250mV_START	0x0
69
+#define AXP20X_LDO4_V_OUT_1250mV_STEPS	0
70
+#define AXP20X_LDO4_V_OUT_1250mV_END	\
71
+	(AXP20X_LDO4_V_OUT_1250mV_START + AXP20X_LDO4_V_OUT_1250mV_STEPS)
72
+#define AXP20X_LDO4_V_OUT_1300mV_START	0x1
73
+#define AXP20X_LDO4_V_OUT_1300mV_STEPS	7
74
+#define AXP20X_LDO4_V_OUT_1300mV_END	\
75
+	(AXP20X_LDO4_V_OUT_1300mV_START + AXP20X_LDO4_V_OUT_1300mV_STEPS)
76
+#define AXP20X_LDO4_V_OUT_2500mV_START	0x9
77
+#define AXP20X_LDO4_V_OUT_2500mV_STEPS	0
78
+#define AXP20X_LDO4_V_OUT_2500mV_END	\
79
+	(AXP20X_LDO4_V_OUT_2500mV_START + AXP20X_LDO4_V_OUT_2500mV_STEPS)
80
+#define AXP20X_LDO4_V_OUT_2700mV_START	0xa
81
+#define AXP20X_LDO4_V_OUT_2700mV_STEPS	1
82
+#define AXP20X_LDO4_V_OUT_2700mV_END	\
83
+	(AXP20X_LDO4_V_OUT_2700mV_START + AXP20X_LDO4_V_OUT_2700mV_STEPS)
84
+#define AXP20X_LDO4_V_OUT_3000mV_START	0xc
85
+#define AXP20X_LDO4_V_OUT_3000mV_STEPS	3
86
+#define AXP20X_LDO4_V_OUT_3000mV_END	\
87
+	(AXP20X_LDO4_V_OUT_3000mV_START + AXP20X_LDO4_V_OUT_3000mV_STEPS)
88
+#define AXP20X_LDO4_V_OUT_NUM_VOLTAGES	16
89
+
3090 #define AXP22X_IO_ENABLED		0x03
3191 #define AXP22X_IO_DISABLED		0x04
3292 
33
-#define AXP20X_WORKMODE_DCDC2_MASK	BIT(2)
34
-#define AXP20X_WORKMODE_DCDC3_MASK	BIT(1)
35
-#define AXP22X_WORKMODE_DCDCX_MASK(x)	BIT(x)
36
-
37
-#define AXP20X_FREQ_DCDC_MASK		0x0f
93
+#define AXP22X_WORKMODE_DCDCX_MASK(x)	BIT_MASK(x)
3894 
3995 #define AXP22X_MISC_N_VBUSEN_FUNC	BIT(4)
96
+
97
+#define AXP22X_DCDC1_V_OUT_MASK		GENMASK(4, 0)
98
+#define AXP22X_DCDC2_V_OUT_MASK		GENMASK(5, 0)
99
+#define AXP22X_DCDC3_V_OUT_MASK		GENMASK(5, 0)
100
+#define AXP22X_DCDC4_V_OUT_MASK		GENMASK(5, 0)
101
+#define AXP22X_DCDC5_V_OUT_MASK		GENMASK(4, 0)
102
+#define AXP22X_DC5LDO_V_OUT_MASK	GENMASK(2, 0)
103
+#define AXP22X_ALDO1_V_OUT_MASK		GENMASK(4, 0)
104
+#define AXP22X_ALDO2_V_OUT_MASK		GENMASK(4, 0)
105
+#define AXP22X_ALDO3_V_OUT_MASK		GENMASK(4, 0)
106
+#define AXP22X_DLDO1_V_OUT_MASK		GENMASK(4, 0)
107
+#define AXP22X_DLDO2_V_OUT_MASK		GENMASK(4, 0)
108
+#define AXP22X_DLDO3_V_OUT_MASK		GENMASK(4, 0)
109
+#define AXP22X_DLDO4_V_OUT_MASK		GENMASK(4, 0)
110
+#define AXP22X_ELDO1_V_OUT_MASK		GENMASK(4, 0)
111
+#define AXP22X_ELDO2_V_OUT_MASK		GENMASK(4, 0)
112
+#define AXP22X_ELDO3_V_OUT_MASK		GENMASK(4, 0)
113
+#define AXP22X_LDO_IO0_V_OUT_MASK	GENMASK(4, 0)
114
+#define AXP22X_LDO_IO1_V_OUT_MASK	GENMASK(4, 0)
115
+
116
+#define AXP22X_PWR_OUT_DC5LDO_MASK	BIT_MASK(0)
117
+#define AXP22X_PWR_OUT_DCDC1_MASK	BIT_MASK(1)
118
+#define AXP22X_PWR_OUT_DCDC2_MASK	BIT_MASK(2)
119
+#define AXP22X_PWR_OUT_DCDC3_MASK	BIT_MASK(3)
120
+#define AXP22X_PWR_OUT_DCDC4_MASK	BIT_MASK(4)
121
+#define AXP22X_PWR_OUT_DCDC5_MASK	BIT_MASK(5)
122
+#define AXP22X_PWR_OUT_ALDO1_MASK	BIT_MASK(6)
123
+#define AXP22X_PWR_OUT_ALDO2_MASK	BIT_MASK(7)
124
+
125
+#define AXP22X_PWR_OUT_SW_MASK		BIT_MASK(6)
126
+#define AXP22X_PWR_OUT_DC1SW_MASK	BIT_MASK(7)
127
+
128
+#define AXP22X_PWR_OUT_ELDO1_MASK	BIT_MASK(0)
129
+#define AXP22X_PWR_OUT_ELDO2_MASK	BIT_MASK(1)
130
+#define AXP22X_PWR_OUT_ELDO3_MASK	BIT_MASK(2)
131
+#define AXP22X_PWR_OUT_DLDO1_MASK	BIT_MASK(3)
132
+#define AXP22X_PWR_OUT_DLDO2_MASK	BIT_MASK(4)
133
+#define AXP22X_PWR_OUT_DLDO3_MASK	BIT_MASK(5)
134
+#define AXP22X_PWR_OUT_DLDO4_MASK	BIT_MASK(6)
135
+#define AXP22X_PWR_OUT_ALDO3_MASK	BIT_MASK(7)
136
+
137
+#define AXP803_PWR_OUT_DCDC1_MASK	BIT_MASK(0)
138
+#define AXP803_PWR_OUT_DCDC2_MASK	BIT_MASK(1)
139
+#define AXP803_PWR_OUT_DCDC3_MASK	BIT_MASK(2)
140
+#define AXP803_PWR_OUT_DCDC4_MASK	BIT_MASK(3)
141
+#define AXP803_PWR_OUT_DCDC5_MASK	BIT_MASK(4)
142
+#define AXP803_PWR_OUT_DCDC6_MASK	BIT_MASK(5)
143
+
144
+#define AXP803_PWR_OUT_FLDO1_MASK	BIT_MASK(2)
145
+#define AXP803_PWR_OUT_FLDO2_MASK	BIT_MASK(3)
146
+
147
+#define AXP803_DCDC1_V_OUT_MASK		GENMASK(4, 0)
148
+#define AXP803_DCDC2_V_OUT_MASK		GENMASK(6, 0)
149
+#define AXP803_DCDC3_V_OUT_MASK		GENMASK(6, 0)
150
+#define AXP803_DCDC4_V_OUT_MASK		GENMASK(6, 0)
151
+#define AXP803_DCDC5_V_OUT_MASK		GENMASK(6, 0)
152
+#define AXP803_DCDC6_V_OUT_MASK		GENMASK(6, 0)
153
+
154
+#define AXP803_FLDO1_V_OUT_MASK		GENMASK(3, 0)
155
+#define AXP803_FLDO2_V_OUT_MASK		GENMASK(3, 0)
156
+
157
+#define AXP803_DCDC23_POLYPHASE_DUAL	BIT(6)
158
+#define AXP803_DCDC56_POLYPHASE_DUAL	BIT(5)
159
+
160
+#define AXP803_DCDC234_500mV_START	0x00
161
+#define AXP803_DCDC234_500mV_STEPS	70
162
+#define AXP803_DCDC234_500mV_END	\
163
+	(AXP803_DCDC234_500mV_START + AXP803_DCDC234_500mV_STEPS)
164
+#define AXP803_DCDC234_1220mV_START	0x47
165
+#define AXP803_DCDC234_1220mV_STEPS	4
166
+#define AXP803_DCDC234_1220mV_END	\
167
+	(AXP803_DCDC234_1220mV_START + AXP803_DCDC234_1220mV_STEPS)
168
+#define AXP803_DCDC234_NUM_VOLTAGES	76
169
+
170
+#define AXP803_DCDC5_800mV_START	0x00
171
+#define AXP803_DCDC5_800mV_STEPS	32
172
+#define AXP803_DCDC5_800mV_END		\
173
+	(AXP803_DCDC5_800mV_START + AXP803_DCDC5_800mV_STEPS)
174
+#define AXP803_DCDC5_1140mV_START	0x21
175
+#define AXP803_DCDC5_1140mV_STEPS	35
176
+#define AXP803_DCDC5_1140mV_END		\
177
+	(AXP803_DCDC5_1140mV_START + AXP803_DCDC5_1140mV_STEPS)
178
+#define AXP803_DCDC5_NUM_VOLTAGES	69
179
+
180
+#define AXP803_DCDC6_600mV_START	0x00
181
+#define AXP803_DCDC6_600mV_STEPS	50
182
+#define AXP803_DCDC6_600mV_END		\
183
+	(AXP803_DCDC6_600mV_START + AXP803_DCDC6_600mV_STEPS)
184
+#define AXP803_DCDC6_1120mV_START	0x33
185
+#define AXP803_DCDC6_1120mV_STEPS	20
186
+#define AXP803_DCDC6_1120mV_END		\
187
+	(AXP803_DCDC6_1120mV_START + AXP803_DCDC6_1120mV_STEPS)
188
+#define AXP803_DCDC6_NUM_VOLTAGES	72
189
+
190
+#define AXP803_DLDO2_700mV_START	0x00
191
+#define AXP803_DLDO2_700mV_STEPS	26
192
+#define AXP803_DLDO2_700mV_END		\
193
+	(AXP803_DLDO2_700mV_START + AXP803_DLDO2_700mV_STEPS)
194
+#define AXP803_DLDO2_3400mV_START	0x1b
195
+#define AXP803_DLDO2_3400mV_STEPS	4
196
+#define AXP803_DLDO2_3400mV_END		\
197
+	(AXP803_DLDO2_3400mV_START + AXP803_DLDO2_3400mV_STEPS)
198
+#define AXP803_DLDO2_NUM_VOLTAGES	32
199
+
200
+#define AXP806_DCDCA_V_CTRL_MASK	GENMASK(6, 0)
201
+#define AXP806_DCDCB_V_CTRL_MASK	GENMASK(4, 0)
202
+#define AXP806_DCDCC_V_CTRL_MASK	GENMASK(6, 0)
203
+#define AXP806_DCDCD_V_CTRL_MASK	GENMASK(5, 0)
204
+#define AXP806_DCDCE_V_CTRL_MASK	GENMASK(4, 0)
205
+#define AXP806_ALDO1_V_CTRL_MASK	GENMASK(4, 0)
206
+#define AXP806_ALDO2_V_CTRL_MASK	GENMASK(4, 0)
207
+#define AXP806_ALDO3_V_CTRL_MASK	GENMASK(4, 0)
208
+#define AXP806_BLDO1_V_CTRL_MASK	GENMASK(3, 0)
209
+#define AXP806_BLDO2_V_CTRL_MASK	GENMASK(3, 0)
210
+#define AXP806_BLDO3_V_CTRL_MASK	GENMASK(3, 0)
211
+#define AXP806_BLDO4_V_CTRL_MASK	GENMASK(3, 0)
212
+#define AXP806_CLDO1_V_CTRL_MASK	GENMASK(4, 0)
213
+#define AXP806_CLDO2_V_CTRL_MASK	GENMASK(4, 0)
214
+#define AXP806_CLDO3_V_CTRL_MASK	GENMASK(4, 0)
215
+
216
+#define AXP806_PWR_OUT_DCDCA_MASK	BIT_MASK(0)
217
+#define AXP806_PWR_OUT_DCDCB_MASK	BIT_MASK(1)
218
+#define AXP806_PWR_OUT_DCDCC_MASK	BIT_MASK(2)
219
+#define AXP806_PWR_OUT_DCDCD_MASK	BIT_MASK(3)
220
+#define AXP806_PWR_OUT_DCDCE_MASK	BIT_MASK(4)
221
+#define AXP806_PWR_OUT_ALDO1_MASK	BIT_MASK(5)
222
+#define AXP806_PWR_OUT_ALDO2_MASK	BIT_MASK(6)
223
+#define AXP806_PWR_OUT_ALDO3_MASK	BIT_MASK(7)
224
+#define AXP806_PWR_OUT_BLDO1_MASK	BIT_MASK(0)
225
+#define AXP806_PWR_OUT_BLDO2_MASK	BIT_MASK(1)
226
+#define AXP806_PWR_OUT_BLDO3_MASK	BIT_MASK(2)
227
+#define AXP806_PWR_OUT_BLDO4_MASK	BIT_MASK(3)
228
+#define AXP806_PWR_OUT_CLDO1_MASK	BIT_MASK(4)
229
+#define AXP806_PWR_OUT_CLDO2_MASK	BIT_MASK(5)
230
+#define AXP806_PWR_OUT_CLDO3_MASK	BIT_MASK(6)
231
+#define AXP806_PWR_OUT_SW_MASK		BIT_MASK(7)
232
+
233
+#define AXP806_DCDCAB_POLYPHASE_DUAL	0x40
234
+#define AXP806_DCDCABC_POLYPHASE_TRI	0x80
235
+#define AXP806_DCDCABC_POLYPHASE_MASK	GENMASK(7, 6)
236
+
237
+#define AXP806_DCDCDE_POLYPHASE_DUAL	BIT(5)
238
+
239
+#define AXP806_DCDCA_600mV_START	0x00
240
+#define AXP806_DCDCA_600mV_STEPS	50
241
+#define AXP806_DCDCA_600mV_END		\
242
+	(AXP806_DCDCA_600mV_START + AXP806_DCDCA_600mV_STEPS)
243
+#define AXP806_DCDCA_1120mV_START	0x33
244
+#define AXP806_DCDCA_1120mV_STEPS	20
245
+#define AXP806_DCDCA_1120mV_END		\
246
+	(AXP806_DCDCA_1120mV_START + AXP806_DCDCA_1120mV_STEPS)
247
+#define AXP806_DCDCA_NUM_VOLTAGES	72
248
+
249
+#define AXP806_DCDCD_600mV_START	0x00
250
+#define AXP806_DCDCD_600mV_STEPS	45
251
+#define AXP806_DCDCD_600mV_END		\
252
+	(AXP806_DCDCD_600mV_START + AXP806_DCDCD_600mV_STEPS)
253
+#define AXP806_DCDCD_1600mV_START	0x2e
254
+#define AXP806_DCDCD_1600mV_STEPS	17
255
+#define AXP806_DCDCD_1600mV_END		\
256
+	(AXP806_DCDCD_1600mV_START + AXP806_DCDCD_1600mV_STEPS)
257
+#define AXP806_DCDCD_NUM_VOLTAGES	64
258
+
259
+#define AXP809_DCDC4_600mV_START	0x00
260
+#define AXP809_DCDC4_600mV_STEPS	47
261
+#define AXP809_DCDC4_600mV_END		\
262
+	(AXP809_DCDC4_600mV_START + AXP809_DCDC4_600mV_STEPS)
263
+#define AXP809_DCDC4_1800mV_START	0x30
264
+#define AXP809_DCDC4_1800mV_STEPS	8
265
+#define AXP809_DCDC4_1800mV_END		\
266
+	(AXP809_DCDC4_1800mV_START + AXP809_DCDC4_1800mV_STEPS)
267
+#define AXP809_DCDC4_NUM_VOLTAGES	57
268
+
269
+#define AXP813_DCDC7_V_OUT_MASK		GENMASK(6, 0)
270
+
271
+#define AXP813_PWR_OUT_DCDC7_MASK	BIT_MASK(6)
40272 
41273 #define AXP_DESC_IO(_family, _id, _match, _supply, _min, _max, _step, _vreg,	\
42274 		    _vmask, _ereg, _emask, _enable_val, _disable_val)		\
....@@ -128,6 +360,128 @@
128360 		.ops		= &axp20x_ops_range,				\
129361 	}
130362 
363
+static const int axp209_dcdc2_ldo3_slew_rates[] = {
364
+	1600,
365
+	 800,
366
+};
367
+
368
+static int axp20x_set_ramp_delay(struct regulator_dev *rdev, int ramp)
369
+{
370
+	struct axp20x_dev *axp20x = rdev_get_drvdata(rdev);
371
+	int id = rdev_get_id(rdev);
372
+	u8 reg, mask, enable, cfg = 0xff;
373
+	const int *slew_rates;
374
+	int rate_count = 0;
375
+
376
+	switch (axp20x->variant) {
377
+	case AXP209_ID:
378
+		if (id == AXP20X_DCDC2) {
379
+			slew_rates = axp209_dcdc2_ldo3_slew_rates;
380
+			rate_count = ARRAY_SIZE(axp209_dcdc2_ldo3_slew_rates);
381
+			reg = AXP20X_DCDC2_LDO3_V_RAMP;
382
+			mask = AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_RATE_MASK |
383
+			       AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_EN_MASK;
384
+			enable = (ramp > 0) ?
385
+				 AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_EN : 0;
386
+			break;
387
+		}
388
+
389
+		if (id == AXP20X_LDO3) {
390
+			slew_rates = axp209_dcdc2_ldo3_slew_rates;
391
+			rate_count = ARRAY_SIZE(axp209_dcdc2_ldo3_slew_rates);
392
+			reg = AXP20X_DCDC2_LDO3_V_RAMP;
393
+			mask = AXP20X_DCDC2_LDO3_V_RAMP_LDO3_RATE_MASK |
394
+			       AXP20X_DCDC2_LDO3_V_RAMP_LDO3_EN_MASK;
395
+			enable = (ramp > 0) ?
396
+				 AXP20X_DCDC2_LDO3_V_RAMP_LDO3_EN : 0;
397
+			break;
398
+		}
399
+
400
+		if (rate_count > 0)
401
+			break;
402
+
403
+		fallthrough;
404
+	default:
405
+		/* Not supported for this regulator */
406
+		return -ENOTSUPP;
407
+	}
408
+
409
+	if (ramp == 0) {
410
+		cfg = enable;
411
+	} else {
412
+		int i;
413
+
414
+		for (i = 0; i < rate_count; i++) {
415
+			if (ramp > slew_rates[i])
416
+				break;
417
+
418
+			if (id == AXP20X_DCDC2)
419
+				cfg = AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_RATE(i);
420
+			else
421
+				cfg = AXP20X_DCDC2_LDO3_V_RAMP_LDO3_RATE(i);
422
+		}
423
+
424
+		if (cfg == 0xff) {
425
+			dev_err(axp20x->dev, "unsupported ramp value %d", ramp);
426
+			return -EINVAL;
427
+		}
428
+
429
+		cfg |= enable;
430
+	}
431
+
432
+	return regmap_update_bits(axp20x->regmap, reg, mask, cfg);
433
+}
434
+
435
+static int axp20x_regulator_enable_regmap(struct regulator_dev *rdev)
436
+{
437
+	struct axp20x_dev *axp20x = rdev_get_drvdata(rdev);
438
+	int id = rdev_get_id(rdev);
439
+
440
+	switch (axp20x->variant) {
441
+	case AXP209_ID:
442
+		if ((id == AXP20X_LDO3) &&
443
+		    rdev->constraints && rdev->constraints->soft_start) {
444
+			int v_out;
445
+			int ret;
446
+
447
+			/*
448
+			 * On some boards, the LDO3 can be overloaded when
449
+			 * turning on, causing the entire PMIC to shutdown
450
+			 * without warning. Turning it on at the minimal voltage
451
+			 * and then setting the voltage to the requested value
452
+			 * works reliably.
453
+			 */
454
+			if (regulator_is_enabled_regmap(rdev))
455
+				break;
456
+
457
+			v_out = regulator_get_voltage_sel_regmap(rdev);
458
+			if (v_out < 0)
459
+				return v_out;
460
+
461
+			if (v_out == 0)
462
+				break;
463
+
464
+			ret = regulator_set_voltage_sel_regmap(rdev, 0x00);
465
+			/*
466
+			 * A small pause is needed between
467
+			 * setting the voltage and enabling the LDO to give the
468
+			 * internal state machine time to process the request.
469
+			 */
470
+			usleep_range(1000, 5000);
471
+			ret |= regulator_enable_regmap(rdev);
472
+			ret |= regulator_set_voltage_sel_regmap(rdev, v_out);
473
+
474
+			return ret;
475
+		}
476
+		break;
477
+	default:
478
+		/* No quirks */
479
+		break;
480
+	}
481
+
482
+	return regulator_enable_regmap(rdev);
483
+};
484
+
131485 static const struct regulator_ops axp20x_ops_fixed = {
132486 	.list_voltage		= regulator_list_voltage_linear,
133487 };
....@@ -145,9 +499,10 @@
145499 	.set_voltage_sel	= regulator_set_voltage_sel_regmap,
146500 	.get_voltage_sel	= regulator_get_voltage_sel_regmap,
147501 	.list_voltage		= regulator_list_voltage_linear,
148
-	.enable			= regulator_enable_regmap,
502
+	.enable			= axp20x_regulator_enable_regmap,
149503 	.disable		= regulator_disable_regmap,
150504 	.is_enabled		= regulator_is_enabled_regmap,
505
+	.set_ramp_delay		= axp20x_set_ramp_delay,
151506 };
152507 
153508 static const struct regulator_ops axp20x_ops_sw = {
....@@ -156,78 +511,117 @@
156511 	.is_enabled		= regulator_is_enabled_regmap,
157512 };
158513 
159
-static const struct regulator_linear_range axp20x_ldo4_ranges[] = {
160
-	REGULATOR_LINEAR_RANGE(1250000, 0x0, 0x0, 0),
161
-	REGULATOR_LINEAR_RANGE(1300000, 0x1, 0x8, 100000),
162
-	REGULATOR_LINEAR_RANGE(2500000, 0x9, 0x9, 0),
163
-	REGULATOR_LINEAR_RANGE(2700000, 0xa, 0xb, 100000),
164
-	REGULATOR_LINEAR_RANGE(3000000, 0xc, 0xf, 100000),
514
+static const struct linear_range axp20x_ldo4_ranges[] = {
515
+	REGULATOR_LINEAR_RANGE(1250000,
516
+			       AXP20X_LDO4_V_OUT_1250mV_START,
517
+			       AXP20X_LDO4_V_OUT_1250mV_END,
518
+			       0),
519
+	REGULATOR_LINEAR_RANGE(1300000,
520
+			       AXP20X_LDO4_V_OUT_1300mV_START,
521
+			       AXP20X_LDO4_V_OUT_1300mV_END,
522
+			       100000),
523
+	REGULATOR_LINEAR_RANGE(2500000,
524
+			       AXP20X_LDO4_V_OUT_2500mV_START,
525
+			       AXP20X_LDO4_V_OUT_2500mV_END,
526
+			       0),
527
+	REGULATOR_LINEAR_RANGE(2700000,
528
+			       AXP20X_LDO4_V_OUT_2700mV_START,
529
+			       AXP20X_LDO4_V_OUT_2700mV_END,
530
+			       100000),
531
+	REGULATOR_LINEAR_RANGE(3000000,
532
+			       AXP20X_LDO4_V_OUT_3000mV_START,
533
+			       AXP20X_LDO4_V_OUT_3000mV_END,
534
+			       100000),
165535 };
166536 
167537 static const struct regulator_desc axp20x_regulators[] = {
168538 	AXP_DESC(AXP20X, DCDC2, "dcdc2", "vin2", 700, 2275, 25,
169
-		 AXP20X_DCDC2_V_OUT, 0x3f, AXP20X_PWR_OUT_CTRL, 0x10),
539
+		 AXP20X_DCDC2_V_OUT, AXP20X_DCDC2_V_OUT_MASK,
540
+		 AXP20X_PWR_OUT_CTRL, AXP20X_PWR_OUT_DCDC2_MASK),
170541 	AXP_DESC(AXP20X, DCDC3, "dcdc3", "vin3", 700, 3500, 25,
171
-		 AXP20X_DCDC3_V_OUT, 0x7f, AXP20X_PWR_OUT_CTRL, 0x02),
542
+		 AXP20X_DCDC3_V_OUT, AXP20X_DCDC3_V_OUT_MASK,
543
+		 AXP20X_PWR_OUT_CTRL, AXP20X_PWR_OUT_DCDC3_MASK),
172544 	AXP_DESC_FIXED(AXP20X, LDO1, "ldo1", "acin", 1300),
173545 	AXP_DESC(AXP20X, LDO2, "ldo2", "ldo24in", 1800, 3300, 100,
174
-		 AXP20X_LDO24_V_OUT, 0xf0, AXP20X_PWR_OUT_CTRL, 0x04),
546
+		 AXP20X_LDO24_V_OUT, AXP20X_LDO2_V_OUT_MASK,
547
+		 AXP20X_PWR_OUT_CTRL, AXP20X_PWR_OUT_LDO2_MASK),
175548 	AXP_DESC(AXP20X, LDO3, "ldo3", "ldo3in", 700, 3500, 25,
176
-		 AXP20X_LDO3_V_OUT, 0x7f, AXP20X_PWR_OUT_CTRL, 0x40),
177
-	AXP_DESC_RANGES(AXP20X, LDO4, "ldo4", "ldo24in", axp20x_ldo4_ranges,
178
-			16, AXP20X_LDO24_V_OUT, 0x0f, AXP20X_PWR_OUT_CTRL,
179
-			0x08),
549
+		 AXP20X_LDO3_V_OUT, AXP20X_LDO3_V_OUT_MASK,
550
+		 AXP20X_PWR_OUT_CTRL, AXP20X_PWR_OUT_LDO3_MASK),
551
+	AXP_DESC_RANGES(AXP20X, LDO4, "ldo4", "ldo24in",
552
+			axp20x_ldo4_ranges, AXP20X_LDO4_V_OUT_NUM_VOLTAGES,
553
+			AXP20X_LDO24_V_OUT, AXP20X_LDO4_V_OUT_MASK,
554
+			AXP20X_PWR_OUT_CTRL, AXP20X_PWR_OUT_LDO4_MASK),
180555 	AXP_DESC_IO(AXP20X, LDO5, "ldo5", "ldo5in", 1800, 3300, 100,
181
-		    AXP20X_LDO5_V_OUT, 0xf0, AXP20X_GPIO0_CTRL, 0x07,
556
+		    AXP20X_LDO5_V_OUT, AXP20X_LDO5_V_OUT_MASK,
557
+		    AXP20X_GPIO0_CTRL, AXP20X_GPIO0_FUNC_MASK,
182558 		    AXP20X_IO_ENABLED, AXP20X_IO_DISABLED),
183559 };
184560 
185561 static const struct regulator_desc axp22x_regulators[] = {
186562 	AXP_DESC(AXP22X, DCDC1, "dcdc1", "vin1", 1600, 3400, 100,
187
-		 AXP22X_DCDC1_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL1, BIT(1)),
563
+		 AXP22X_DCDC1_V_OUT, AXP22X_DCDC1_V_OUT_MASK,
564
+		 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC1_MASK),
188565 	AXP_DESC(AXP22X, DCDC2, "dcdc2", "vin2", 600, 1540, 20,
189
-		 AXP22X_DCDC2_V_OUT, 0x3f, AXP22X_PWR_OUT_CTRL1, BIT(2)),
566
+		 AXP22X_DCDC2_V_OUT, AXP22X_DCDC2_V_OUT_MASK,
567
+		 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC2_MASK),
190568 	AXP_DESC(AXP22X, DCDC3, "dcdc3", "vin3", 600, 1860, 20,
191
-		 AXP22X_DCDC3_V_OUT, 0x3f, AXP22X_PWR_OUT_CTRL1, BIT(3)),
569
+		 AXP22X_DCDC3_V_OUT, AXP22X_DCDC3_V_OUT_MASK,
570
+		 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC3_MASK),
192571 	AXP_DESC(AXP22X, DCDC4, "dcdc4", "vin4", 600, 1540, 20,
193
-		 AXP22X_DCDC4_V_OUT, 0x3f, AXP22X_PWR_OUT_CTRL1, BIT(4)),
572
+		 AXP22X_DCDC4_V_OUT, AXP22X_DCDC4_V_OUT_MASK,
573
+		 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC4_MASK),
194574 	AXP_DESC(AXP22X, DCDC5, "dcdc5", "vin5", 1000, 2550, 50,
195
-		 AXP22X_DCDC5_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL1, BIT(5)),
575
+		 AXP22X_DCDC5_V_OUT, AXP22X_DCDC5_V_OUT_MASK,
576
+		 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC5_MASK),
196577 	/* secondary switchable output of DCDC1 */
197
-	AXP_DESC_SW(AXP22X, DC1SW, "dc1sw", NULL, AXP22X_PWR_OUT_CTRL2,
198
-		    BIT(7)),
578
+	AXP_DESC_SW(AXP22X, DC1SW, "dc1sw", NULL,
579
+		    AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DC1SW_MASK),
199580 	/* LDO regulator internally chained to DCDC5 */
200581 	AXP_DESC(AXP22X, DC5LDO, "dc5ldo", NULL, 700, 1400, 100,
201
-		 AXP22X_DC5LDO_V_OUT, 0x7, AXP22X_PWR_OUT_CTRL1, BIT(0)),
582
+		 AXP22X_DC5LDO_V_OUT, AXP22X_DC5LDO_V_OUT_MASK,
583
+		 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DC5LDO_MASK),
202584 	AXP_DESC(AXP22X, ALDO1, "aldo1", "aldoin", 700, 3300, 100,
203
-		 AXP22X_ALDO1_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL1, BIT(6)),
585
+		 AXP22X_ALDO1_V_OUT, AXP22X_ALDO1_V_OUT_MASK,
586
+		 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_ALDO1_MASK),
204587 	AXP_DESC(AXP22X, ALDO2, "aldo2", "aldoin", 700, 3300, 100,
205
-		 AXP22X_ALDO2_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL1, BIT(7)),
588
+		 AXP22X_ALDO2_V_OUT, AXP22X_ALDO2_V_OUT_MASK,
589
+		 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_ALDO2_MASK),
206590 	AXP_DESC(AXP22X, ALDO3, "aldo3", "aldoin", 700, 3300, 100,
207
-		 AXP22X_ALDO3_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL3, BIT(7)),
591
+		 AXP22X_ALDO3_V_OUT, AXP22X_ALDO3_V_OUT_MASK,
592
+		 AXP22X_PWR_OUT_CTRL3, AXP22X_PWR_OUT_ALDO3_MASK),
208593 	AXP_DESC(AXP22X, DLDO1, "dldo1", "dldoin", 700, 3300, 100,
209
-		 AXP22X_DLDO1_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(3)),
594
+		 AXP22X_DLDO1_V_OUT, AXP22X_DLDO1_V_OUT_MASK,
595
+		 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO1_MASK),
210596 	AXP_DESC(AXP22X, DLDO2, "dldo2", "dldoin", 700, 3300, 100,
211
-		 AXP22X_DLDO2_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(4)),
597
+		 AXP22X_DLDO2_V_OUT, AXP22X_DLDO2_V_OUT_MASK,
598
+		 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO2_MASK),
212599 	AXP_DESC(AXP22X, DLDO3, "dldo3", "dldoin", 700, 3300, 100,
213
-		 AXP22X_DLDO3_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(5)),
600
+		 AXP22X_DLDO3_V_OUT, AXP22X_DLDO3_V_OUT_MASK,
601
+		 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO3_MASK),
214602 	AXP_DESC(AXP22X, DLDO4, "dldo4", "dldoin", 700, 3300, 100,
215
-		 AXP22X_DLDO4_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(6)),
603
+		 AXP22X_DLDO4_V_OUT, AXP22X_DLDO4_V_OUT_MASK,
604
+		 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO4_MASK),
216605 	AXP_DESC(AXP22X, ELDO1, "eldo1", "eldoin", 700, 3300, 100,
217
-		 AXP22X_ELDO1_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(0)),
606
+		 AXP22X_ELDO1_V_OUT, AXP22X_ELDO1_V_OUT_MASK,
607
+		 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO1_MASK),
218608 	AXP_DESC(AXP22X, ELDO2, "eldo2", "eldoin", 700, 3300, 100,
219
-		 AXP22X_ELDO2_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(1)),
609
+		 AXP22X_ELDO2_V_OUT, AXP22X_ELDO2_V_OUT_MASK,
610
+		 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO2_MASK),
220611 	AXP_DESC(AXP22X, ELDO3, "eldo3", "eldoin", 700, 3300, 100,
221
-		 AXP22X_ELDO3_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(2)),
612
+		 AXP22X_ELDO3_V_OUT, AXP22X_ELDO3_V_OUT_MASK,
613
+		 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO3_MASK),
222614 	/* Note the datasheet only guarantees reliable operation up to
223615 	 * 3.3V, this needs to be enforced via dts provided constraints */
224616 	AXP_DESC_IO(AXP22X, LDO_IO0, "ldo_io0", "ips", 700, 3800, 100,
225
-		    AXP22X_LDO_IO0_V_OUT, 0x1f, AXP20X_GPIO0_CTRL, 0x07,
617
+		    AXP22X_LDO_IO0_V_OUT, AXP22X_LDO_IO0_V_OUT_MASK,
618
+		    AXP20X_GPIO0_CTRL, AXP20X_GPIO0_FUNC_MASK,
226619 		    AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
227620 	/* Note the datasheet only guarantees reliable operation up to
228621 	 * 3.3V, this needs to be enforced via dts provided constraints */
229622 	AXP_DESC_IO(AXP22X, LDO_IO1, "ldo_io1", "ips", 700, 3800, 100,
230
-		    AXP22X_LDO_IO1_V_OUT, 0x1f, AXP20X_GPIO1_CTRL, 0x07,
623
+		    AXP22X_LDO_IO1_V_OUT, AXP22X_LDO_IO1_V_OUT_MASK,
624
+		    AXP20X_GPIO1_CTRL, AXP20X_GPIO1_FUNC_MASK,
231625 		    AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
232626 	AXP_DESC_FIXED(AXP22X, RTC_LDO, "rtc_ldo", "ips", 3000),
233627 };
....@@ -240,240 +634,354 @@
240634 	.type		= REGULATOR_VOLTAGE,
241635 	.owner		= THIS_MODULE,
242636 	.enable_reg	= AXP20X_VBUS_IPSOUT_MGMT,
243
-	.enable_mask	= BIT(2),
637
+	.enable_mask	= AXP20X_VBUS_IPSOUT_MGMT_MASK,
244638 	.ops		= &axp20x_ops_sw,
245639 };
246640 
247641 /* DCDC ranges shared with AXP813 */
248
-static const struct regulator_linear_range axp803_dcdc234_ranges[] = {
249
-	REGULATOR_LINEAR_RANGE(500000, 0x0, 0x46, 10000),
250
-	REGULATOR_LINEAR_RANGE(1220000, 0x47, 0x4b, 20000),
642
+static const struct linear_range axp803_dcdc234_ranges[] = {
643
+	REGULATOR_LINEAR_RANGE(500000,
644
+			       AXP803_DCDC234_500mV_START,
645
+			       AXP803_DCDC234_500mV_END,
646
+			       10000),
647
+	REGULATOR_LINEAR_RANGE(1220000,
648
+			       AXP803_DCDC234_1220mV_START,
649
+			       AXP803_DCDC234_1220mV_END,
650
+			       20000),
251651 };
252652 
253
-static const struct regulator_linear_range axp803_dcdc5_ranges[] = {
254
-	REGULATOR_LINEAR_RANGE(800000, 0x0, 0x20, 10000),
255
-	REGULATOR_LINEAR_RANGE(1140000, 0x21, 0x44, 20000),
653
+static const struct linear_range axp803_dcdc5_ranges[] = {
654
+	REGULATOR_LINEAR_RANGE(800000,
655
+			       AXP803_DCDC5_800mV_START,
656
+			       AXP803_DCDC5_800mV_END,
657
+			       10000),
658
+	REGULATOR_LINEAR_RANGE(1140000,
659
+			       AXP803_DCDC5_1140mV_START,
660
+			       AXP803_DCDC5_1140mV_END,
661
+			       20000),
256662 };
257663 
258
-static const struct regulator_linear_range axp803_dcdc6_ranges[] = {
259
-	REGULATOR_LINEAR_RANGE(600000, 0x0, 0x32, 10000),
260
-	REGULATOR_LINEAR_RANGE(1120000, 0x33, 0x47, 20000),
664
+static const struct linear_range axp803_dcdc6_ranges[] = {
665
+	REGULATOR_LINEAR_RANGE(600000,
666
+			       AXP803_DCDC6_600mV_START,
667
+			       AXP803_DCDC6_600mV_END,
668
+			       10000),
669
+	REGULATOR_LINEAR_RANGE(1120000,
670
+			       AXP803_DCDC6_1120mV_START,
671
+			       AXP803_DCDC6_1120mV_END,
672
+			       20000),
261673 };
262674 
263
-/* AXP806's CLDO2 and AXP809's DLDO1 shares the same range */
264
-static const struct regulator_linear_range axp803_dldo2_ranges[] = {
265
-	REGULATOR_LINEAR_RANGE(700000, 0x0, 0x1a, 100000),
266
-	REGULATOR_LINEAR_RANGE(3400000, 0x1b, 0x1f, 200000),
675
+/* AXP806's CLDO2 and AXP809's DLDO1 share the same range */
676
+static const struct linear_range axp803_dldo2_ranges[] = {
677
+	REGULATOR_LINEAR_RANGE(700000,
678
+			       AXP803_DLDO2_700mV_START,
679
+			       AXP803_DLDO2_700mV_END,
680
+			       100000),
681
+	REGULATOR_LINEAR_RANGE(3400000,
682
+			       AXP803_DLDO2_3400mV_START,
683
+			       AXP803_DLDO2_3400mV_END,
684
+			       200000),
267685 };
268686 
269687 static const struct regulator_desc axp803_regulators[] = {
270688 	AXP_DESC(AXP803, DCDC1, "dcdc1", "vin1", 1600, 3400, 100,
271
-		 AXP803_DCDC1_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL1, BIT(0)),
272
-	AXP_DESC_RANGES(AXP803, DCDC2, "dcdc2", "vin2", axp803_dcdc234_ranges,
273
-			76, AXP803_DCDC2_V_OUT, 0x7f, AXP22X_PWR_OUT_CTRL1,
274
-			BIT(1)),
275
-	AXP_DESC_RANGES(AXP803, DCDC3, "dcdc3", "vin3", axp803_dcdc234_ranges,
276
-			76, AXP803_DCDC3_V_OUT, 0x7f, AXP22X_PWR_OUT_CTRL1,
277
-			BIT(2)),
278
-	AXP_DESC_RANGES(AXP803, DCDC4, "dcdc4", "vin4", axp803_dcdc234_ranges,
279
-			76, AXP803_DCDC4_V_OUT, 0x7f, AXP22X_PWR_OUT_CTRL1,
280
-			BIT(3)),
281
-	AXP_DESC_RANGES(AXP803, DCDC5, "dcdc5", "vin5", axp803_dcdc5_ranges,
282
-			68, AXP803_DCDC5_V_OUT, 0x7f, AXP22X_PWR_OUT_CTRL1,
283
-			BIT(4)),
284
-	AXP_DESC_RANGES(AXP803, DCDC6, "dcdc6", "vin6", axp803_dcdc6_ranges,
285
-			72, AXP803_DCDC6_V_OUT, 0x7f, AXP22X_PWR_OUT_CTRL1,
286
-			BIT(5)),
689
+		 AXP803_DCDC1_V_OUT, AXP803_DCDC1_V_OUT_MASK,
690
+		 AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC1_MASK),
691
+	AXP_DESC_RANGES(AXP803, DCDC2, "dcdc2", "vin2",
692
+			axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES,
693
+			AXP803_DCDC2_V_OUT, AXP803_DCDC2_V_OUT_MASK,
694
+			AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC2_MASK),
695
+	AXP_DESC_RANGES(AXP803, DCDC3, "dcdc3", "vin3",
696
+			axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES,
697
+			AXP803_DCDC3_V_OUT, AXP803_DCDC3_V_OUT_MASK,
698
+			AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC3_MASK),
699
+	AXP_DESC_RANGES(AXP803, DCDC4, "dcdc4", "vin4",
700
+			axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES,
701
+			AXP803_DCDC4_V_OUT, AXP803_DCDC4_V_OUT_MASK,
702
+			AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC4_MASK),
703
+	AXP_DESC_RANGES(AXP803, DCDC5, "dcdc5", "vin5",
704
+			axp803_dcdc5_ranges, AXP803_DCDC5_NUM_VOLTAGES,
705
+			AXP803_DCDC5_V_OUT, AXP803_DCDC5_V_OUT_MASK,
706
+			AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC5_MASK),
707
+	AXP_DESC_RANGES(AXP803, DCDC6, "dcdc6", "vin6",
708
+			axp803_dcdc6_ranges, AXP803_DCDC6_NUM_VOLTAGES,
709
+			AXP803_DCDC6_V_OUT, AXP803_DCDC6_V_OUT_MASK,
710
+			AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC6_MASK),
287711 	/* secondary switchable output of DCDC1 */
288
-	AXP_DESC_SW(AXP803, DC1SW, "dc1sw", NULL, AXP22X_PWR_OUT_CTRL2,
289
-		    BIT(7)),
712
+	AXP_DESC_SW(AXP803, DC1SW, "dc1sw", NULL,
713
+		    AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DC1SW_MASK),
290714 	AXP_DESC(AXP803, ALDO1, "aldo1", "aldoin", 700, 3300, 100,
291
-		 AXP22X_ALDO1_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL3, BIT(5)),
715
+		 AXP22X_ALDO1_V_OUT, AXP22X_ALDO1_V_OUT_MASK,
716
+		 AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO1_MASK),
292717 	AXP_DESC(AXP803, ALDO2, "aldo2", "aldoin", 700, 3300, 100,
293
-		 AXP22X_ALDO2_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL3, BIT(6)),
718
+		 AXP22X_ALDO2_V_OUT, AXP22X_ALDO2_V_OUT_MASK,
719
+		 AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO2_MASK),
294720 	AXP_DESC(AXP803, ALDO3, "aldo3", "aldoin", 700, 3300, 100,
295
-		 AXP22X_ALDO3_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL3, BIT(7)),
721
+		 AXP22X_ALDO3_V_OUT, AXP22X_ALDO3_V_OUT_MASK,
722
+		 AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO3_MASK),
296723 	AXP_DESC(AXP803, DLDO1, "dldo1", "dldoin", 700, 3300, 100,
297
-		 AXP22X_DLDO1_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(3)),
298
-	AXP_DESC_RANGES(AXP803, DLDO2, "dldo2", "dldoin", axp803_dldo2_ranges,
299
-			32, AXP22X_DLDO2_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2,
300
-			BIT(4)),
724
+		 AXP22X_DLDO1_V_OUT, AXP22X_DLDO1_V_OUT_MASK,
725
+		 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO1_MASK),
726
+	AXP_DESC_RANGES(AXP803, DLDO2, "dldo2", "dldoin",
727
+			axp803_dldo2_ranges, AXP803_DLDO2_NUM_VOLTAGES,
728
+			AXP22X_DLDO2_V_OUT, AXP22X_DLDO2_V_OUT_MASK,
729
+			AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO2_MASK),
301730 	AXP_DESC(AXP803, DLDO3, "dldo3", "dldoin", 700, 3300, 100,
302
-		 AXP22X_DLDO3_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(5)),
731
+		 AXP22X_DLDO3_V_OUT, AXP22X_DLDO3_V_OUT_MASK,
732
+		 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO3_MASK),
303733 	AXP_DESC(AXP803, DLDO4, "dldo4", "dldoin", 700, 3300, 100,
304
-		 AXP22X_DLDO4_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(6)),
734
+		 AXP22X_DLDO4_V_OUT, AXP22X_DLDO4_V_OUT_MASK,
735
+		 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO4_MASK),
305736 	AXP_DESC(AXP803, ELDO1, "eldo1", "eldoin", 700, 1900, 50,
306
-		 AXP22X_ELDO1_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(0)),
737
+		 AXP22X_ELDO1_V_OUT, AXP22X_ELDO1_V_OUT_MASK,
738
+		 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO1_MASK),
307739 	AXP_DESC(AXP803, ELDO2, "eldo2", "eldoin", 700, 1900, 50,
308
-		 AXP22X_ELDO2_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(1)),
740
+		 AXP22X_ELDO2_V_OUT, AXP22X_ELDO2_V_OUT_MASK,
741
+		 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO2_MASK),
309742 	AXP_DESC(AXP803, ELDO3, "eldo3", "eldoin", 700, 1900, 50,
310
-		 AXP22X_ELDO3_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(2)),
743
+		 AXP22X_ELDO3_V_OUT, AXP22X_ELDO3_V_OUT_MASK,
744
+		 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO3_MASK),
311745 	AXP_DESC(AXP803, FLDO1, "fldo1", "fldoin", 700, 1450, 50,
312
-		 AXP803_FLDO1_V_OUT, 0x0f, AXP22X_PWR_OUT_CTRL3, BIT(2)),
746
+		 AXP803_FLDO1_V_OUT, AXP803_FLDO1_V_OUT_MASK,
747
+		 AXP22X_PWR_OUT_CTRL3, AXP803_PWR_OUT_FLDO1_MASK),
313748 	AXP_DESC(AXP803, FLDO2, "fldo2", "fldoin", 700, 1450, 50,
314
-		 AXP803_FLDO2_V_OUT, 0x0f, AXP22X_PWR_OUT_CTRL3, BIT(3)),
749
+		 AXP803_FLDO2_V_OUT, AXP803_FLDO2_V_OUT_MASK,
750
+		 AXP22X_PWR_OUT_CTRL3, AXP803_PWR_OUT_FLDO2_MASK),
315751 	AXP_DESC_IO(AXP803, LDO_IO0, "ldo-io0", "ips", 700, 3300, 100,
316
-		    AXP22X_LDO_IO0_V_OUT, 0x1f, AXP20X_GPIO0_CTRL, 0x07,
752
+		    AXP22X_LDO_IO0_V_OUT, AXP22X_LDO_IO0_V_OUT_MASK,
753
+		    AXP20X_GPIO0_CTRL, AXP20X_GPIO0_FUNC_MASK,
317754 		    AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
318755 	AXP_DESC_IO(AXP803, LDO_IO1, "ldo-io1", "ips", 700, 3300, 100,
319
-		    AXP22X_LDO_IO1_V_OUT, 0x1f, AXP20X_GPIO1_CTRL, 0x07,
756
+		    AXP22X_LDO_IO1_V_OUT, AXP22X_LDO_IO1_V_OUT_MASK,
757
+		    AXP20X_GPIO1_CTRL, AXP20X_GPIO1_FUNC_MASK,
320758 		    AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
321759 	AXP_DESC_FIXED(AXP803, RTC_LDO, "rtc-ldo", "ips", 3000),
322760 };
323761 
324
-static const struct regulator_linear_range axp806_dcdca_ranges[] = {
325
-	REGULATOR_LINEAR_RANGE(600000, 0x0, 0x32, 10000),
326
-	REGULATOR_LINEAR_RANGE(1120000, 0x33, 0x47, 20000),
762
+static const struct linear_range axp806_dcdca_ranges[] = {
763
+	REGULATOR_LINEAR_RANGE(600000,
764
+			       AXP806_DCDCA_600mV_START,
765
+			       AXP806_DCDCA_600mV_END,
766
+			       10000),
767
+	REGULATOR_LINEAR_RANGE(1120000,
768
+			       AXP806_DCDCA_1120mV_START,
769
+			       AXP806_DCDCA_1120mV_END,
770
+			       20000),
327771 };
328772 
329
-static const struct regulator_linear_range axp806_dcdcd_ranges[] = {
330
-	REGULATOR_LINEAR_RANGE(600000, 0x0, 0x2d, 20000),
331
-	REGULATOR_LINEAR_RANGE(1600000, 0x2e, 0x3f, 100000),
773
+static const struct linear_range axp806_dcdcd_ranges[] = {
774
+	REGULATOR_LINEAR_RANGE(600000,
775
+			       AXP806_DCDCD_600mV_START,
776
+			       AXP806_DCDCD_600mV_END,
777
+			       20000),
778
+	REGULATOR_LINEAR_RANGE(1600000,
779
+			       AXP806_DCDCD_1600mV_START,
780
+			       AXP806_DCDCD_1600mV_END,
781
+			       100000),
332782 };
333783 
334784 static const struct regulator_desc axp806_regulators[] = {
335
-	AXP_DESC_RANGES(AXP806, DCDCA, "dcdca", "vina", axp806_dcdca_ranges,
336
-			72, AXP806_DCDCA_V_CTRL, 0x7f, AXP806_PWR_OUT_CTRL1,
337
-			BIT(0)),
785
+	AXP_DESC_RANGES(AXP806, DCDCA, "dcdca", "vina",
786
+			axp806_dcdca_ranges, AXP806_DCDCA_NUM_VOLTAGES,
787
+			AXP806_DCDCA_V_CTRL, AXP806_DCDCA_V_CTRL_MASK,
788
+			AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_DCDCA_MASK),
338789 	AXP_DESC(AXP806, DCDCB, "dcdcb", "vinb", 1000, 2550, 50,
339
-		 AXP806_DCDCB_V_CTRL, 0x1f, AXP806_PWR_OUT_CTRL1, BIT(1)),
340
-	AXP_DESC_RANGES(AXP806, DCDCC, "dcdcc", "vinc", axp806_dcdca_ranges,
341
-			72, AXP806_DCDCC_V_CTRL, 0x7f, AXP806_PWR_OUT_CTRL1,
342
-			BIT(2)),
343
-	AXP_DESC_RANGES(AXP806, DCDCD, "dcdcd", "vind", axp806_dcdcd_ranges,
344
-			64, AXP806_DCDCD_V_CTRL, 0x3f, AXP806_PWR_OUT_CTRL1,
345
-			BIT(3)),
790
+		 AXP806_DCDCB_V_CTRL, AXP806_DCDCB_V_CTRL_MASK,
791
+		 AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_DCDCB_MASK),
792
+	AXP_DESC_RANGES(AXP806, DCDCC, "dcdcc", "vinc",
793
+			axp806_dcdca_ranges, AXP806_DCDCA_NUM_VOLTAGES,
794
+			AXP806_DCDCC_V_CTRL, AXP806_DCDCC_V_CTRL_MASK,
795
+			AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_DCDCC_MASK),
796
+	AXP_DESC_RANGES(AXP806, DCDCD, "dcdcd", "vind",
797
+			axp806_dcdcd_ranges, AXP806_DCDCD_NUM_VOLTAGES,
798
+			AXP806_DCDCD_V_CTRL, AXP806_DCDCD_V_CTRL_MASK,
799
+			AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_DCDCD_MASK),
346800 	AXP_DESC(AXP806, DCDCE, "dcdce", "vine", 1100, 3400, 100,
347
-		 AXP806_DCDCE_V_CTRL, 0x1f, AXP806_PWR_OUT_CTRL1, BIT(4)),
801
+		 AXP806_DCDCE_V_CTRL, AXP806_DCDCE_V_CTRL_MASK,
802
+		 AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_DCDCE_MASK),
348803 	AXP_DESC(AXP806, ALDO1, "aldo1", "aldoin", 700, 3300, 100,
349
-		 AXP806_ALDO1_V_CTRL, 0x1f, AXP806_PWR_OUT_CTRL1, BIT(5)),
804
+		 AXP806_ALDO1_V_CTRL, AXP806_ALDO1_V_CTRL_MASK,
805
+		 AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_ALDO1_MASK),
350806 	AXP_DESC(AXP806, ALDO2, "aldo2", "aldoin", 700, 3400, 100,
351
-		 AXP806_ALDO2_V_CTRL, 0x1f, AXP806_PWR_OUT_CTRL1, BIT(6)),
807
+		 AXP806_ALDO2_V_CTRL, AXP806_ALDO2_V_CTRL_MASK,
808
+		 AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_ALDO2_MASK),
352809 	AXP_DESC(AXP806, ALDO3, "aldo3", "aldoin", 700, 3300, 100,
353
-		 AXP806_ALDO3_V_CTRL, 0x1f, AXP806_PWR_OUT_CTRL1, BIT(7)),
810
+		 AXP806_ALDO3_V_CTRL, AXP806_ALDO3_V_CTRL_MASK,
811
+		 AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_ALDO3_MASK),
354812 	AXP_DESC(AXP806, BLDO1, "bldo1", "bldoin", 700, 1900, 100,
355
-		 AXP806_BLDO1_V_CTRL, 0x0f, AXP806_PWR_OUT_CTRL2, BIT(0)),
813
+		 AXP806_BLDO1_V_CTRL, AXP806_BLDO1_V_CTRL_MASK,
814
+		 AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_BLDO1_MASK),
356815 	AXP_DESC(AXP806, BLDO2, "bldo2", "bldoin", 700, 1900, 100,
357
-		 AXP806_BLDO2_V_CTRL, 0x0f, AXP806_PWR_OUT_CTRL2, BIT(1)),
816
+		 AXP806_BLDO2_V_CTRL, AXP806_BLDO2_V_CTRL_MASK,
817
+		 AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_BLDO2_MASK),
358818 	AXP_DESC(AXP806, BLDO3, "bldo3", "bldoin", 700, 1900, 100,
359
-		 AXP806_BLDO3_V_CTRL, 0x0f, AXP806_PWR_OUT_CTRL2, BIT(2)),
819
+		 AXP806_BLDO3_V_CTRL, AXP806_BLDO3_V_CTRL_MASK,
820
+		 AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_BLDO3_MASK),
360821 	AXP_DESC(AXP806, BLDO4, "bldo4", "bldoin", 700, 1900, 100,
361
-		 AXP806_BLDO4_V_CTRL, 0x0f, AXP806_PWR_OUT_CTRL2, BIT(3)),
822
+		 AXP806_BLDO4_V_CTRL, AXP806_BLDO4_V_CTRL_MASK,
823
+		 AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_BLDO4_MASK),
362824 	AXP_DESC(AXP806, CLDO1, "cldo1", "cldoin", 700, 3300, 100,
363
-		 AXP806_CLDO1_V_CTRL, 0x1f, AXP806_PWR_OUT_CTRL2, BIT(4)),
364
-	AXP_DESC_RANGES(AXP806, CLDO2, "cldo2", "cldoin", axp803_dldo2_ranges,
365
-			32, AXP806_CLDO2_V_CTRL, 0x1f, AXP806_PWR_OUT_CTRL2,
366
-			BIT(5)),
825
+		 AXP806_CLDO1_V_CTRL, AXP806_CLDO1_V_CTRL_MASK,
826
+		 AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_CLDO1_MASK),
827
+	AXP_DESC_RANGES(AXP806, CLDO2, "cldo2", "cldoin",
828
+			axp803_dldo2_ranges, AXP803_DLDO2_NUM_VOLTAGES,
829
+			AXP806_CLDO2_V_CTRL, AXP806_CLDO2_V_CTRL_MASK,
830
+			AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_CLDO2_MASK),
367831 	AXP_DESC(AXP806, CLDO3, "cldo3", "cldoin", 700, 3300, 100,
368
-		 AXP806_CLDO3_V_CTRL, 0x1f, AXP806_PWR_OUT_CTRL2, BIT(6)),
369
-	AXP_DESC_SW(AXP806, SW, "sw", "swin", AXP806_PWR_OUT_CTRL2, BIT(7)),
832
+		 AXP806_CLDO3_V_CTRL, AXP806_CLDO3_V_CTRL_MASK,
833
+		 AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_CLDO3_MASK),
834
+	AXP_DESC_SW(AXP806, SW, "sw", "swin",
835
+		    AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_SW_MASK),
370836 };
371837 
372
-static const struct regulator_linear_range axp809_dcdc4_ranges[] = {
373
-	REGULATOR_LINEAR_RANGE(600000, 0x0, 0x2f, 20000),
374
-	REGULATOR_LINEAR_RANGE(1800000, 0x30, 0x38, 100000),
838
+static const struct linear_range axp809_dcdc4_ranges[] = {
839
+	REGULATOR_LINEAR_RANGE(600000,
840
+			       AXP809_DCDC4_600mV_START,
841
+			       AXP809_DCDC4_600mV_END,
842
+			       20000),
843
+	REGULATOR_LINEAR_RANGE(1800000,
844
+			       AXP809_DCDC4_1800mV_START,
845
+			       AXP809_DCDC4_1800mV_END,
846
+			       100000),
375847 };
376848 
377849 static const struct regulator_desc axp809_regulators[] = {
378850 	AXP_DESC(AXP809, DCDC1, "dcdc1", "vin1", 1600, 3400, 100,
379
-		 AXP22X_DCDC1_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL1, BIT(1)),
851
+		 AXP22X_DCDC1_V_OUT, AXP22X_DCDC1_V_OUT_MASK,
852
+		 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC1_MASK),
380853 	AXP_DESC(AXP809, DCDC2, "dcdc2", "vin2", 600, 1540, 20,
381
-		 AXP22X_DCDC2_V_OUT, 0x3f, AXP22X_PWR_OUT_CTRL1, BIT(2)),
854
+		 AXP22X_DCDC2_V_OUT, AXP22X_DCDC2_V_OUT_MASK,
855
+		 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC2_MASK),
382856 	AXP_DESC(AXP809, DCDC3, "dcdc3", "vin3", 600, 1860, 20,
383
-		 AXP22X_DCDC3_V_OUT, 0x3f, AXP22X_PWR_OUT_CTRL1, BIT(3)),
384
-	AXP_DESC_RANGES(AXP809, DCDC4, "dcdc4", "vin4", axp809_dcdc4_ranges,
385
-			57, AXP22X_DCDC4_V_OUT, 0x3f, AXP22X_PWR_OUT_CTRL1,
386
-			BIT(4)),
857
+		 AXP22X_DCDC3_V_OUT, AXP22X_DCDC3_V_OUT_MASK,
858
+		 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC3_MASK),
859
+	AXP_DESC_RANGES(AXP809, DCDC4, "dcdc4", "vin4",
860
+			axp809_dcdc4_ranges, AXP809_DCDC4_NUM_VOLTAGES,
861
+			AXP22X_DCDC4_V_OUT, AXP22X_DCDC4_V_OUT_MASK,
862
+			AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC4_MASK),
387863 	AXP_DESC(AXP809, DCDC5, "dcdc5", "vin5", 1000, 2550, 50,
388
-		 AXP22X_DCDC5_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL1, BIT(5)),
864
+		 AXP22X_DCDC5_V_OUT, AXP22X_DCDC5_V_OUT_MASK,
865
+		 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC5_MASK),
389866 	/* secondary switchable output of DCDC1 */
390
-	AXP_DESC_SW(AXP809, DC1SW, "dc1sw", NULL, AXP22X_PWR_OUT_CTRL2,
391
-		    BIT(7)),
867
+	AXP_DESC_SW(AXP809, DC1SW, "dc1sw", NULL,
868
+		    AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DC1SW_MASK),
392869 	/* LDO regulator internally chained to DCDC5 */
393870 	AXP_DESC(AXP809, DC5LDO, "dc5ldo", NULL, 700, 1400, 100,
394
-		 AXP22X_DC5LDO_V_OUT, 0x7, AXP22X_PWR_OUT_CTRL1, BIT(0)),
871
+		 AXP22X_DC5LDO_V_OUT, AXP22X_DC5LDO_V_OUT_MASK,
872
+		 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DC5LDO_MASK),
395873 	AXP_DESC(AXP809, ALDO1, "aldo1", "aldoin", 700, 3300, 100,
396
-		 AXP22X_ALDO1_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL1, BIT(6)),
874
+		 AXP22X_ALDO1_V_OUT, AXP22X_ALDO1_V_OUT_MASK,
875
+		 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_ALDO1_MASK),
397876 	AXP_DESC(AXP809, ALDO2, "aldo2", "aldoin", 700, 3300, 100,
398
-		 AXP22X_ALDO2_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL1, BIT(7)),
877
+		 AXP22X_ALDO2_V_OUT, AXP22X_ALDO2_V_OUT_MASK,
878
+		 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_ALDO2_MASK),
399879 	AXP_DESC(AXP809, ALDO3, "aldo3", "aldoin", 700, 3300, 100,
400
-		 AXP22X_ALDO3_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(5)),
401
-	AXP_DESC_RANGES(AXP809, DLDO1, "dldo1", "dldoin", axp803_dldo2_ranges,
402
-			32, AXP22X_DLDO1_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2,
403
-			BIT(3)),
880
+		 AXP22X_ALDO3_V_OUT, AXP22X_ALDO3_V_OUT_MASK,
881
+		 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ALDO3_MASK),
882
+	AXP_DESC_RANGES(AXP809, DLDO1, "dldo1", "dldoin",
883
+			axp803_dldo2_ranges, AXP803_DLDO2_NUM_VOLTAGES,
884
+			AXP22X_DLDO1_V_OUT, AXP22X_DLDO1_V_OUT_MASK,
885
+			AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO1_MASK),
404886 	AXP_DESC(AXP809, DLDO2, "dldo2", "dldoin", 700, 3300, 100,
405
-		 AXP22X_DLDO2_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(4)),
887
+		 AXP22X_DLDO2_V_OUT, AXP22X_DLDO2_V_OUT_MASK,
888
+		 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO2_MASK),
406889 	AXP_DESC(AXP809, ELDO1, "eldo1", "eldoin", 700, 3300, 100,
407
-		 AXP22X_ELDO1_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(0)),
890
+		 AXP22X_ELDO1_V_OUT, AXP22X_ELDO1_V_OUT_MASK,
891
+		 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO1_MASK),
408892 	AXP_DESC(AXP809, ELDO2, "eldo2", "eldoin", 700, 3300, 100,
409
-		 AXP22X_ELDO2_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(1)),
893
+		 AXP22X_ELDO2_V_OUT, AXP22X_ELDO2_V_OUT_MASK,
894
+		 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO2_MASK),
410895 	AXP_DESC(AXP809, ELDO3, "eldo3", "eldoin", 700, 3300, 100,
411
-		 AXP22X_ELDO3_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(2)),
896
+		 AXP22X_ELDO3_V_OUT, AXP22X_ELDO3_V_OUT_MASK,
897
+		 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO3_MASK),
412898 	/*
413899 	 * Note the datasheet only guarantees reliable operation up to
414900 	 * 3.3V, this needs to be enforced via dts provided constraints
415901 	 */
416902 	AXP_DESC_IO(AXP809, LDO_IO0, "ldo_io0", "ips", 700, 3800, 100,
417
-		    AXP22X_LDO_IO0_V_OUT, 0x1f, AXP20X_GPIO0_CTRL, 0x07,
903
+		    AXP22X_LDO_IO0_V_OUT, AXP22X_LDO_IO0_V_OUT_MASK,
904
+		    AXP20X_GPIO0_CTRL, AXP20X_GPIO0_FUNC_MASK,
418905 		    AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
419906 	/*
420907 	 * Note the datasheet only guarantees reliable operation up to
421908 	 * 3.3V, this needs to be enforced via dts provided constraints
422909 	 */
423910 	AXP_DESC_IO(AXP809, LDO_IO1, "ldo_io1", "ips", 700, 3800, 100,
424
-		    AXP22X_LDO_IO1_V_OUT, 0x1f, AXP20X_GPIO1_CTRL, 0x07,
911
+		    AXP22X_LDO_IO1_V_OUT, AXP22X_LDO_IO1_V_OUT_MASK,
912
+		    AXP20X_GPIO1_CTRL, AXP20X_GPIO1_FUNC_MASK,
425913 		    AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
426914 	AXP_DESC_FIXED(AXP809, RTC_LDO, "rtc_ldo", "ips", 1800),
427
-	AXP_DESC_SW(AXP809, SW, "sw", "swin", AXP22X_PWR_OUT_CTRL2, BIT(6)),
915
+	AXP_DESC_SW(AXP809, SW, "sw", "swin",
916
+		    AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_SW_MASK),
428917 };
429918 
430919 static const struct regulator_desc axp813_regulators[] = {
431920 	AXP_DESC(AXP813, DCDC1, "dcdc1", "vin1", 1600, 3400, 100,
432
-		 AXP803_DCDC1_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL1, BIT(0)),
433
-	AXP_DESC_RANGES(AXP813, DCDC2, "dcdc2", "vin2", axp803_dcdc234_ranges,
434
-			76, AXP803_DCDC2_V_OUT, 0x7f, AXP22X_PWR_OUT_CTRL1,
435
-			BIT(1)),
436
-	AXP_DESC_RANGES(AXP813, DCDC3, "dcdc3", "vin3", axp803_dcdc234_ranges,
437
-			76, AXP803_DCDC3_V_OUT, 0x7f, AXP22X_PWR_OUT_CTRL1,
438
-			BIT(2)),
439
-	AXP_DESC_RANGES(AXP813, DCDC4, "dcdc4", "vin4", axp803_dcdc234_ranges,
440
-			76, AXP803_DCDC4_V_OUT, 0x7f, AXP22X_PWR_OUT_CTRL1,
441
-			BIT(3)),
442
-	AXP_DESC_RANGES(AXP813, DCDC5, "dcdc5", "vin5", axp803_dcdc5_ranges,
443
-			68, AXP803_DCDC5_V_OUT, 0x7f, AXP22X_PWR_OUT_CTRL1,
444
-			BIT(4)),
445
-	AXP_DESC_RANGES(AXP813, DCDC6, "dcdc6", "vin6", axp803_dcdc6_ranges,
446
-			72, AXP803_DCDC6_V_OUT, 0x7f, AXP22X_PWR_OUT_CTRL1,
447
-			BIT(5)),
448
-	AXP_DESC_RANGES(AXP813, DCDC7, "dcdc7", "vin7", axp803_dcdc6_ranges,
449
-			72, AXP813_DCDC7_V_OUT, 0x7f, AXP22X_PWR_OUT_CTRL1,
450
-			BIT(6)),
921
+		 AXP803_DCDC1_V_OUT, AXP803_DCDC1_V_OUT_MASK,
922
+		 AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC1_MASK),
923
+	AXP_DESC_RANGES(AXP813, DCDC2, "dcdc2", "vin2",
924
+			axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES,
925
+			AXP803_DCDC2_V_OUT, AXP803_DCDC2_V_OUT_MASK,
926
+			AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC2_MASK),
927
+	AXP_DESC_RANGES(AXP813, DCDC3, "dcdc3", "vin3",
928
+			axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES,
929
+			AXP803_DCDC3_V_OUT, AXP803_DCDC3_V_OUT_MASK,
930
+			AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC3_MASK),
931
+	AXP_DESC_RANGES(AXP813, DCDC4, "dcdc4", "vin4",
932
+			axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES,
933
+			AXP803_DCDC4_V_OUT, AXP803_DCDC4_V_OUT_MASK,
934
+			AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC4_MASK),
935
+	AXP_DESC_RANGES(AXP813, DCDC5, "dcdc5", "vin5",
936
+			axp803_dcdc5_ranges, AXP803_DCDC5_NUM_VOLTAGES,
937
+			AXP803_DCDC5_V_OUT, AXP803_DCDC5_V_OUT_MASK,
938
+			AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC5_MASK),
939
+	AXP_DESC_RANGES(AXP813, DCDC6, "dcdc6", "vin6",
940
+			axp803_dcdc6_ranges, AXP803_DCDC6_NUM_VOLTAGES,
941
+			AXP803_DCDC6_V_OUT, AXP803_DCDC6_V_OUT_MASK,
942
+			AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC6_MASK),
943
+	AXP_DESC_RANGES(AXP813, DCDC7, "dcdc7", "vin7",
944
+			axp803_dcdc6_ranges, AXP803_DCDC6_NUM_VOLTAGES,
945
+			AXP813_DCDC7_V_OUT, AXP813_DCDC7_V_OUT_MASK,
946
+			AXP22X_PWR_OUT_CTRL1, AXP813_PWR_OUT_DCDC7_MASK),
451947 	AXP_DESC(AXP813, ALDO1, "aldo1", "aldoin", 700, 3300, 100,
452
-		 AXP22X_ALDO1_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL3, BIT(5)),
948
+		 AXP22X_ALDO1_V_OUT, AXP22X_ALDO1_V_OUT_MASK,
949
+		 AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO1_MASK),
453950 	AXP_DESC(AXP813, ALDO2, "aldo2", "aldoin", 700, 3300, 100,
454
-		 AXP22X_ALDO2_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL3, BIT(6)),
951
+		 AXP22X_ALDO2_V_OUT, AXP22X_ALDO2_V_OUT_MASK,
952
+		 AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO2_MASK),
455953 	AXP_DESC(AXP813, ALDO3, "aldo3", "aldoin", 700, 3300, 100,
456
-		 AXP22X_ALDO3_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL3, BIT(7)),
954
+		 AXP22X_ALDO3_V_OUT, AXP22X_ALDO3_V_OUT_MASK,
955
+		 AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO3_MASK),
457956 	AXP_DESC(AXP813, DLDO1, "dldo1", "dldoin", 700, 3300, 100,
458
-		 AXP22X_DLDO1_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(3)),
459
-	AXP_DESC_RANGES(AXP813, DLDO2, "dldo2", "dldoin", axp803_dldo2_ranges,
460
-			32, AXP22X_DLDO2_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2,
461
-			BIT(4)),
957
+		 AXP22X_DLDO1_V_OUT, AXP22X_DLDO1_V_OUT_MASK,
958
+		 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO1_MASK),
959
+	AXP_DESC_RANGES(AXP813, DLDO2, "dldo2", "dldoin",
960
+			axp803_dldo2_ranges, AXP803_DLDO2_NUM_VOLTAGES,
961
+			AXP22X_DLDO2_V_OUT, AXP22X_DLDO2_V_OUT_MASK,
962
+			AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO2_MASK),
462963 	AXP_DESC(AXP813, DLDO3, "dldo3", "dldoin", 700, 3300, 100,
463
-		 AXP22X_DLDO3_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(5)),
964
+		 AXP22X_DLDO3_V_OUT, AXP22X_DLDO3_V_OUT_MASK,
965
+		 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO3_MASK),
464966 	AXP_DESC(AXP813, DLDO4, "dldo4", "dldoin", 700, 3300, 100,
465
-		 AXP22X_DLDO4_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(6)),
967
+		 AXP22X_DLDO4_V_OUT, AXP22X_DLDO4_V_OUT_MASK,
968
+		 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO4_MASK),
466969 	AXP_DESC(AXP813, ELDO1, "eldo1", "eldoin", 700, 1900, 50,
467
-		 AXP22X_ELDO1_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(0)),
970
+		 AXP22X_ELDO1_V_OUT, AXP22X_ELDO1_V_OUT_MASK,
971
+		 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO1_MASK),
468972 	AXP_DESC(AXP813, ELDO2, "eldo2", "eldoin", 700, 1900, 50,
469
-		 AXP22X_ELDO2_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(1)),
973
+		 AXP22X_ELDO2_V_OUT, AXP22X_ELDO2_V_OUT_MASK,
974
+		 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO2_MASK),
470975 	AXP_DESC(AXP813, ELDO3, "eldo3", "eldoin", 700, 1900, 50,
471
-		 AXP22X_ELDO3_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(2)),
976
+		 AXP22X_ELDO3_V_OUT, AXP22X_ELDO3_V_OUT_MASK,
977
+		 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO3_MASK),
472978 	/* to do / check ... */
473979 	AXP_DESC(AXP813, FLDO1, "fldo1", "fldoin", 700, 1450, 50,
474
-		 AXP803_FLDO1_V_OUT, 0x0f, AXP22X_PWR_OUT_CTRL3, BIT(2)),
980
+		 AXP803_FLDO1_V_OUT, AXP803_FLDO1_V_OUT_MASK,
981
+		 AXP22X_PWR_OUT_CTRL3, AXP803_PWR_OUT_FLDO1_MASK),
475982 	AXP_DESC(AXP813, FLDO2, "fldo2", "fldoin", 700, 1450, 50,
476
-		 AXP803_FLDO2_V_OUT, 0x0f, AXP22X_PWR_OUT_CTRL3, BIT(3)),
983
+		 AXP803_FLDO2_V_OUT, AXP803_FLDO2_V_OUT_MASK,
984
+		 AXP22X_PWR_OUT_CTRL3, AXP803_PWR_OUT_FLDO2_MASK),
477985 	/*
478986 	 * TODO: FLDO3 = {DCDC5, FLDOIN} / 2
479987 	 *
....@@ -482,12 +990,15 @@
482990 	 */
483991 	AXP_DESC_FIXED(AXP813, RTC_LDO, "rtc-ldo", "ips", 1800),
484992 	AXP_DESC_IO(AXP813, LDO_IO0, "ldo-io0", "ips", 700, 3300, 100,
485
-		    AXP22X_LDO_IO0_V_OUT, 0x1f, AXP20X_GPIO0_CTRL, 0x07,
993
+		    AXP22X_LDO_IO0_V_OUT, AXP22X_LDO_IO0_V_OUT_MASK,
994
+		    AXP20X_GPIO0_CTRL, AXP20X_GPIO0_FUNC_MASK,
486995 		    AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
487996 	AXP_DESC_IO(AXP813, LDO_IO1, "ldo-io1", "ips", 700, 3300, 100,
488
-		    AXP22X_LDO_IO1_V_OUT, 0x1f, AXP20X_GPIO1_CTRL, 0x07,
997
+		    AXP22X_LDO_IO1_V_OUT, AXP22X_LDO_IO1_V_OUT_MASK,
998
+		    AXP20X_GPIO1_CTRL, AXP20X_GPIO1_FUNC_MASK,
489999 		    AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
490
-	AXP_DESC_SW(AXP813, SW, "sw", "swin", AXP22X_PWR_OUT_CTRL2, BIT(7)),
1000
+	AXP_DESC_SW(AXP813, SW, "sw", "swin",
1001
+		    AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DC1SW_MASK),
4911002 };
4921003 
4931004 static int axp20x_set_dcdc_freq(struct platform_device *pdev, u32 dcdcfreq)
....@@ -509,10 +1020,10 @@
5091020 		/*
5101021 		 * AXP803/AXP813 DCDC work frequency setting has the same
5111022 		 * range and step as AXP22X, but at a different register.
512
-		 * Fall through to the check below.
5131023 		 * (See include/linux/mfd/axp20x.h)
5141024 		 */
5151025 		reg = AXP803_DCDC_FREQ_CTRL;
1026
+		fallthrough;	/* to the check below */
5161027 	case AXP806_ID:
5171028 		/*
5181029 		 * AXP806 also have DCDC work frequency setting register at a
....@@ -520,6 +1031,7 @@
5201031 		 */
5211032 		if (axp20x->variant == AXP806_ID)
5221033 			reg = AXP806_DCDC_FREQ_CTRL;
1034
+		fallthrough;
5231035 	case AXP221_ID:
5241036 	case AXP223_ID:
5251037 	case AXP809_ID:
....@@ -601,12 +1113,12 @@
6011113 		break;
6021114 
6031115 	case AXP806_ID:
604
-		reg = AXP806_DCDC_MODE_CTRL2;
6051116 		/*
6061117 		 * AXP806 DCDC regulator IDs have the same range as AXP22X.
607
-		 * Fall through to the check below.
6081118 		 * (See include/linux/mfd/axp20x.h)
6091119 		 */
1120
+		reg = AXP806_DCDC_MODE_CTRL2;
1121
+		fallthrough;	/* to the check below */
6101122 	case AXP221_ID:
6111123 	case AXP223_ID:
6121124 	case AXP809_ID:
....@@ -661,9 +1173,9 @@
6611173 
6621174 		switch (id) {
6631175 		case AXP803_DCDC3:
664
-			return !!(reg & BIT(6));
1176
+			return !!(reg & AXP803_DCDC23_POLYPHASE_DUAL);
6651177 		case AXP803_DCDC6:
666
-			return !!(reg & BIT(5));
1178
+			return !!(reg & AXP803_DCDC56_POLYPHASE_DUAL);
6671179 		}
6681180 		break;
6691181 
....@@ -672,12 +1184,15 @@
6721184 
6731185 		switch (id) {
6741186 		case AXP806_DCDCB:
675
-			return (((reg & GENMASK(7, 6)) == BIT(6)) ||
676
-				((reg & GENMASK(7, 6)) == BIT(7)));
1187
+			return (((reg & AXP806_DCDCABC_POLYPHASE_MASK) ==
1188
+				AXP806_DCDCAB_POLYPHASE_DUAL) ||
1189
+				((reg & AXP806_DCDCABC_POLYPHASE_MASK) ==
1190
+				AXP806_DCDCABC_POLYPHASE_TRI));
6771191 		case AXP806_DCDCC:
678
-			return ((reg & GENMASK(7, 6)) == BIT(7));
1192
+			return ((reg & AXP806_DCDCABC_POLYPHASE_MASK) ==
1193
+				AXP806_DCDCABC_POLYPHASE_TRI);
6791194 		case AXP806_DCDCE:
680
-			return !!(reg & BIT(5));
1195
+			return !!(reg & AXP806_DCDCDE_POLYPHASE_DUAL);
6811196 		}
6821197 		break;
6831198