.. | .. |
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41 | 41 | #define DP83867_STRAP_STS1 0x006E |
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42 | 42 | #define DP83867_STRAP_STS2 0x006f |
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43 | 43 | #define DP83867_RGMIIDCTL 0x0086 |
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| 44 | +#define DP83867_DSP_FFE_CFG 0x012c |
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44 | 45 | #define DP83867_RXFCFG 0x0134 |
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45 | 46 | #define DP83867_RXFPMD1 0x0136 |
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46 | 47 | #define DP83867_RXFPMD2 0x0137 |
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.. | .. |
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801 | 802 | { |
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802 | 803 | int err; |
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803 | 804 | |
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| 805 | + err = phy_write(phydev, DP83867_CTRL, DP83867_SW_RESET); |
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| 806 | + if (err < 0) |
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| 807 | + return err; |
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| 808 | + |
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| 809 | + usleep_range(10, 20); |
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| 810 | + |
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| 811 | + err = phy_modify(phydev, MII_DP83867_PHYCTRL, |
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| 812 | + DP83867_PHYCR_FORCE_LINK_GOOD, 0); |
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| 813 | + if (err < 0) |
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| 814 | + return err; |
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| 815 | + |
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| 816 | + /* Configure the DSP Feedforward Equalizer Configuration register to |
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| 817 | + * improve short cable (< 1 meter) performance. This will not affect |
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| 818 | + * long cable performance. |
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| 819 | + */ |
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| 820 | + err = phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_DSP_FFE_CFG, |
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| 821 | + 0x0e81); |
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| 822 | + if (err < 0) |
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| 823 | + return err; |
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| 824 | + |
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804 | 825 | err = phy_write(phydev, DP83867_CTRL, DP83867_SW_RESTART); |
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805 | 826 | if (err < 0) |
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806 | 827 | return err; |
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807 | 828 | |
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808 | 829 | usleep_range(10, 20); |
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809 | 830 | |
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810 | | - return phy_modify(phydev, MII_DP83867_PHYCTRL, |
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811 | | - DP83867_PHYCR_FORCE_LINK_GOOD, 0); |
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| 831 | + return 0; |
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812 | 832 | } |
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813 | 833 | |
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814 | 834 | static void dp83867_link_change_notify(struct phy_device *phydev) |
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