add gpio led uart

hc

2024-05-10 748e4f3d702def1a4bff191e0cf93b6a05340f01

 kernel/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
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@@ -1,17 +1,10 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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  * Copyright (c) 2016 Maxime Ripard. All rights reserved.
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- *
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- * This software is licensed under the terms of the GNU General Public
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- * License version 2, as published by the Free Software Foundation, and
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- * may be copied, distributed, and modified under those terms.
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- *
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- * This program is distributed in the hope that it will be useful,
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- * but WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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- * GNU General Public License for more details.
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  */
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5
 
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 #include <linux/clk-provider.h>
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+#include <linux/io.h>
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 #include <linux/of_address.h>
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9
 
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 #include "ccu_common.h"
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@@ -69,18 +62,19 @@
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 				       BIT(28),	/* lock */
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 				       CLK_SET_RATE_UNGATE);
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64
 
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-static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN(pll_video_clk, "pll-video",
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-					    "osc24M", 0x0010,
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-					    192000000,	/* Minimum rate */
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-					    8, 7,	/* N */
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-					    0, 4,	/* M */
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-					    BIT(24),	/* frac enable */
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-					    BIT(25),	/* frac select */
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-					    270000000,	/* frac rate 0 */
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-					    297000000,	/* frac rate 1 */
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-					    BIT(31),	/* gate */
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-					    BIT(28),	/* lock */
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-					    CLK_SET_RATE_UNGATE);
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+static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(pll_video_clk, "pll-video",
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+						"osc24M", 0x0010,
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+						192000000, /* Minimum rate */
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+						912000000, /* Maximum rate */
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+						8, 7,      /* N */
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+						0, 4,	   /* M */
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+						BIT(24),   /* frac enable */
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+						BIT(25),   /* frac select */
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+						270000000, /* frac rate 0 */
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+						297000000, /* frac rate 1 */
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+						BIT(31),   /* gate */
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+						BIT(28),   /* lock */
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+						CLK_SET_RATE_UNGATE);
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 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
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 					"osc24M", 0x0018,
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@@ -481,7 +475,7 @@
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 				 0x134, 0, 5, 8, 3, BIT(15), 0);
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476
 
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 static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",
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-			     0x13c, 16, 3, BIT(31), 0);
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+			     0x13c, 16, 3, BIT(31), CLK_SET_RATE_PARENT);
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 static SUNXI_CCU_GATE(ac_dig_clk,	"ac-dig",	"pll-audio",
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 		      0x140, BIT(31), CLK_SET_RATE_PARENT);
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@@ -724,17 +718,26 @@
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 	&gpu_clk.common,
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 };
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+static const struct clk_hw *clk_parent_pll_audio[] = {
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+	&pll_audio_base_clk.common.hw
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+};
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+
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 /* We hardcode the divider to 1 for now */
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-static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio",
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-			"pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);
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-static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x",
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-			"pll-audio-base", 2, 1, CLK_SET_RATE_PARENT);
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-static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x",
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-			"pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);
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-static CLK_FIXED_FACTOR(pll_audio_8x_clk, "pll-audio-8x",
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-			"pll-audio-base", 1, 2, CLK_SET_RATE_PARENT);
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-static CLK_FIXED_FACTOR(pll_periph0_2x_clk, "pll-periph0-2x",
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-			"pll-periph0", 1, 2, 0);
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+static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
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+			    clk_parent_pll_audio,
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+			    1, 1, CLK_SET_RATE_PARENT);
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+static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
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+			    clk_parent_pll_audio,
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+			    2, 1, CLK_SET_RATE_PARENT);
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+static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",
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+			    clk_parent_pll_audio,
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+			    1, 1, CLK_SET_RATE_PARENT);
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+static CLK_FIXED_FACTOR_HWS(pll_audio_8x_clk, "pll-audio-8x",
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+			    clk_parent_pll_audio,
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+			    1, 2, CLK_SET_RATE_PARENT);
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+static CLK_FIXED_FACTOR_HW(pll_periph0_2x_clk, "pll-periph0-2x",
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+			   &pll_periph0_clk.common.hw,
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+			   1, 2, 0);
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 static struct clk_hw_onecell_data sun8i_h3_hw_clks = {
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 	.hws	= {