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| 1 | +/* SPDX-License-Identifier: GPL-2.0-or-later */ |
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1 | 2 | /* |
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2 | 3 | * Copyright 2016 Maxime Ripard |
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3 | 4 | * |
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4 | 5 | * Maxime Ripard <maxime.ripard@free-electrons.com> |
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5 | | - * |
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6 | | - * This program is free software; you can redistribute it and/or modify |
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7 | | - * it under the terms of the GNU General Public License as published by |
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8 | | - * the Free Software Foundation; either version 2 of the License, or |
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9 | | - * (at your option) any later version. |
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10 | | - * |
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11 | | - * This program is distributed in the hope that it will be useful, |
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12 | | - * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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13 | | - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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14 | | - * GNU General Public License for more details. |
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15 | 6 | */ |
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16 | 7 | |
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17 | 8 | #ifndef _CCU_SUN50I_A64_H_ |
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.. | .. |
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27 | 18 | #define CLK_PLL_AUDIO_2X 4 |
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28 | 19 | #define CLK_PLL_AUDIO_4X 5 |
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29 | 20 | #define CLK_PLL_AUDIO_8X 6 |
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30 | | -#define CLK_PLL_VIDEO0 7 |
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| 21 | + |
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| 22 | +/* PLL_VIDEO0 exported for HDMI PHY */ |
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| 23 | + |
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31 | 24 | #define CLK_PLL_VIDEO0_2X 8 |
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32 | 25 | #define CLK_PLL_VE 9 |
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33 | 26 | #define CLK_PLL_DDR0 10 |
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.. | .. |
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43 | 36 | #define CLK_PLL_HSIC 18 |
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44 | 37 | #define CLK_PLL_DE 19 |
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45 | 38 | #define CLK_PLL_DDR1 20 |
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46 | | -#define CLK_CPUX 21 |
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47 | 39 | #define CLK_AXI 22 |
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48 | 40 | #define CLK_APB 23 |
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49 | 41 | #define CLK_AHB1 24 |
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.. | .. |
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62 | 54 | #define CLK_DRAM 94 |
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63 | 55 | |
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64 | 56 | /* All the DRAM gates are exported */ |
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65 | | - |
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66 | | -/* Some more module clocks are exported */ |
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67 | | - |
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68 | | -#define CLK_MBUS 112 |
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69 | 57 | |
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70 | 58 | /* And the DSI and GPU module clock is exported */ |
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71 | 59 | |
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