add gpio led uart

hc

2024-05-10 748e4f3d702def1a4bff191e0cf93b6a05340f01

 kernel/drivers/clk/actions/owl-pll.h
..
..
@@ -1,4 +1,4 @@
1
-// SPDX-License-Identifier: GPL-2.0+
1
+/* SPDX-License-Identifier: GPL-2.0+ */
2
2
 //
3
3
 // OWL pll clock driver
4
4
 //
..
..
@@ -12,6 +12,8 @@
12
12
 #define _OWL_PLL_H_
13
13
 
14
14
 #include "owl-common.h"
15
+
16
+#define OWL_PLL_DEF_DELAY	50
15
17
 
16
18
 /* last entry should have rate = 0 */
17
19
 struct clk_pll_table {
..
..
@@ -27,6 +29,7 @@
27
29
 	u8			width;
28
30
 	u8			min_mul;
29
31
 	u8			max_mul;
32
+	u8			delay;
30
33
 	const struct clk_pll_table *table;
31
34
 };
32
35
 
..
..
@@ -36,7 +39,7 @@
36
39
 };
37
40
 
38
41
 #define OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift,			\
39
-		   _width, _min_mul, _max_mul, _table)			\
42
+		   _width, _min_mul, _max_mul, _delay, _table)		\
40
43
 	{								\
41
44
 		.reg		= _reg,					\
42
45
 		.bfreq		= _bfreq,				\
..
..
@@ -45,6 +48,7 @@
45
48
 		.width		= _width,				\
46
49
 		.min_mul	= _min_mul,				\
47
50
 		.max_mul	= _max_mul,				\
51
+		.delay		= _delay,				\
48
52
 		.table		= _table,				\
49
53
 	}
50
54
 
..
..
@@ -52,8 +56,8 @@
52
56
 		_shift, _width, _min_mul, _max_mul, _table, _flags)	\
53
57
 	struct owl_pll _struct = {					\
54
58
 		.pll_hw	= OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift,	\
55
-				     _width, _min_mul,			\
56
-				     _max_mul, _table),			\
59
+				     _width, _min_mul, _max_mul,	\
60
+				     OWL_PLL_DEF_DELAY,	_table),	\
57
61
 		.common = {						\
58
62
 			.regmap = NULL,					\
59
63
 			.hw.init = CLK_HW_INIT(_name,			\
..
..
@@ -67,8 +71,23 @@
67
71
 		_shift, _width, _min_mul, _max_mul, _table, _flags)	\
68
72
 	struct owl_pll _struct = {					\
69
73
 		.pll_hw	= OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift,	\
70
-				     _width, _min_mul,			\
71
-				     _max_mul, _table),			\
74
+				     _width, _min_mul, _max_mul,	\
75
+				     OWL_PLL_DEF_DELAY,	_table),	\
76
+		.common = {						\
77
+			.regmap = NULL,					\
78
+			.hw.init = CLK_HW_INIT_NO_PARENT(_name,		\
79
+					       &owl_pll_ops,		\
80
+					       _flags),			\
81
+		},							\
82
+	}
83
+
84
+#define OWL_PLL_NO_PARENT_DELAY(_struct, _name, _reg, _bfreq, _bit_idx,	\
85
+		_shift, _width, _min_mul, _max_mul, _delay, _table,	\
86
+		_flags)							\
87
+	struct owl_pll _struct = {					\
88
+		.pll_hw	= OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift,	\
89
+				     _width, _min_mul,  _max_mul,	\
90
+				     _delay, _table),			\
72
91
 		.common = {						\
73
92
 			.regmap = NULL,					\
74
93
 			.hw.init = CLK_HW_INIT_NO_PARENT(_name,		\
..
..
@@ -78,7 +97,6 @@
78
97
 	}
79
98
 
80
99
 #define mul_mask(m)		((1 << ((m)->width)) - 1)
81
-#define PLL_STABILITY_WAIT_US	(50)
82
100
 
83
101
 static inline struct owl_pll *hw_to_owl_pll(const struct clk_hw *hw)
84
102
 {