.. | .. |
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13 | 13 | #ifndef _XTENSA_BITOPS_H |
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14 | 14 | #define _XTENSA_BITOPS_H |
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15 | 15 | |
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16 | | -#ifdef __KERNEL__ |
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17 | | - |
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18 | 16 | #ifndef _LINUX_BITOPS_H |
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19 | 17 | #error only <linux/bitops.h> can be included directly |
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20 | 18 | #endif |
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.. | .. |
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98 | 96 | |
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99 | 97 | #include <asm-generic/bitops/fls64.h> |
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100 | 98 | |
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101 | | -#if XCHAL_HAVE_S32C1I |
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| 99 | +#if XCHAL_HAVE_EXCLUSIVE |
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102 | 100 | |
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103 | | -static inline void set_bit(unsigned int bit, volatile unsigned long *p) |
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104 | | -{ |
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105 | | - unsigned long tmp, value; |
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106 | | - unsigned long mask = 1UL << (bit & 31); |
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107 | | - |
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108 | | - p += bit >> 5; |
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109 | | - |
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110 | | - __asm__ __volatile__( |
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111 | | - "1: l32i %1, %3, 0\n" |
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112 | | - " wsr %1, scompare1\n" |
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113 | | - " or %0, %1, %2\n" |
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114 | | - " s32c1i %0, %3, 0\n" |
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115 | | - " bne %0, %1, 1b\n" |
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116 | | - : "=&a" (tmp), "=&a" (value) |
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117 | | - : "a" (mask), "a" (p) |
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118 | | - : "memory"); |
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| 101 | +#define BIT_OP(op, insn, inv) \ |
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| 102 | +static inline void op##_bit(unsigned int bit, volatile unsigned long *p)\ |
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| 103 | +{ \ |
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| 104 | + unsigned long tmp; \ |
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| 105 | + unsigned long mask = 1UL << (bit & 31); \ |
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| 106 | + \ |
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| 107 | + p += bit >> 5; \ |
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| 108 | + \ |
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| 109 | + __asm__ __volatile__( \ |
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| 110 | + "1: l32ex %[tmp], %[addr]\n" \ |
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| 111 | + " "insn" %[tmp], %[tmp], %[mask]\n" \ |
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| 112 | + " s32ex %[tmp], %[addr]\n" \ |
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| 113 | + " getex %[tmp]\n" \ |
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| 114 | + " beqz %[tmp], 1b\n" \ |
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| 115 | + : [tmp] "=&a" (tmp) \ |
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| 116 | + : [mask] "a" (inv mask), [addr] "a" (p) \ |
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| 117 | + : "memory"); \ |
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119 | 118 | } |
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120 | 119 | |
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121 | | -static inline void clear_bit(unsigned int bit, volatile unsigned long *p) |
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122 | | -{ |
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123 | | - unsigned long tmp, value; |
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124 | | - unsigned long mask = 1UL << (bit & 31); |
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125 | | - |
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126 | | - p += bit >> 5; |
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127 | | - |
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128 | | - __asm__ __volatile__( |
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129 | | - "1: l32i %1, %3, 0\n" |
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130 | | - " wsr %1, scompare1\n" |
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131 | | - " and %0, %1, %2\n" |
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132 | | - " s32c1i %0, %3, 0\n" |
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133 | | - " bne %0, %1, 1b\n" |
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134 | | - : "=&a" (tmp), "=&a" (value) |
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135 | | - : "a" (~mask), "a" (p) |
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136 | | - : "memory"); |
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| 120 | +#define TEST_AND_BIT_OP(op, insn, inv) \ |
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| 121 | +static inline int \ |
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| 122 | +test_and_##op##_bit(unsigned int bit, volatile unsigned long *p) \ |
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| 123 | +{ \ |
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| 124 | + unsigned long tmp, value; \ |
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| 125 | + unsigned long mask = 1UL << (bit & 31); \ |
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| 126 | + \ |
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| 127 | + p += bit >> 5; \ |
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| 128 | + \ |
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| 129 | + __asm__ __volatile__( \ |
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| 130 | + "1: l32ex %[value], %[addr]\n" \ |
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| 131 | + " "insn" %[tmp], %[value], %[mask]\n" \ |
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| 132 | + " s32ex %[tmp], %[addr]\n" \ |
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| 133 | + " getex %[tmp]\n" \ |
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| 134 | + " beqz %[tmp], 1b\n" \ |
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| 135 | + : [tmp] "=&a" (tmp), [value] "=&a" (value) \ |
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| 136 | + : [mask] "a" (inv mask), [addr] "a" (p) \ |
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| 137 | + : "memory"); \ |
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| 138 | + \ |
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| 139 | + return value & mask; \ |
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137 | 140 | } |
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138 | 141 | |
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139 | | -static inline void change_bit(unsigned int bit, volatile unsigned long *p) |
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140 | | -{ |
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141 | | - unsigned long tmp, value; |
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142 | | - unsigned long mask = 1UL << (bit & 31); |
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| 142 | +#elif XCHAL_HAVE_S32C1I |
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143 | 143 | |
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144 | | - p += bit >> 5; |
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145 | | - |
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146 | | - __asm__ __volatile__( |
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147 | | - "1: l32i %1, %3, 0\n" |
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148 | | - " wsr %1, scompare1\n" |
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149 | | - " xor %0, %1, %2\n" |
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150 | | - " s32c1i %0, %3, 0\n" |
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151 | | - " bne %0, %1, 1b\n" |
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152 | | - : "=&a" (tmp), "=&a" (value) |
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153 | | - : "a" (mask), "a" (p) |
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154 | | - : "memory"); |
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| 144 | +#define BIT_OP(op, insn, inv) \ |
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| 145 | +static inline void op##_bit(unsigned int bit, volatile unsigned long *p)\ |
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| 146 | +{ \ |
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| 147 | + unsigned long tmp, value; \ |
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| 148 | + unsigned long mask = 1UL << (bit & 31); \ |
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| 149 | + \ |
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| 150 | + p += bit >> 5; \ |
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| 151 | + \ |
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| 152 | + __asm__ __volatile__( \ |
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| 153 | + "1: l32i %[value], %[mem]\n" \ |
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| 154 | + " wsr %[value], scompare1\n" \ |
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| 155 | + " "insn" %[tmp], %[value], %[mask]\n" \ |
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| 156 | + " s32c1i %[tmp], %[mem]\n" \ |
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| 157 | + " bne %[tmp], %[value], 1b\n" \ |
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| 158 | + : [tmp] "=&a" (tmp), [value] "=&a" (value), \ |
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| 159 | + [mem] "+m" (*p) \ |
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| 160 | + : [mask] "a" (inv mask) \ |
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| 161 | + : "memory"); \ |
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155 | 162 | } |
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156 | 163 | |
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157 | | -static inline int |
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158 | | -test_and_set_bit(unsigned int bit, volatile unsigned long *p) |
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159 | | -{ |
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160 | | - unsigned long tmp, value; |
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161 | | - unsigned long mask = 1UL << (bit & 31); |
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162 | | - |
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163 | | - p += bit >> 5; |
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164 | | - |
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165 | | - __asm__ __volatile__( |
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166 | | - "1: l32i %1, %3, 0\n" |
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167 | | - " wsr %1, scompare1\n" |
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168 | | - " or %0, %1, %2\n" |
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169 | | - " s32c1i %0, %3, 0\n" |
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170 | | - " bne %0, %1, 1b\n" |
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171 | | - : "=&a" (tmp), "=&a" (value) |
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172 | | - : "a" (mask), "a" (p) |
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173 | | - : "memory"); |
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174 | | - |
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175 | | - return tmp & mask; |
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176 | | -} |
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177 | | - |
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178 | | -static inline int |
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179 | | -test_and_clear_bit(unsigned int bit, volatile unsigned long *p) |
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180 | | -{ |
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181 | | - unsigned long tmp, value; |
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182 | | - unsigned long mask = 1UL << (bit & 31); |
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183 | | - |
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184 | | - p += bit >> 5; |
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185 | | - |
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186 | | - __asm__ __volatile__( |
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187 | | - "1: l32i %1, %3, 0\n" |
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188 | | - " wsr %1, scompare1\n" |
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189 | | - " and %0, %1, %2\n" |
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190 | | - " s32c1i %0, %3, 0\n" |
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191 | | - " bne %0, %1, 1b\n" |
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192 | | - : "=&a" (tmp), "=&a" (value) |
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193 | | - : "a" (~mask), "a" (p) |
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194 | | - : "memory"); |
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195 | | - |
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196 | | - return tmp & mask; |
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197 | | -} |
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198 | | - |
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199 | | -static inline int |
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200 | | -test_and_change_bit(unsigned int bit, volatile unsigned long *p) |
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201 | | -{ |
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202 | | - unsigned long tmp, value; |
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203 | | - unsigned long mask = 1UL << (bit & 31); |
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204 | | - |
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205 | | - p += bit >> 5; |
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206 | | - |
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207 | | - __asm__ __volatile__( |
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208 | | - "1: l32i %1, %3, 0\n" |
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209 | | - " wsr %1, scompare1\n" |
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210 | | - " xor %0, %1, %2\n" |
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211 | | - " s32c1i %0, %3, 0\n" |
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212 | | - " bne %0, %1, 1b\n" |
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213 | | - : "=&a" (tmp), "=&a" (value) |
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214 | | - : "a" (mask), "a" (p) |
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215 | | - : "memory"); |
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216 | | - |
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217 | | - return tmp & mask; |
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| 164 | +#define TEST_AND_BIT_OP(op, insn, inv) \ |
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| 165 | +static inline int \ |
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| 166 | +test_and_##op##_bit(unsigned int bit, volatile unsigned long *p) \ |
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| 167 | +{ \ |
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| 168 | + unsigned long tmp, value; \ |
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| 169 | + unsigned long mask = 1UL << (bit & 31); \ |
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| 170 | + \ |
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| 171 | + p += bit >> 5; \ |
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| 172 | + \ |
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| 173 | + __asm__ __volatile__( \ |
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| 174 | + "1: l32i %[value], %[mem]\n" \ |
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| 175 | + " wsr %[value], scompare1\n" \ |
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| 176 | + " "insn" %[tmp], %[value], %[mask]\n" \ |
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| 177 | + " s32c1i %[tmp], %[mem]\n" \ |
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| 178 | + " bne %[tmp], %[value], 1b\n" \ |
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| 179 | + : [tmp] "=&a" (tmp), [value] "=&a" (value), \ |
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| 180 | + [mem] "+m" (*p) \ |
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| 181 | + : [mask] "a" (inv mask) \ |
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| 182 | + : "memory"); \ |
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| 183 | + \ |
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| 184 | + return tmp & mask; \ |
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218 | 185 | } |
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219 | 186 | |
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220 | 187 | #else |
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221 | 188 | |
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| 189 | +#define BIT_OP(op, insn, inv) |
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| 190 | +#define TEST_AND_BIT_OP(op, insn, inv) |
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| 191 | + |
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222 | 192 | #include <asm-generic/bitops/atomic.h> |
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223 | 193 | |
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224 | 194 | #endif /* XCHAL_HAVE_S32C1I */ |
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| 195 | + |
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| 196 | +#define BIT_OPS(op, insn, inv) \ |
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| 197 | + BIT_OP(op, insn, inv) \ |
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| 198 | + TEST_AND_BIT_OP(op, insn, inv) |
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| 199 | + |
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| 200 | +BIT_OPS(set, "or", ) |
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| 201 | +BIT_OPS(clear, "and", ~) |
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| 202 | +BIT_OPS(change, "xor", ) |
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| 203 | + |
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| 204 | +#undef BIT_OPS |
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| 205 | +#undef BIT_OP |
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| 206 | +#undef TEST_AND_BIT_OP |
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225 | 207 | |
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226 | 208 | #include <asm-generic/bitops/find.h> |
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227 | 209 | #include <asm-generic/bitops/le.h> |
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.. | .. |
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231 | 213 | #include <asm-generic/bitops/hweight.h> |
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232 | 214 | #include <asm-generic/bitops/lock.h> |
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233 | 215 | #include <asm-generic/bitops/sched.h> |
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234 | | - |
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235 | | -#endif /* __KERNEL__ */ |
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236 | 216 | |
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237 | 217 | #endif /* _XTENSA_BITOPS_H */ |
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