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2024-05-10 748e4f3d702def1a4bff191e0cf93b6a05340f01

 kernel/arch/arm/mm/copypage-v4wt.c
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@@ -1,11 +1,8 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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  *  linux/arch/arm/mm/copypage-v4wt.S
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  *
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  *  Copyright (C) 1995-1999 Russell King
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 as
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- * published by the Free Software Foundation.
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  *
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  *  This is for CPUs with a writethrough cache and 'flush ID cache' is
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  *  the only supported cache operation.
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@@ -25,6 +22,7 @@
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 	int tmp;
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 	asm volatile ("\
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+	.syntax unified\n\
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 	ldmia	%1!, {r3, r4, ip, lr}		@ 4\n\
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 1:	stmia	%0!, {r3, r4, ip, lr}		@ 4\n\
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 	ldmia	%1!, {r3, r4, ip, lr}		@ 4+1\n\
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@@ -34,7 +32,7 @@
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 	ldmia	%1!, {r3, r4, ip, lr}		@ 4\n\
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 	subs	%2, %2, #1			@ 1\n\
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 	stmia	%0!, {r3, r4, ip, lr}		@ 4\n\
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-	ldmneia	%1!, {r3, r4, ip, lr}		@ 4\n\
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+	ldmiane	%1!, {r3, r4, ip, lr}		@ 4\n\
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 	bne	1b				@ 1\n\
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 	mcr	p15, 0, %2, c7, c7, 0		@ flush ID cache"
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 	: "+&r" (kto), "+&r" (kfrom), "=&r" (tmp)