forked from ~ljy/RK356X_SDK_RELEASE
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2024-05-10 748e4f3d702def1a4bff191e0cf93b6a05340f01 
 kernel/arch/arm/mach-davinci/dm646x.c
....@@ -1,5 +1,5 @@
11 /*
2
- * TI DaVinci DM644x chip specific setup
2
+ * TI DaVinci DM646x chip specific setup
33  *
44  * Author: Kevin Hilman, Deep Root Systems, LLC
55  *
....@@ -15,6 +15,8 @@
1515 #include <linux/dma-mapping.h>
1616 #include <linux/dmaengine.h>
1717 #include <linux/init.h>
18
+#include <linux/io.h>
19
+#include <linux/irqchip/irq-davinci-aintc.h>
1820 #include <linux/platform_data/edma.h>
1921 #include <linux/platform_data/gpio-davinci.h>
2022 #include <linux/platform_device.h>
....@@ -24,13 +26,14 @@
2426 
2527 #include <mach/common.h>
2628 #include <mach/cputype.h>
27
-#include <mach/irqs.h>
2829 #include <mach/mux.h>
2930 #include <mach/serial.h>
30
-#include <mach/time.h>
31
+
32
+#include <clocksource/timer-davinci.h>
3133 
3234 #include "asp.h"
3335 #include "davinci.h"
36
+#include "irqs.h"
3437 #include "mux.h"
3538 
3639 #define DAVINCI_VPIF_BASE       (0x01C12000)
....@@ -62,23 +65,23 @@
6265 		.flags	= IORESOURCE_MEM,
6366 	},
6467 	{
65
-		.start	= IRQ_DM646X_EMACRXTHINT,
66
-		.end	= IRQ_DM646X_EMACRXTHINT,
68
+		.start	= DAVINCI_INTC_IRQ(IRQ_DM646X_EMACRXTHINT),
69
+		.end	= DAVINCI_INTC_IRQ(IRQ_DM646X_EMACRXTHINT),
6770 		.flags	= IORESOURCE_IRQ,
6871 	},
6972 	{
70
-		.start	= IRQ_DM646X_EMACRXINT,
71
-		.end	= IRQ_DM646X_EMACRXINT,
73
+		.start	= DAVINCI_INTC_IRQ(IRQ_DM646X_EMACRXINT),
74
+		.end	= DAVINCI_INTC_IRQ(IRQ_DM646X_EMACRXINT),
7275 		.flags	= IORESOURCE_IRQ,
7376 	},
7477 	{
75
-		.start	= IRQ_DM646X_EMACTXINT,
76
-		.end	= IRQ_DM646X_EMACTXINT,
78
+		.start	= DAVINCI_INTC_IRQ(IRQ_DM646X_EMACTXINT),
79
+		.end	= DAVINCI_INTC_IRQ(IRQ_DM646X_EMACTXINT),
7780 		.flags	= IORESOURCE_IRQ,
7881 	},
7982 	{
80
-		.start	= IRQ_DM646X_EMACMISCINT,
81
-		.end	= IRQ_DM646X_EMACMISCINT,
83
+		.start	= DAVINCI_INTC_IRQ(IRQ_DM646X_EMACMISCINT),
84
+		.end	= DAVINCI_INTC_IRQ(IRQ_DM646X_EMACMISCINT),
8285 		.flags	= IORESOURCE_IRQ,
8386 	},
8487 };
....@@ -273,12 +276,12 @@
273276 	},
274277 	{
275278 		.name	= "edma3_ccint",
276
-		.start	= IRQ_CCINT0,
279
+		.start	= DAVINCI_INTC_IRQ(IRQ_CCINT0),
277280 		.flags	= IORESOURCE_IRQ,
278281 	},
279282 	{
280283 		.name	= "edma3_ccerrint",
281
-		.start	= IRQ_CCERRINT,
284
+		.start	= DAVINCI_INTC_IRQ(IRQ_CCERRINT),
282285 		.flags	= IORESOURCE_IRQ,
283286 	},
284287 	/* not using TC*_ERR */
....@@ -315,12 +318,12 @@
315318 	},
316319 	{
317320 		.name	= "tx",
318
-		.start	= IRQ_DM646X_MCASP0TXINT,
321
+		.start	= DAVINCI_INTC_IRQ(IRQ_DM646X_MCASP0TXINT),
319322 		.flags	= IORESOURCE_IRQ,
320323 	},
321324 	{
322325 		.name	= "rx",
323
-		.start	= IRQ_DM646X_MCASP0RXINT,
326
+		.start	= DAVINCI_INTC_IRQ(IRQ_DM646X_MCASP0RXINT),
324327 		.flags	= IORESOURCE_IRQ,
325328 	},
326329 };
....@@ -341,7 +344,7 @@
341344 	},
342345 	{
343346 		.name	= "tx",
344
-		.start	= IRQ_DM646X_MCASP1TXINT,
347
+		.start	= DAVINCI_INTC_IRQ(IRQ_DM646X_MCASP1TXINT),
345348 		.flags	= IORESOURCE_IRQ,
346349 	},
347350 };
....@@ -388,13 +391,13 @@
388391 
389392 static struct resource vpif_display_resource[] = {
390393 	{
391
-		.start = IRQ_DM646X_VP_VERTINT2,
392
-		.end   = IRQ_DM646X_VP_VERTINT2,
394
+		.start = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT2),
395
+		.end   = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT2),
393396 		.flags = IORESOURCE_IRQ,
394397 	},
395398 	{
396
-		.start = IRQ_DM646X_VP_VERTINT3,
397
-		.end   = IRQ_DM646X_VP_VERTINT3,
399
+		.start = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT3),
400
+		.end   = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT3),
398401 		.flags = IORESOURCE_IRQ,
399402 	},
400403 };
....@@ -412,13 +415,13 @@
412415 
413416 static struct resource vpif_capture_resource[] = {
414417 	{
415
-		.start = IRQ_DM646X_VP_VERTINT0,
416
-		.end   = IRQ_DM646X_VP_VERTINT0,
418
+		.start = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT0),
419
+		.end   = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT0),
417420 		.flags = IORESOURCE_IRQ,
418421 	},
419422 	{
420
-		.start = IRQ_DM646X_VP_VERTINT1,
421
-		.end   = IRQ_DM646X_VP_VERTINT1,
423
+		.start = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT1),
424
+		.end   = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT1),
422425 		.flags = IORESOURCE_IRQ,
423426 	},
424427 };
....@@ -441,23 +444,25 @@
441444 		.flags	= IORESOURCE_MEM,
442445 	},
443446 	{	/* interrupt */
444
-		.start	= IRQ_DM646X_GPIOBNK0,
445
-		.end	= IRQ_DM646X_GPIOBNK0,
447
+		.start	= DAVINCI_INTC_IRQ(IRQ_DM646X_GPIOBNK0),
448
+		.end	= DAVINCI_INTC_IRQ(IRQ_DM646X_GPIOBNK0),
446449 		.flags	= IORESOURCE_IRQ,
447450 	},
448451 	{
449
-		.start	= IRQ_DM646X_GPIOBNK1,
450
-		.end	= IRQ_DM646X_GPIOBNK1,
452
+		.start	= DAVINCI_INTC_IRQ(IRQ_DM646X_GPIOBNK1),
453
+		.end	= DAVINCI_INTC_IRQ(IRQ_DM646X_GPIOBNK1),
451454 		.flags	= IORESOURCE_IRQ,
452455 	},
453456 	{
454
-		.start	= IRQ_DM646X_GPIOBNK2,
455
-		.end	= IRQ_DM646X_GPIOBNK2,
457
+		.start	= DAVINCI_INTC_IRQ(IRQ_DM646X_GPIOBNK2),
458
+		.end	= DAVINCI_INTC_IRQ(IRQ_DM646X_GPIOBNK2),
456459 		.flags	= IORESOURCE_IRQ,
457460 	},
458461 };
459462 
460463 static struct davinci_gpio_platform_data dm646x_gpio_platform_data = {
464
+	.no_auto_base	= true,
465
+	.base		= 0,
461466 	.ngpio		= 43,
462467 };
463468 
....@@ -497,21 +502,21 @@
497502 };
498503 
499504 /*
500
- * T0_BOT: Timer 0, bottom:  clockevent source for hrtimers
501
- * T0_TOP: Timer 0, top   :  clocksource for generic timekeeping
502
- * T1_BOT: Timer 1, bottom:  (used by DSP in TI DSPLink code)
503
- * T1_TOP: Timer 1, top   :  <unused>
505
+ * Bottom half of timer0 is used for clockevent, top half is used for
506
+ * clocksource.
504507  */
505
-static struct davinci_timer_info dm646x_timer_info = {
506
-	.timers		= davinci_timer_instance,
507
-	.clockevent_id	= T0_BOT,
508
-	.clocksource_id	= T0_TOP,
508
+static const struct davinci_timer_cfg dm646x_timer_cfg = {
509
+	.reg = DEFINE_RES_IO(DAVINCI_TIMER0_BASE, SZ_4K),
510
+	.irq = {
511
+		DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT12)),
512
+		DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT34)),
513
+	},
509514 };
510515 
511516 static struct plat_serial8250_port dm646x_serial0_platform_data[] = {
512517 	{
513518 		.mapbase	= DAVINCI_UART0_BASE,
514
-		.irq		= IRQ_UARTINT0,
519
+		.irq		= DAVINCI_INTC_IRQ(IRQ_UARTINT0),
515520 		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
516521 				  UPF_IOREMAP,
517522 		.iotype		= UPIO_MEM32,
....@@ -524,7 +529,7 @@
524529 static struct plat_serial8250_port dm646x_serial1_platform_data[] = {
525530 	{
526531 		.mapbase	= DAVINCI_UART1_BASE,
527
-		.irq		= IRQ_UARTINT1,
532
+		.irq		= DAVINCI_INTC_IRQ(IRQ_UARTINT1),
528533 		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
529534 				  UPF_IOREMAP,
530535 		.iotype		= UPIO_MEM32,
....@@ -537,7 +542,7 @@
537542 static struct plat_serial8250_port dm646x_serial2_platform_data[] = {
538543 	{
539544 		.mapbase	= DAVINCI_UART2_BASE,
540
-		.irq		= IRQ_DM646X_UARTINT2,
545
+		.irq		= DAVINCI_INTC_IRQ(IRQ_DM646X_UARTINT2),
541546 		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
542547 				  UPF_IOREMAP,
543548 		.iotype		= UPIO_MEM32,
....@@ -583,11 +588,6 @@
583588 	.pinmux_base		= DAVINCI_SYSTEM_MODULE_BASE,
584589 	.pinmux_pins		= dm646x_pins,
585590 	.pinmux_pins_num	= ARRAY_SIZE(dm646x_pins),
586
-	.intc_base		= DAVINCI_ARM_INTC_BASE,
587
-	.intc_type		= DAVINCI_INTC_TYPE_AINTC,
588
-	.intc_irq_prios		= dm646x_default_priorities,
589
-	.intc_irq_num		= DAVINCI_N_AINTC_IRQ,
590
-	.timer_info		= &dm646x_timer_info,
591591 	.emac_pdata		= &dm646x_emac_pdata,
592592 	.sram_dma		= 0x10010000,
593593 	.sram_len		= SZ_32K,
....@@ -652,6 +652,7 @@
652652 {
653653 	void __iomem *pll1, *psc;
654654 	struct clk *clk;
655
+	int rv;
655656 
656657 	clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, ref_clk_rate);
657658 	clk_register_fixed_rate(NULL, "aux_clkin", NULL, 0, aux_clkin_rate);
....@@ -663,8 +664,13 @@
663664 	dm646x_psc_init(NULL, psc);
664665 
665666 	clk = clk_get(NULL, "timer0");
667
+	if (WARN_ON(IS_ERR(clk))) {
668
+		pr_err("Unable to get the timer clock\n");
669
+		return;
670
+	}
666671 
667
-	davinci_timer_init(clk);
672
+	rv = davinci_timer_register(clk, &dm646x_timer_cfg);
673
+	WARN(rv, "Unable to register the timer: %d\n", rv);
668674 }
669675 
670676 static struct resource dm646x_pll2_resources[] = {
....@@ -688,6 +694,21 @@
688694 	platform_device_register(&dm646x_pll2_device);
689695 }
690696 
697
+static const struct davinci_aintc_config dm646x_aintc_config = {
698
+	.reg = {
699
+		.start		= DAVINCI_ARM_INTC_BASE,
700
+		.end		= DAVINCI_ARM_INTC_BASE + SZ_4K - 1,
701
+		.flags		= IORESOURCE_MEM,
702
+	},
703
+	.num_irqs		= 64,
704
+	.prios			= dm646x_default_priorities,
705
+};
706
+
707
+void __init dm646x_init_irq(void)
708
+{
709
+	davinci_aintc_init(&dm646x_aintc_config);
710
+}
711
+
691712 static int __init dm646x_init_devices(void)
692713 {
693714 	int ret = 0;