add gpio led uart

hc

2024-05-10 748e4f3d702def1a4bff191e0cf93b6a05340f01

 kernel/arch/arm/boot/dts/exynos4.dtsi
..
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@@ -51,6 +51,12 @@
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 		serial3 = &serial_3;
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 	};
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+	pmu: pmu {
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+		compatible = "arm,cortex-a9-pmu";
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+		interrupt-parent = <&combiner>;
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+		status = "disabled";
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+	};
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+
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 	soc: soc {
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 		compatible = "simple-bus";
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 		#address-cells = <1>;
..
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@@ -105,28 +111,28 @@
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 			syscon = <&pmu_system_controller>;
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 		};
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-		pd_mfc: mfc-power-domain@10023c40 {
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+		pd_mfc: power-domain@10023c40 {
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 			compatible = "samsung,exynos4210-pd";
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 			reg = <0x10023C40 0x20>;
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 			#power-domain-cells = <0>;
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 			label = "MFC";
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 		};
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-		pd_g3d: g3d-power-domain@10023c60 {
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+		pd_g3d: power-domain@10023c60 {
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 			compatible = "samsung,exynos4210-pd";
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 			reg = <0x10023C60 0x20>;
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 			#power-domain-cells = <0>;
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 			label = "G3D";
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 		};
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-		pd_lcd0: lcd0-power-domain@10023c80 {
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+		pd_lcd0: power-domain@10023c80 {
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 			compatible = "samsung,exynos4210-pd";
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 			reg = <0x10023C80 0x20>;
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 			#power-domain-cells = <0>;
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 			label = "LCD0";
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 		};
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-		pd_tv: tv-power-domain@10023c20 {
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+		pd_tv: power-domain@10023c20 {
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 			compatible = "samsung,exynos4210-pd";
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 			reg = <0x10023C20 0x20>;
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 			#power-domain-cells = <0>;
..
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@@ -134,21 +140,21 @@
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 			label = "TV";
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 		};
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-		pd_cam: cam-power-domain@10023c00 {
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+		pd_cam: power-domain@10023c00 {
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 			compatible = "samsung,exynos4210-pd";
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 			reg = <0x10023C00 0x20>;
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 			#power-domain-cells = <0>;
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 			label = "CAM";
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 		};
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-		pd_gps: gps-power-domain@10023ce0 {
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+		pd_gps: power-domain@10023ce0 {
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 			compatible = "samsung,exynos4210-pd";
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 			reg = <0x10023CE0 0x20>;
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 			#power-domain-cells = <0>;
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 			label = "GPS";
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 		};
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-		pd_gps_alive: gps-alive-power-domain@10023d00 {
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+		pd_gps_alive: power-domain@10023d00 {
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 			compatible = "samsung,exynos4210-pd";
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 			reg = <0x10023D00 0x20>;
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 			#power-domain-cells = <0>;
..
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@@ -167,12 +173,6 @@
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 			#interrupt-cells = <2>;
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 			interrupt-controller;
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 			reg = <0x10440000 0x1000>;
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-		};
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-
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-		pmu: pmu {
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-			compatible = "arm,cortex-a9-pmu";
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-			interrupt-parent = <&combiner>;
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-			interrupts = <2 2>, <3 2>;
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 		};
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 		sys_reg: syscon@10010000 {
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@@ -380,23 +380,8 @@
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 			clocks = <&clock CLK_USB_HOST>;
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 			clock-names = "usbhost";
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 			status = "disabled";
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-			#address-cells = <1>;
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-			#size-cells = <0>;
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-			port@0 {
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-				reg = <0>;
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-				phys = <&exynos_usbphy 1>;
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-				status = "disabled";
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-			};
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-			port@1 {
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-				reg = <1>;
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-				phys = <&exynos_usbphy 2>;
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-				status = "disabled";
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-			};
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-			port@2 {
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-				reg = <2>;
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-				phys = <&exynos_usbphy 3>;
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-				status = "disabled";
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-			};
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+			phys = <&exynos_usbphy 1>, <&exynos_usbphy 2>, <&exynos_usbphy 3>;
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+			phy-names = "host", "hsic0", "hsic1";
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 		};
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 		ohci: ohci@12590000 {
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@@ -406,13 +391,22 @@
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 			clocks = <&clock CLK_USB_HOST>;
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 			clock-names = "usbhost";
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 			status = "disabled";
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-			#address-cells = <1>;
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-			#size-cells = <0>;
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-			port@0 {
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-				reg = <0>;
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-				phys = <&exynos_usbphy 1>;
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-				status = "disabled";
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-			};
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+			phys = <&exynos_usbphy 1>;
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+			phy-names = "host";
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+		};
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+
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+		gpu: gpu@13000000 {
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+			compatible = "samsung,exynos4210-mali", "arm,mali-400";
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+			reg = <0x13000000 0x10000>;
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+			/*
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+			 * CLK_G3D is not actually bus clock but a IP-level clock.
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+			 * The bus clock is not described in hardware manual.
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+			 */
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+			clocks = <&clock CLK_G3D>,
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+				 <&clock CLK_SCLK_G3D>;
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+			clock-names = "bus", "core";
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+			power-domains = <&pd_g3d>;
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+			status = "disabled";
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 		};
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 		i2s1: i2s@13960000 {
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@@ -611,7 +605,7 @@
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 			status = "disabled";
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 			hdmi_i2c_phy: hdmiphy@38 {
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-				compatible = "exynos4210-hdmiphy";
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+				compatible = "samsung,exynos4210-hdmiphy";
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 				reg = <0x38>;
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 			};
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 		};
..
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@@ -675,45 +669,37 @@
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 			status = "disabled";
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 		};
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-		amba {
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-			#address-cells = <1>;
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-			#size-cells = <1>;
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-			compatible = "simple-bus";
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-			interrupt-parent = <&gic>;
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-			ranges;
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+		pdma0: pdma@12680000 {
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+			compatible = "arm,pl330", "arm,primecell";
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+			reg = <0x12680000 0x1000>;
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+			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
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+			clocks = <&clock CLK_PDMA0>;
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+			clock-names = "apb_pclk";
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+			#dma-cells = <1>;
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+			#dma-channels = <8>;
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+			#dma-requests = <32>;
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+		};
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-			pdma0: pdma@12680000 {
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-				compatible = "arm,pl330", "arm,primecell";
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-				reg = <0x12680000 0x1000>;
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-				interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
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-				clocks = <&clock CLK_PDMA0>;
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-				clock-names = "apb_pclk";
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-				#dma-cells = <1>;
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-				#dma-channels = <8>;
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-				#dma-requests = <32>;
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-			};
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+		pdma1: pdma@12690000 {
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+			compatible = "arm,pl330", "arm,primecell";
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+			reg = <0x12690000 0x1000>;
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+			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
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+			clocks = <&clock CLK_PDMA1>;
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+			clock-names = "apb_pclk";
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+			#dma-cells = <1>;
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+			#dma-channels = <8>;
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+			#dma-requests = <32>;
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+		};
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-			pdma1: pdma@12690000 {
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-				compatible = "arm,pl330", "arm,primecell";
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-				reg = <0x12690000 0x1000>;
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-				interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
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-				clocks = <&clock CLK_PDMA1>;
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-				clock-names = "apb_pclk";
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-				#dma-cells = <1>;
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-				#dma-channels = <8>;
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-				#dma-requests = <32>;
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-			};
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-
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-			mdma1: mdma@12850000 {
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-				compatible = "arm,pl330", "arm,primecell";
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-				reg = <0x12850000 0x1000>;
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-				interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
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-				clocks = <&clock CLK_MDMA>;
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-				clock-names = "apb_pclk";
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-				#dma-cells = <1>;
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-				#dma-channels = <8>;
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-				#dma-requests = <1>;
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-			};
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+		mdma1: mdma@12850000 {
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+			compatible = "arm,pl330", "arm,primecell";
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+			reg = <0x12850000 0x1000>;
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+			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
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+			clocks = <&clock CLK_MDMA>;
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+			clock-names = "apb_pclk";
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+			#dma-cells = <1>;
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+			#dma-channels = <8>;
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+			#dma-requests = <1>;
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 		};
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 		fimd: fimd@11c00000 {