add gpio led uart

hc

2024-05-10 748e4f3d702def1a4bff191e0cf93b6a05340f01

 kernel/arch/alpha/kernel/sys_nautilus.c
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@@ -32,7 +32,7 @@
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 #include <linux/pci.h>
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 #include <linux/init.h>
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 #include <linux/reboot.h>
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-#include <linux/bootmem.h>
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+#include <linux/memblock.h>
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 #include <linux/bitops.h>
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 #include <asm/ptrace.h>
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@@ -40,7 +40,6 @@
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 #include <asm/irq.h>
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 #include <asm/mmu_context.h>
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 #include <asm/io.h>
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-#include <asm/pgtable.h>
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 #include <asm/core_irongate.h>
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 #include <asm/hwrpb.h>
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 #include <asm/tlbflush.h>
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@@ -187,10 +186,6 @@
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 extern void pcibios_claim_one_bus(struct pci_bus *);
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-static struct resource irongate_io = {
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-	.name	= "Irongate PCI IO",
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-	.flags	= IORESOURCE_IO,
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-};
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 static struct resource irongate_mem = {
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 	.name	= "Irongate PCI MEM",
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 	.flags	= IORESOURCE_MEM,
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@@ -208,17 +203,19 @@
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 	struct pci_controller *hose = hose_head;
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 	struct pci_host_bridge *bridge;
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 	struct pci_bus *bus;
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-	struct pci_dev *irongate;
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 	unsigned long bus_align, bus_size, pci_mem;
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 	unsigned long memtop = max_low_pfn << PAGE_SHIFT;
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-	int ret;
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 	bridge = pci_alloc_host_bridge(0);
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 	if (!bridge)
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 		return;
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+	/* Use default IO. */
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 	pci_add_resource(&bridge->windows, &ioport_resource);
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-	pci_add_resource(&bridge->windows, &iomem_resource);
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+	/* Irongate PCI memory aperture, calculate requred size before
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+	   setting it up. */
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+	pci_add_resource(&bridge->windows, &irongate_mem);
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+
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 	pci_add_resource(&bridge->windows, &busn_resource);
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 	bridge->dev.parent = NULL;
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 	bridge->sysdata = hose;
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@@ -226,59 +223,49 @@
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 	bridge->ops = alpha_mv.pci_ops;
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 	bridge->swizzle_irq = alpha_mv.pci_swizzle;
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 	bridge->map_irq = alpha_mv.pci_map_irq;
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+	bridge->size_windows = 1;
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 	/* Scan our single hose.  */
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-	ret = pci_scan_root_bus_bridge(bridge);
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-	if (ret) {
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+	if (pci_scan_root_bus_bridge(bridge)) {
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 		pci_free_host_bridge(bridge);
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 		return;
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 	}
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-
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 	bus = hose->bus = bridge->bus;
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 	pcibios_claim_one_bus(bus);
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-	irongate = pci_get_domain_bus_and_slot(pci_domain_nr(bus), 0, 0);
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-	bus->self = irongate;
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-	bus->resource[0] = &irongate_io;
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-	bus->resource[1] = &irongate_mem;
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-
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 	pci_bus_size_bridges(bus);
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-	/* IO port range. */
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-	bus->resource[0]->start = 0;
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-	bus->resource[0]->end = 0xffff;
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-
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-	/* Set up PCI memory range - limit is hardwired to 0xffffffff,
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-	   base must be at aligned to 16Mb. */
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-	bus_align = bus->resource[1]->start;
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-	bus_size = bus->resource[1]->end + 1 - bus_align;
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+	/* Now we've got the size and alignment of PCI memory resources
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+	   stored in irongate_mem. Set up the PCI memory range: limit is
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+	   hardwired to 0xffffffff, base must be aligned to 16Mb. */
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+	bus_align = irongate_mem.start;
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+	bus_size = irongate_mem.end + 1 - bus_align;
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 	if (bus_align < 0x1000000UL)
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 		bus_align = 0x1000000UL;
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 	pci_mem = (0x100000000UL - bus_size) & -bus_align;
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+	irongate_mem.start = pci_mem;
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+	irongate_mem.end = 0xffffffffUL;
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-	bus->resource[1]->start = pci_mem;
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-	bus->resource[1]->end = 0xffffffffUL;
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-	if (request_resource(&iomem_resource, bus->resource[1]) < 0)
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+	/* Register our newly calculated PCI memory window in the resource
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+	   tree. */
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+	if (request_resource(&iomem_resource, &irongate_mem) < 0)
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 		printk(KERN_ERR "Failed to request MEM on hose 0\n");
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+
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+	printk(KERN_INFO "Irongate pci_mem %pR\n", &irongate_mem);
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 	if (pci_mem < memtop)
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 		memtop = pci_mem;
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 	if (memtop > alpha_mv.min_mem_address) {
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 		free_reserved_area(__va(alpha_mv.min_mem_address),
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 				   __va(memtop), -1, NULL);
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-		printk("nautilus_init_pci: %ldk freed\n",
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+		printk(KERN_INFO "nautilus_init_pci: %ldk freed\n",
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 			(memtop - alpha_mv.min_mem_address) >> 10);
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 	}
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-
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 	if ((IRONGATE0->dev_vendor >> 16) > 0x7006)	/* Albacore? */
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 		IRONGATE0->pci_mem = pci_mem;
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 	pci_bus_assign_resources(bus);
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-
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-	/* pci_common_swizzle() relies on bus->self being NULL
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-	   for the root bus, so just clear it. */
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-	bus->self = NULL;
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 	pci_bus_add_devices(bus);
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 }
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