add gpio led uart

hc

2024-05-10 748e4f3d702def1a4bff191e0cf93b6a05340f01

 kernel/Documentation/devicetree/bindings/common-properties.txt
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 ----------
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 The Devicetree Specification does not define any properties related to hardware
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-byteswapping, but endianness issues show up frequently in porting Linux to
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+byte swapping, but endianness issues show up frequently in porting drivers to
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 different machine types.  This document attempts to provide a consistent
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-way of handling byteswapping across drivers.
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+way of handling byte swapping across drivers.
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 Optional properties:
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  - big-endian: Boolean; force big endian register accesses
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    unconditionally (e.g. ioread32be/iowrite32be).  Use this if you
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-   know the peripheral always needs to be accessed in BE mode.
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+   know the peripheral always needs to be accessed in big endian (BE) mode.
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  - little-endian: Boolean; force little endian register accesses
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    unconditionally (e.g. readl/writel).  Use this if you know the
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-   peripheral always needs to be accessed in LE mode.
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+   peripheral always needs to be accessed in little endian (LE) mode.
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  - native-endian: Boolean; always use register accesses matched to the
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    endianness of the kernel binary (e.g. LE vmlinux -> readl/writel,
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-   BE vmlinux -> ioread32be/iowrite32be).  In this case no byteswaps
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+   BE vmlinux -> ioread32be/iowrite32be).  In this case no byte swaps
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    will ever be performed.  Use this if the hardware "self-adjusts"
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    register endianness based on the CPU's configured endianness.
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 If a binding supports these properties, then the binding should also
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 specify the default behavior if none of these properties are present.
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 In such cases, little-endian is the preferred default, but it is not
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-a requirement.  The of_device_is_big_endian() and of_fdt_is_big_endian()
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-helper functions do assume that little-endian is the default, because
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-most existing (PCI-based) drivers implicitly default to LE by using
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-readl/writel for MMIO accesses.
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+a requirement.  Some implementations assume that little-endian is
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+the default, because most existing (PCI-based) drivers implicitly
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+default to LE for their MMIO accesses.
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 Examples:
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 Scenario 1 : CPU in LE mode & device in LE mode.