forked from ~ljy/RK356X_SDK_RELEASE

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hc
2023-11-30 6c9be420e167ee7ce45c0309586f09ddab28ac15 
 kernel/drivers/spi/spi-rockchip.c
....@@ -14,6 +14,7 @@
1414  */
1515 
1616 #include <linux/clk.h>
17
+#include <linux/delay.h>
1718 #include <linux/dmaengine.h>
1819 #include <linux/gpio.h>
1920 #include <linux/interrupt.h>
....@@ -181,6 +182,12 @@
181182 
182183 #define ROCKCHIP_SPI_REGISTER_SIZE		0x1000
183184 
185
+enum rockchip_spi_xfer_mode {
186
+	ROCKCHIP_SPI_DMA,
187
+	ROCKCHIP_SPI_IRQ,
188
+	ROCKCHIP_SPI_POLL,
189
+};
190
+
184191 struct rockchip_spi_quirks {
185192 	u32 max_baud_div_in_cpha;
186193 };
....@@ -201,7 +208,9 @@
201208 	unsigned int rx_left;
202209 
203210 	atomic_t state;
211
+	struct completion xfer_done;
204212 
213
+	u32 version;
205214 	/*depth of the FIFO buffer */
206215 	u32 fifo_len;
207216 	/* frequency of spiclk */
....@@ -211,11 +220,13 @@
211220 
212221 	u8 n_bytes;
213222 	u8 rsd;
223
+	u8 csm;
224
+	bool poll; /* only support transfer data by cpu polling */
214225 
215226 	bool cs_asserted[ROCKCHIP_SPI_MAX_CS_NUM];
216227 
217228 	struct pinctrl_state *high_speed_state;
218
-	bool slave_abort;
229
+	bool slave_aborted;
219230 	bool gpio_requested;
220231 	bool cs_inactive; /* spi slave tansmition stop when cs inactive */
221232 	struct spi_transfer *xfer; /* Store xfer temporarily */
....@@ -231,17 +242,29 @@
231242 	writel_relaxed((enable ? 1U : 0U), rs->regs + ROCKCHIP_SPI_SSIENR);
232243 }
233244 
234
-static inline void wait_for_idle(struct rockchip_spi *rs, bool slave_mode)
245
+static inline void wait_for_tx_idle(struct rockchip_spi *rs, bool slave_mode)
235246 {
236247 	unsigned long timeout = jiffies + msecs_to_jiffies(5);
248
+	u32 bit_filed = SR_BUSY;
249
+	u32 idle_val = 0;
250
+	uint32_t speed, us;
251
+
252
+	if (slave_mode && rs->version == ROCKCHIP_SPI_VER2_TYPE2) {
253
+		bit_filed = SR_SLAVE_TX_BUSY;
254
+		idle_val = 0;
255
+	} else if (slave_mode) {
256
+		bit_filed = SR_TF_EMPTY;
257
+		idle_val = 1;
258
+	}
237259 
238260 	do {
239
-		if (slave_mode) {
240
-			if (!(readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_SLAVE_TX_BUSY))
241
-				return;
242
-		} else {
243
-			if (!(readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY))
244
-				return;
261
+		if ((readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & bit_filed) == idle_val) {
262
+			if (bit_filed == SR_TF_EMPTY) {
263
+				speed = rs->speed_hz;
264
+				us = (8 * 1000000 / speed) * 2;
265
+				udelay(us);
266
+			}
267
+			return;
245268 		}
246269 	} while (!time_after(jiffies, timeout));
247270 
....@@ -250,11 +273,7 @@
250273 
251274 static u32 get_fifo_len(struct rockchip_spi *rs)
252275 {
253
-	u32 ver;
254
-
255
-	ver = readl_relaxed(rs->regs + ROCKCHIP_SPI_VERSION);
256
-
257
-	switch (ver) {
276
+	switch (rs->version) {
258277 	case ROCKCHIP_SPI_VER2_TYPE1:
259278 	case ROCKCHIP_SPI_VER2_TYPE2:
260279 		return 64;
....@@ -299,6 +318,11 @@
299318 {
300319 	struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
301320 
321
+	dev_err(rs->dev, "state=%x\n", atomic_read(&rs->state));
322
+	dev_err(rs->dev, "tx_left=%x\n", rs->tx_left);
323
+	dev_err(rs->dev, "rx_left=%x\n", rs->rx_left);
324
+	print_hex_dump(KERN_ERR, "regs ", DUMP_PREFIX_OFFSET, 4, 4, rs->regs, 0x4c, 0);
325
+
302326 	/* stop running spi transfer
303327 	 * this also flushes both rx and tx fifos
304328 	 */
....@@ -313,6 +337,7 @@
313337 
314338 	if (atomic_read(&rs->state) & RXDMA)
315339 		dmaengine_terminate_async(ctlr->dma_rx);
340
+	atomic_set(&rs->state, 0);
316341 }
317342 
318343 static void rockchip_spi_pio_writer(struct rockchip_spi *rs)
....@@ -374,7 +399,7 @@
374399 	struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
375400 
376401 	/* When int_cs_inactive comes, spi slave abort */
377
-	if (readl_relaxed(rs->regs + ROCKCHIP_SPI_IMR) & INT_CS_INACTIVE) {
402
+	if (rs->cs_inactive && readl_relaxed(rs->regs + ROCKCHIP_SPI_ISR) & INT_CS_INACTIVE) {
378403 		ctlr->slave_abort(ctlr);
379404 		writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR);
380405 		writel_relaxed(0xffffffff, rs->regs + ROCKCHIP_SPI_ICR);
....@@ -390,7 +415,7 @@
390415 		spi_enable_chip(rs, false);
391416 		writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR);
392417 		writel_relaxed(0xffffffff, rs->regs + ROCKCHIP_SPI_ICR);
393
-		spi_finalize_current_transfer(ctlr);
418
+		complete(&rs->xfer_done);
394419 	}
395420 
396421 	return IRQ_HANDLED;
....@@ -400,8 +425,6 @@
400425 				    struct spi_controller *ctlr,
401426 				    struct spi_transfer *xfer)
402427 {
403
-	rs->tx = xfer->tx_buf;
404
-	rs->rx = xfer->rx_buf;
405428 	rs->tx_left = rs->tx ? xfer->len / rs->n_bytes : 0;
406429 	rs->rx_left = xfer->len / rs->n_bytes;
407430 
....@@ -427,14 +450,16 @@
427450 	struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
428451 	int state = atomic_fetch_andnot(RXDMA, &rs->state);
429452 
430
-	if (state & TXDMA && !rs->slave_abort)
453
+	if (state & TXDMA && !rs->slave_aborted)
431454 		return;
432455 
433456 	if (rs->cs_inactive)
434457 		writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR);
435458 
436459 	spi_enable_chip(rs, false);
437
-	spi_finalize_current_transfer(ctlr);
460
+	writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR);
461
+	writel_relaxed(0xffffffff, rs->regs + ROCKCHIP_SPI_ICR);
462
+	complete(&rs->xfer_done);
438463 }
439464 
440465 static void rockchip_spi_dma_txcb(void *data)
....@@ -443,14 +468,16 @@
443468 	struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
444469 	int state = atomic_fetch_andnot(TXDMA, &rs->state);
445470 
446
-	if (state & RXDMA && !rs->slave_abort)
471
+	if (state & RXDMA && !rs->slave_aborted)
447472 		return;
448473 
449474 	/* Wait until the FIFO data completely. */
450
-	wait_for_idle(rs, ctlr->slave);
475
+	wait_for_tx_idle(rs, ctlr->slave);
451476 
452477 	spi_enable_chip(rs, false);
453
-	spi_finalize_current_transfer(ctlr);
478
+	writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR);
479
+	writel_relaxed(0xffffffff, rs->regs + ROCKCHIP_SPI_ICR);
480
+	complete(&rs->xfer_done);
454481 }
455482 
456483 static u32 rockchip_spi_calc_burst_size(u32 data_len)
....@@ -472,9 +499,6 @@
472499 	struct dma_async_tx_descriptor *rxdesc, *txdesc;
473500 
474501 	atomic_set(&rs->state, 0);
475
-
476
-	rs->tx = xfer->tx_buf;
477
-	rs->rx = xfer->rx_buf;
478502 
479503 	rxdesc = NULL;
480504 	if (xfer->rx_buf) {
....@@ -545,9 +569,59 @@
545569 	return 1;
546570 }
547571 
548
-static void rockchip_spi_config(struct rockchip_spi *rs,
572
+static int rockchip_spi_pio_transfer(struct rockchip_spi *rs,
573
+		struct spi_controller *ctlr, struct spi_transfer *xfer)
574
+{
575
+	unsigned long time, timeout;
576
+	u32 speed_hz = xfer->speed_hz;
577
+	unsigned long long ms;
578
+	int ret = 0;
579
+
580
+	if (!speed_hz)
581
+		speed_hz = 100000;
582
+
583
+	ms = 8LL * 1000LL * xfer->len;
584
+	do_div(ms, speed_hz);
585
+	ms += ms + 200; /* some tolerance */
586
+
587
+	if (ms > UINT_MAX || ctlr->slave)
588
+		ms = UINT_MAX;
589
+
590
+	timeout = jiffies + msecs_to_jiffies(ms);
591
+	time = jiffies;
592
+	rs->tx_left = rs->tx ? xfer->len / rs->n_bytes : 0;
593
+	rs->rx_left = rs->rx ? xfer->len / rs->n_bytes : 0;
594
+
595
+	spi_enable_chip(rs, true);
596
+
597
+	while (rs->tx_left || rs->rx_left) {
598
+		if (rs->tx)
599
+			rockchip_spi_pio_writer(rs);
600
+
601
+		if (rs->rx)
602
+			rockchip_spi_pio_reader(rs);
603
+
604
+		cpu_relax();
605
+
606
+		if (time_after(time, timeout)) {
607
+			ret = -EIO;
608
+			goto out;
609
+		}
610
+	};
611
+
612
+	/* If tx, wait until the FIFO data completely. */
613
+	if (rs->tx)
614
+		wait_for_tx_idle(rs, ctlr->slave);
615
+
616
+out:
617
+	spi_enable_chip(rs, false);
618
+
619
+	return ret;
620
+}
621
+
622
+static int rockchip_spi_config(struct rockchip_spi *rs,
549623 		struct spi_device *spi, struct spi_transfer *xfer,
550
-		bool use_dma, bool slave_mode)
624
+		enum rockchip_spi_xfer_mode xfer_mode, bool slave_mode)
551625 {
552626 	u32 cr0 = CR0_FRF_SPI  << CR0_FRF_OFFSET
553627 		| CR0_BHT_8BIT << CR0_BHT_OFFSET
....@@ -558,21 +632,33 @@
558632 
559633 	if (slave_mode)
560634 		cr0 |= CR0_OPM_SLAVE << CR0_OPM_OFFSET;
561
-	rs->slave_abort = false;
635
+	rs->slave_aborted = false;
562636 
563637 	cr0 |= rs->rsd << CR0_RSD_OFFSET;
638
+	cr0 |= rs->csm << CR0_CSM_OFFSET;
564639 	cr0 |= (spi->mode & 0x3U) << CR0_SCPH_OFFSET;
565640 	if (spi->mode & SPI_LSB_FIRST)
566641 		cr0 |= CR0_FBM_LSB << CR0_FBM_OFFSET;
567642 	if (spi->mode & SPI_CS_HIGH)
568643 		cr0 |= BIT(spi->chip_select) << CR0_SOI_OFFSET;
569644 
570
-	if (xfer->rx_buf && xfer->tx_buf)
645
+	if (xfer->rx_buf && xfer->tx_buf) {
571646 		cr0 |= CR0_XFM_TR << CR0_XFM_OFFSET;
572
-	else if (xfer->rx_buf)
647
+	} else if (xfer->rx_buf) {
573648 		cr0 |= CR0_XFM_RO << CR0_XFM_OFFSET;
574
-	else if (use_dma)
575
-		cr0 |= CR0_XFM_TO << CR0_XFM_OFFSET;
649
+	} else if (xfer->tx_buf) {
650
+		/*
651
+		 * Use the water line of rx fifo in full duplex mode to trigger
652
+		 * the interruption of tx irq transmission completion.
653
+		 */
654
+		if (xfer_mode == ROCKCHIP_SPI_IRQ)
655
+			cr0 |= CR0_XFM_TR << CR0_XFM_OFFSET;
656
+		else
657
+			cr0 |= CR0_XFM_TO << CR0_XFM_OFFSET;
658
+	} else {
659
+		dev_err(rs->dev, "no transmission buffer\n");
660
+		return -EINVAL;
661
+	}
576662 
577663 	switch (xfer->bits_per_word) {
578664 	case 4:
....@@ -595,7 +681,7 @@
595681 		unreachable();
596682 	}
597683 
598
-	if (use_dma) {
684
+	if (xfer_mode == ROCKCHIP_SPI_DMA) {
599685 		if (xfer->tx_buf)
600686 			dmacr |= TF_DMA_EN;
601687 		if (xfer->rx_buf)
....@@ -652,6 +738,8 @@
652738 	writel_relaxed(2 * DIV_ROUND_UP(rs->freq, 2 * xfer->speed_hz),
653739 			rs->regs + ROCKCHIP_SPI_BAUDR);
654740 	rs->speed_hz = xfer->speed_hz;
741
+
742
+	return 0;
655743 }
656744 
657745 static size_t rockchip_spi_max_transfer_size(struct spi_device *spi)
....@@ -663,50 +751,54 @@
663751 {
664752 	struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
665753 	u32 rx_fifo_left;
666
-	struct dma_tx_state state;
667
-	enum dma_status status;
668754 
669
-	/* Get current dma rx point */
670
-	if (atomic_read(&rs->state) & RXDMA) {
671
-		dmaengine_pause(ctlr->dma_rx);
672
-		status = dmaengine_tx_status(ctlr->dma_rx, ctlr->dma_rx->cookie, &state);
673
-		if (status == DMA_ERROR) {
674
-			rs->rx = rs->xfer->rx_buf;
675
-			rs->xfer->len = 0;
676
-			rx_fifo_left = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR);
677
-			for (; rx_fifo_left; rx_fifo_left--)
678
-				readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR);
679
-			goto out;
680
-		} else {
681
-			rs->rx += rs->xfer->len - rs->n_bytes * state.residue;
682
-		}
683
-	}
755
+	/* Flush rx fifo */
756
+	rx_fifo_left = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR);
757
+	for (; rx_fifo_left; rx_fifo_left--)
758
+		readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR);
684759 
685
-	/* Get the valid data left in rx fifo and set rs->xfer->len real rx size */
686
-	if (rs->rx) {
687
-		rx_fifo_left = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR);
688
-		for (; rx_fifo_left; rx_fifo_left--) {
689
-			u32 rxw = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR);
760
+	rs->slave_aborted = true;
761
+	complete(&rs->xfer_done);
690762 
691
-			if (rs->n_bytes == 1)
692
-				*(u8 *)rs->rx = (u8)rxw;
693
-			else
694
-				*(u16 *)rs->rx = (u16)rxw;
695
-			rs->rx += rs->n_bytes;
763
+	return 0;
764
+}
765
+
766
+static int rockchip_spi_transfer_wait(struct spi_controller *ctlr,
767
+				      struct spi_transfer *xfer)
768
+{
769
+	struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
770
+	u32 speed_hz = xfer->speed_hz;
771
+	unsigned long long ms;
772
+
773
+	if (spi_controller_is_slave(ctlr)) {
774
+		if (wait_for_completion_interruptible(&rs->xfer_done)) {
775
+			dev_dbg(rs->dev, "RK SPI transfer interrupted\n");
776
+			return -EINTR;
696777 		}
697778 
698
-		rs->xfer->len = (unsigned int)(rs->rx - rs->xfer->rx_buf);
699
-	}
779
+		if (rs->slave_aborted) {
780
+			dev_err(rs->dev, "RK SPI transfer slave abort\n");
781
+			return -EIO;
782
+		}
783
+	} else {
784
+		if (!speed_hz)
785
+			speed_hz = 100000;
700786 
701
-out:
702
-	if (atomic_read(&rs->state) & RXDMA)
703
-		dmaengine_terminate_sync(ctlr->dma_rx);
704
-	if (atomic_read(&rs->state) & TXDMA)
705
-		dmaengine_terminate_sync(ctlr->dma_tx);
706
-	atomic_set(&rs->state, 0);
707
-	spi_enable_chip(rs, false);
708
-	rs->slave_abort = true;
709
-	complete(&ctlr->xfer_completion);
787
+		ms = 8LL * 1000LL * xfer->len;
788
+		do_div(ms, speed_hz);
789
+		ms += ms + 200; /* some tolerance */
790
+
791
+		if (ms > UINT_MAX)
792
+			ms = UINT_MAX;
793
+
794
+		ms = wait_for_completion_timeout(&rs->xfer_done,
795
+						 msecs_to_jiffies(ms));
796
+
797
+		if (ms == 0) {
798
+			dev_err(rs->dev, "RK SPI transfer timed out\n");
799
+			return -ETIMEDOUT;
800
+		}
801
+	}
710802 
711803 	return 0;
712804 }
....@@ -717,11 +809,13 @@
717809 		struct spi_transfer *xfer)
718810 {
719811 	struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
812
+	int ret;
720813 	bool use_dma;
814
+	enum rockchip_spi_xfer_mode xfer_mode;
721815 
722816 	/* Zero length transfers won't trigger an interrupt on completion */
723817 	if (!xfer->len) {
724
-		spi_finalize_current_transfer(ctlr);
818
+		complete(&rs->xfer_done);
725819 		return 1;
726820 	}
727821 
....@@ -740,14 +834,40 @@
740834 
741835 	rs->n_bytes = xfer->bits_per_word <= 8 ? 1 : 2;
742836 	rs->xfer = xfer;
743
-	use_dma = ctlr->can_dma ? ctlr->can_dma(ctlr, spi, xfer) : false;
837
+	if (rs->poll) {
838
+		xfer_mode = ROCKCHIP_SPI_POLL;
839
+	} else {
840
+		use_dma = ctlr->can_dma ? ctlr->can_dma(ctlr, spi, xfer) : false;
841
+		if (use_dma)
842
+			xfer_mode = ROCKCHIP_SPI_DMA;
843
+		else
844
+			xfer_mode = ROCKCHIP_SPI_IRQ;
845
+	}
744846 
745
-	rockchip_spi_config(rs, spi, xfer, use_dma, ctlr->slave);
847
+	ret = rockchip_spi_config(rs, spi, xfer, xfer_mode, ctlr->slave);
848
+	if (ret)
849
+		return ret;
746850 
747
-	if (use_dma)
748
-		return rockchip_spi_prepare_dma(rs, ctlr, xfer);
851
+	rs->tx = xfer->tx_buf;
852
+	rs->rx = xfer->rx_buf;
749853 
750
-	return rockchip_spi_prepare_irq(rs, ctlr, xfer);
854
+	reinit_completion(&rs->xfer_done);
855
+
856
+	switch (xfer_mode) {
857
+	case ROCKCHIP_SPI_POLL:
858
+		ret = rockchip_spi_pio_transfer(rs, ctlr, xfer);
859
+		break;
860
+	case ROCKCHIP_SPI_DMA:
861
+		ret = rockchip_spi_prepare_dma(rs, ctlr, xfer);
862
+		break;
863
+	default:
864
+		ret = rockchip_spi_prepare_irq(rs, ctlr, xfer);
865
+	}
866
+
867
+	if (ret > 0)
868
+		ret = rockchip_spi_transfer_wait(ctlr, xfer);
869
+
870
+	return ret;
751871 }
752872 
753873 static bool rockchip_spi_can_dma(struct spi_controller *ctlr,
....@@ -879,7 +999,7 @@
879999 	struct spi_controller *ctlr;
8801000 	struct resource *mem;
8811001 	struct device_node *np = pdev->dev.of_node;
882
-	u32 rsd_nsecs;
1002
+	u32 rsd_nsecs, csm;
8831003 	bool slave_mode;
8841004 	struct pinctrl *pinctrl = NULL;
8851005 	const struct rockchip_spi_quirks *quirks_cfg;
....@@ -968,6 +1088,16 @@
9681088 		rs->rsd = rsd;
9691089 	}
9701090 
1091
+	if (!device_property_read_u32(&pdev->dev, "csm", &csm)) {
1092
+		if (csm > CR0_CSM_ONE)	{
1093
+			dev_warn(rs->dev, "The csm value %u exceeds the limit, clamping at %u\n",
1094
+				 csm, CR0_CSM_ONE);
1095
+			csm = CR0_CSM_ONE;
1096
+		}
1097
+		rs->csm = csm;
1098
+	}
1099
+
1100
+	rs->version = readl_relaxed(rs->regs + ROCKCHIP_SPI_VERSION);
9711101 	rs->fifo_len = get_fifo_len(rs);
9721102 	if (!rs->fifo_len) {
9731103 		dev_err(&pdev->dev, "Failed to get fifo length\n");
....@@ -1030,10 +1160,18 @@
10301160 		ctlr->can_dma = rockchip_spi_can_dma;
10311161 	}
10321162 
1033
-	switch (readl_relaxed(rs->regs + ROCKCHIP_SPI_VERSION)) {
1163
+	rs->poll = device_property_read_bool(&pdev->dev, "rockchip,poll-only");
1164
+	init_completion(&rs->xfer_done);
1165
+	if (rs->poll && slave_mode) {
1166
+		dev_err(rs->dev, "only support rockchip,poll-only property in master mode\n");
1167
+		ret = -EINVAL;
1168
+		goto err_free_dma_rx;
1169
+	}
1170
+
1171
+	switch (rs->version) {
10341172 	case ROCKCHIP_SPI_VER2_TYPE1:
10351173 	case ROCKCHIP_SPI_VER2_TYPE2:
1036
-		if (ctlr->can_dma && slave_mode)
1174
+		if (slave_mode)
10371175 			rs->cs_inactive = true;
10381176 		else
10391177 			rs->cs_inactive = false;
....@@ -1041,7 +1179,6 @@
10411179 	default:
10421180 		rs->cs_inactive = false;
10431181 	}
1044
-
10451182 	pinctrl = devm_pinctrl_get(&pdev->dev);
10461183 	if (!IS_ERR(pinctrl)) {
10471184 		rs->high_speed_state = pinctrl_lookup_state(pinctrl, "high_speed");
....@@ -1072,6 +1209,8 @@
10721209 		else
10731210 			dev_info(&pdev->dev, "register misc device %s\n", misc_name);
10741211 	}
1212
+
1213
+	dev_info(rs->dev, "probed, poll=%d, rsd=%d\n", rs->poll, rs->rsd);
10751214 
10761215 	return 0;
10771216 
....@@ -1120,51 +1259,6 @@
11201259 	return 0;
11211260 }
11221261 
1123
-#ifdef CONFIG_PM_SLEEP
1124
-static int rockchip_spi_suspend(struct device *dev)
1125
-{
1126
-	int ret;
1127
-	struct spi_controller *ctlr = dev_get_drvdata(dev);
1128
-	struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
1129
-
1130
-	ret = spi_controller_suspend(ctlr);
1131
-	if (ret < 0)
1132
-		return ret;
1133
-
1134
-	clk_disable_unprepare(rs->spiclk);
1135
-	clk_disable_unprepare(rs->apb_pclk);
1136
-
1137
-	pinctrl_pm_select_sleep_state(dev);
1138
-
1139
-	return 0;
1140
-}
1141
-
1142
-static int rockchip_spi_resume(struct device *dev)
1143
-{
1144
-	int ret;
1145
-	struct spi_controller *ctlr = dev_get_drvdata(dev);
1146
-	struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
1147
-
1148
-	pinctrl_pm_select_default_state(dev);
1149
-
1150
-	ret = clk_prepare_enable(rs->apb_pclk);
1151
-	if (ret < 0)
1152
-		return ret;
1153
-
1154
-	ret = clk_prepare_enable(rs->spiclk);
1155
-	if (ret < 0)
1156
-		clk_disable_unprepare(rs->apb_pclk);
1157
-
1158
-	ret = spi_controller_resume(ctlr);
1159
-	if (ret < 0) {
1160
-		clk_disable_unprepare(rs->spiclk);
1161
-		clk_disable_unprepare(rs->apb_pclk);
1162
-	}
1163
-
1164
-	return 0;
1165
-}
1166
-#endif /* CONFIG_PM_SLEEP */
1167
-
11681262 #ifdef CONFIG_PM
11691263 static int rockchip_spi_runtime_suspend(struct device *dev)
11701264 {
....@@ -1195,6 +1289,46 @@
11951289 }
11961290 #endif /* CONFIG_PM */
11971291 
1292
+#ifdef CONFIG_PM_SLEEP
1293
+static int rockchip_spi_suspend(struct device *dev)
1294
+{
1295
+	int ret;
1296
+	struct spi_controller *ctlr = dev_get_drvdata(dev);
1297
+
1298
+	ret = spi_controller_suspend(ctlr);
1299
+	if (ret < 0)
1300
+		return ret;
1301
+
1302
+	/* Avoid redundant clock disable */
1303
+	if (!pm_runtime_status_suspended(dev))
1304
+		rockchip_spi_runtime_suspend(dev);
1305
+
1306
+	pinctrl_pm_select_sleep_state(dev);
1307
+
1308
+	return 0;
1309
+}
1310
+
1311
+static int rockchip_spi_resume(struct device *dev)
1312
+{
1313
+	int ret;
1314
+	struct spi_controller *ctlr = dev_get_drvdata(dev);
1315
+
1316
+	pinctrl_pm_select_default_state(dev);
1317
+
1318
+	if (!pm_runtime_status_suspended(dev)) {
1319
+		ret = rockchip_spi_runtime_resume(dev);
1320
+		if (ret < 0)
1321
+			return ret;
1322
+	}
1323
+
1324
+	ret = spi_controller_resume(ctlr);
1325
+	if (ret < 0)
1326
+		rockchip_spi_runtime_suspend(dev);
1327
+
1328
+	return 0;
1329
+}
1330
+#endif /* CONFIG_PM_SLEEP */
1331
+
11981332 static const struct dev_pm_ops rockchip_spi_pm = {
11991333 	SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(rockchip_spi_suspend, rockchip_spi_resume)
12001334 	SET_RUNTIME_PM_OPS(rockchip_spi_runtime_suspend,