forked from ~ljy/RK356X_SDK_RELEASE
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2023-12-11 6778948f9de86c3cfaf36725a7c87dcff9ba247f 
 u-boot/drivers/phy/phy-rockchip-inno-usb2.c
....@@ -149,6 +149,7 @@
149149  *		     primary stage.
150150  * @grf: General Register Files register base.
151151  * @usbgrf_base : USB General Register Files register base.
152
+ * @phy_base: the base address of USB PHY.
152153  * @phy_rst: phy reset control.
153154  * @phy_cfg: phy register configuration, assigned by driver data.
154155  */
....@@ -157,6 +158,7 @@
157158 	u8		primary_retries;
158159 	struct regmap	*grf_base;
159160 	struct regmap	*usbgrf_base;
161
+	void __iomem	*phy_base;
160162 	struct udevice	*vbus_supply[USB2PHY_NUM_PORTS];
161163 	struct reset_ctl phy_rst;
162164 	const struct rockchip_usb2phy_cfg	*phy_cfg;
....@@ -282,6 +284,11 @@
282284 		return POWER_SUPPLY_TYPE_UNKNOWN;
283285 	}
284286 
287
+#ifdef CONFIG_ROCKCHIP_RK3036
288
+	chg_type = POWER_SUPPLY_TYPE_USB;
289
+	goto out;
290
+#endif
291
+
285292 	/* Suspend USB-PHY and put the controller in non-driving mode */
286293 	property_enable(base, &port_cfg->phy_sus, true);
287294 	property_enable(base, &rphy->phy_cfg->chg_det.opmode, false);
....@@ -388,36 +395,14 @@
388395 	port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG];
389396 
390397 	/* Set the USB-PHY COMMONONN to 1'b0 to ensure USB's clocks */
391
-	property_enable(base, &rphy->phy_cfg->clkout_ctl, false);
398
+	if(rphy->phy_cfg->clkout_ctl.disable)
399
+		property_enable(base, &rphy->phy_cfg->clkout_ctl, true);
392400 
393401 	/* Reset USB-PHY */
394402 	property_enable(base, &port_cfg->phy_sus, true);
395403 	udelay(20);
396404 	property_enable(base, &port_cfg->phy_sus, false);
397405 	mdelay(2);
398
-}
399
-
400
-static struct udevice *rockchip_usb2phy_check_vbus(struct phy *phy)
401
-{
402
-	struct udevice *parent = phy->dev->parent;
403
-	struct rockchip_usb2phy *rphy = dev_get_priv(parent);
404
-	const struct rockchip_usb2phy_port_cfg *port_cfg;
405
-	struct regmap *base = get_reg_base(rphy);
406
-	struct udevice *vbus = NULL;
407
-	bool iddig = true;
408
-
409
-	if (phy->id == USB2PHY_PORT_HOST) {
410
-		vbus = rphy->vbus_supply[USB2PHY_PORT_HOST];
411
-	} else if (phy->id == USB2PHY_PORT_OTG) {
412
-		port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG];
413
-		if (port_cfg->utmi_iddig.offset) {
414
-			iddig = property_enabled(base, &port_cfg->utmi_iddig);
415
-			if (!iddig)
416
-				vbus = rphy->vbus_supply[USB2PHY_PORT_OTG];
417
-		}
418
-	}
419
-
420
-	return vbus;
421406 }
422407 
423408 static int rockchip_usb2phy_reset(struct rockchip_usb2phy *rphy)
....@@ -492,10 +477,11 @@
492477 
493478 static int rockchip_usb2phy_power_on(struct phy *phy)
494479 {
495
-	struct udevice *vbus = NULL;
480
+	struct udevice *parent = phy->dev->parent;
481
+	struct rockchip_usb2phy *rphy = dev_get_priv(parent);
482
+	struct udevice *vbus = rphy->vbus_supply[phy->id];
496483 	int ret;
497484 
498
-	vbus = rockchip_usb2phy_check_vbus(phy);
499485 	if (vbus) {
500486 		ret = regulator_set_enable(vbus, true);
501487 		if (ret) {
....@@ -509,10 +495,11 @@
509495 
510496 static int rockchip_usb2phy_power_off(struct phy *phy)
511497 {
512
-	struct udevice *vbus = NULL;
498
+	struct udevice *parent = phy->dev->parent;
499
+	struct rockchip_usb2phy *rphy = dev_get_priv(parent);
500
+	struct udevice *vbus = rphy->vbus_supply[phy->id];
513501 	int ret;
514502 
515
-	vbus = rockchip_usb2phy_check_vbus(phy);
516503 	if (vbus) {
517504 		ret = regulator_set_enable(vbus, false);
518505 		if (ret) {
....@@ -587,6 +574,11 @@
587574 	struct resource res;
588575 	u32 reg, index;
589576 	int ret;
577
+
578
+	rphy->phy_base = (void __iomem *)dev_read_addr(dev);
579
+	if (IS_ERR(rphy->phy_base)) {
580
+		dev_err(dev, "get the base address of usb phy failed\n");
581
+	}
590582 
591583 	if (!strncmp(parent->name, "root_driver", 11) &&
592584 	    dev_read_bool(dev, "rockchip,grf")) {
....@@ -818,6 +810,102 @@
818810 	return 0;
819811 }
820812 
813
+static int rv1106_usb2phy_tuning(struct rockchip_usb2phy *rphy)
814
+{
815
+	u32 reg;
816
+
817
+	/* Set HS disconnect detect mode to single ended detect mode */
818
+	reg = readl(rphy->phy_base + 0x70);
819
+	writel(reg | BIT(2), rphy->phy_base + 0x70);
820
+
821
+	return 0;
822
+}
823
+
824
+static int rk3528_usb2phy_tuning(struct rockchip_usb2phy *rphy)
825
+{
826
+	u32 reg;
827
+	int ret = 0;
828
+
829
+	if (IS_ERR(rphy->phy_base)) {
830
+		return PTR_ERR(rphy->phy_base);
831
+	}
832
+
833
+	/* Turn off otg port differential receiver in suspend mode */
834
+	reg = readl(rphy->phy_base + 0x30);
835
+	writel(reg & ~BIT(2), rphy->phy_base + 0x30);
836
+
837
+	/* Turn off host port differential receiver in suspend mode */
838
+	reg = readl(rphy->phy_base + 0x0430);
839
+	writel(reg & ~BIT(2), rphy->phy_base + 0x0430);
840
+
841
+	/* Set otg port HS eye height to 400mv(default is 450mv) */
842
+	reg = readl(rphy->phy_base + 0x30);
843
+	reg &= ~GENMASK(6, 4);
844
+	reg |= (0x00 << 4);
845
+	writel(reg, rphy->phy_base + 0x30);
846
+
847
+	/* Set host port HS eye height to 400mv(default is 450mv) */
848
+	reg = readl(rphy->phy_base + 0x430);
849
+	reg &= ~GENMASK(6, 4);
850
+	reg |= (0x00 << 4);
851
+	writel(reg, rphy->phy_base + 0x430);
852
+
853
+	/* Choose the Tx fs/ls data as linestate from TX driver for otg port */
854
+	reg = readl(rphy->phy_base + 0x94);
855
+	reg &= ~GENMASK(6, 3);
856
+	reg |= (0x03 << 3);
857
+	writel(reg, rphy->phy_base + 0x94);
858
+
859
+	/* Turn on output clk of phy*/
860
+	reg = readl(rphy->phy_base + 0x41c);
861
+	reg &= ~GENMASK(7, 2);
862
+	reg |= (0x27 << 2);
863
+	writel(reg, rphy->phy_base + 0x41c);
864
+
865
+	return ret;
866
+}
867
+
868
+static int rk3562_usb2phy_tuning(struct rockchip_usb2phy *rphy)
869
+{
870
+	u32 reg;
871
+	int ret = 0;
872
+
873
+	if (IS_ERR(rphy->phy_base)) {
874
+		return PTR_ERR(rphy->phy_base);
875
+	}
876
+
877
+	/* Turn off differential receiver by default to save power */
878
+	reg = readl(rphy->phy_base + 0x30);
879
+	writel(reg & ~BIT(2), rphy->phy_base + 0x30);
880
+
881
+	reg = readl(rphy->phy_base + 0x0430);
882
+	writel(reg & ~BIT(2), rphy->phy_base + 0x0430);
883
+
884
+	/* Enable pre-emphasis during non-chirp phase */
885
+	reg = readl(rphy->phy_base);
886
+	reg &= ~GENMASK(2, 0);
887
+	reg |= 0x04;
888
+	writel(reg, rphy->phy_base);
889
+
890
+	reg = readl(rphy->phy_base + 0x0400);
891
+	reg &= ~GENMASK(2, 0);
892
+	reg |= 0x04;
893
+	writel(reg, rphy->phy_base + 0x0400);
894
+
895
+	/* Set HS eye height to 425mv(default is 400mv) */
896
+	reg = readl(rphy->phy_base + 0x0030);
897
+	reg &= ~GENMASK(6, 4);
898
+	reg |= (0x05 << 4);
899
+	writel(reg, rphy->phy_base + 0x0030);
900
+
901
+	reg = readl(rphy->phy_base + 0x0430);
902
+	reg &= ~GENMASK(6, 4);
903
+	reg |= (0x05 << 4);
904
+	writel(reg, rphy->phy_base + 0x0430);
905
+
906
+	return ret;
907
+}
908
+
821909 static int rk3588_usb2phy_tuning(struct rockchip_usb2phy *rphy)
822910 {
823911 	struct regmap *base = get_reg_base(rphy);
....@@ -902,6 +990,43 @@
902990 			.rdm_pdwn_en	= { 0x0108, 10, 10, 0, 1 },
903991 			.vdm_src_en	= { 0x0108, 12, 12, 0, 1 },
904992 			.vdp_src_en	= { 0x0108, 11, 11, 0, 1 },
993
+		},
994
+	},
995
+	{ /* sentinel */ }
996
+};
997
+
998
+static const struct rockchip_usb2phy_cfg rk3036_phy_cfgs[] = {
999
+	{
1000
+		.reg = 0x17c,
1001
+		.num_ports	= 2,
1002
+		.clkout_ctl	= { 0x017c, 11, 11, 1, 0 },
1003
+		.port_cfgs	= {
1004
+			[USB2PHY_PORT_OTG] = {
1005
+				.phy_sus	= { 0x017c, 8, 0, 0, 0x1d1 },
1006
+				.bvalid_det_en	= { 0x017c, 14, 14, 0, 1 },
1007
+				.bvalid_det_st	= { 0x017c, 15, 15, 0, 1 },
1008
+				.bvalid_det_clr	= { 0x017c, 15, 15, 0, 1 },
1009
+				.iddig_output	= { 0x017c, 10, 10, 0, 1 },
1010
+				.iddig_en	= { 0x017c, 9, 9, 0, 1 },
1011
+				.idfall_det_en  = { 0x01a0, 2, 2, 0, 1 },
1012
+				.idfall_det_st  = { 0x01a0, 3, 3, 0, 1 },
1013
+				.idfall_det_clr = { 0x01a0, 3, 3, 0, 1 },
1014
+				.idrise_det_en  = { 0x01a0, 0, 0, 0, 1 },
1015
+				.idrise_det_st  = { 0x01a0, 1, 1, 0, 1 },
1016
+				.idrise_det_clr = { 0x01a0, 1, 1, 0, 1 },
1017
+				.ls_det_en	= { 0x017c, 12, 12, 0, 1 },
1018
+				.ls_det_st	= { 0x017c, 13, 13, 0, 1 },
1019
+				.ls_det_clr	= { 0x017c, 13, 13, 0, 1 },
1020
+				.utmi_bvalid	= { 0x014c, 5, 5, 0, 1 },
1021
+				.utmi_iddig	= { 0x014c, 8, 8, 0, 1 },
1022
+				.utmi_ls	= { 0x014c, 7, 6, 0, 1 },
1023
+			},
1024
+			[USB2PHY_PORT_HOST] = {
1025
+				.phy_sus	= { 0x0194, 8, 0, 0, 0x1d1 },
1026
+				.ls_det_en	= { 0x0194, 14, 14, 0, 1 },
1027
+				.ls_det_st	= { 0x0194, 15, 15, 0, 1 },
1028
+				.ls_det_clr	= { 0x0194, 15, 15, 0, 1 }
1029
+			}
9051030 		},
9061031 	},
9071032 	{ /* sentinel */ }
....@@ -1272,6 +1397,51 @@
12721397 	{ /* sentinel */ }
12731398 };
12741399 
1400
+static const struct rockchip_usb2phy_cfg rv1106_phy_cfgs[] = {
1401
+	{
1402
+		.reg = 0xff3e0000,
1403
+		.num_ports	= 1,
1404
+		.phy_tuning	= rv1106_usb2phy_tuning,
1405
+		.clkout_ctl	= { 0x0058, 4, 4, 1, 0 },
1406
+		.port_cfgs	= {
1407
+			[USB2PHY_PORT_OTG] = {
1408
+				.phy_sus	= { 0x0050, 8, 0, 0, 0x1d1 },
1409
+				.bvalid_det_en	= { 0x0100, 2, 2, 0, 1 },
1410
+				.bvalid_det_st	= { 0x0104, 2, 2, 0, 1 },
1411
+				.bvalid_det_clr = { 0x0108, 2, 2, 0, 1 },
1412
+				.iddig_output	= { 0x0050, 10, 10, 0, 1 },
1413
+				.iddig_en	= { 0x0050, 9, 9, 0, 1 },
1414
+				.idfall_det_en	= { 0x0100, 5, 5, 0, 1 },
1415
+				.idfall_det_st	= { 0x0104, 5, 5, 0, 1 },
1416
+				.idfall_det_clr = { 0x0108, 5, 5, 0, 1 },
1417
+				.idrise_det_en	= { 0x0100, 4, 4, 0, 1 },
1418
+				.idrise_det_st	= { 0x0104, 4, 4, 0, 1 },
1419
+				.idrise_det_clr = { 0x0108, 4, 4, 0, 1 },
1420
+				.ls_det_en	= { 0x0100, 0, 0, 0, 1 },
1421
+				.ls_det_st	= { 0x0104, 0, 0, 0, 1 },
1422
+				.ls_det_clr	= { 0x0108, 0, 0, 0, 1 },
1423
+				.utmi_avalid	= { 0x0060, 10, 10, 0, 1 },
1424
+				.utmi_bvalid	= { 0x0060, 9, 9, 0, 1 },
1425
+				.utmi_iddig	= { 0x0060, 6, 6, 0, 1 },
1426
+				.utmi_ls	= { 0x0060, 5, 4, 0, 1 },
1427
+			},
1428
+		},
1429
+		.chg_det = {
1430
+			.opmode	= { 0x0050, 3, 0, 5, 1 },
1431
+			.cp_det		= { 0x0060, 13, 13, 0, 1 },
1432
+			.dcp_det	= { 0x0060, 12, 12, 0, 1 },
1433
+			.dp_det		= { 0x0060, 14, 14, 0, 1 },
1434
+			.idm_sink_en	= { 0x0058, 8, 8, 0, 1 },
1435
+			.idp_sink_en	= { 0x0058, 7, 7, 0, 1 },
1436
+			.idp_src_en	= { 0x0058, 9, 9, 0, 1 },
1437
+			.rdm_pdwn_en	= { 0x0058, 10, 10, 0, 1 },
1438
+			.vdm_src_en	= { 0x0058, 12, 12, 0, 1 },
1439
+			.vdp_src_en	= { 0x0058, 11, 11, 0, 1 },
1440
+		},
1441
+	},
1442
+	{ /* sentinel */ }
1443
+};
1444
+
12751445 static const struct rockchip_usb2phy_cfg rv1108_phy_cfgs[] = {
12761446 	{
12771447 		.reg = 0x100,
....@@ -1309,6 +1479,110 @@
13091479 			.rdm_pdwn_en	= { 0x0ffa0108, 10, 10, 0, 1 },
13101480 			.vdm_src_en	= { 0x0ffa0108, 12, 12, 0, 1 },
13111481 			.vdp_src_en	= { 0x0ffa0108, 11, 11, 0, 1 },
1482
+		},
1483
+	},
1484
+	{ /* sentinel */ }
1485
+};
1486
+
1487
+static const struct rockchip_usb2phy_cfg rk3528_phy_cfgs[] = {
1488
+	{
1489
+		.reg = 0xffdf0000,
1490
+		.num_ports	= 2,
1491
+		.phy_tuning	= rk3528_usb2phy_tuning,
1492
+		.port_cfgs	= {
1493
+			[USB2PHY_PORT_OTG] = {
1494
+				.phy_sus	= { 0x6004c, 8, 0, 0, 0x1d1 },
1495
+				.bvalid_det_en	= { 0x60074, 2, 2, 0, 1 },
1496
+				.bvalid_det_st	= { 0x60078, 2, 2, 0, 1 },
1497
+				.bvalid_det_clr = { 0x6007c, 2, 2, 0, 1 },
1498
+				.iddig_output	= { 0x6004c, 10, 10, 0, 1 },
1499
+				.iddig_en	= { 0x6004c, 9, 9, 0, 1 },
1500
+				.idfall_det_en	= { 0x60074, 5, 5, 0, 1 },
1501
+				.idfall_det_st	= { 0x60078, 5, 5, 0, 1 },
1502
+				.idfall_det_clr = { 0x6007c, 5, 5, 0, 1 },
1503
+				.idrise_det_en	= { 0x60074, 4, 4, 0, 1 },
1504
+				.idrise_det_st	= { 0x60078, 4, 4, 0, 1 },
1505
+				.idrise_det_clr = { 0x6007c, 4, 4, 0, 1 },
1506
+				.ls_det_en	= { 0x60074, 0, 0, 0, 1 },
1507
+				.ls_det_st	= { 0x60078, 0, 0, 0, 1 },
1508
+				.ls_det_clr	= { 0x6007c, 0, 0, 0, 1 },
1509
+				.utmi_avalid	= { 0x6006c, 1, 1, 0, 1 },
1510
+				.utmi_bvalid	= { 0x6006c, 0, 0, 0, 1 },
1511
+				.utmi_iddig	= { 0x6006c, 6, 6, 0, 1 },
1512
+				.utmi_ls	= { 0x6006c, 5, 4, 0, 1 },
1513
+			},
1514
+			[USB2PHY_PORT_HOST] = {
1515
+				.phy_sus	= { 0x6005c, 8, 0, 0x1d2, 0x1d1 },
1516
+				.ls_det_en	= { 0x60090, 0, 0, 0, 1 },
1517
+				.ls_det_st	= { 0x60094, 0, 0, 0, 1 },
1518
+				.ls_det_clr	= { 0x60098, 0, 0, 0, 1 },
1519
+				.utmi_ls	= { 0x6006c, 13, 12, 0, 1 },
1520
+				.utmi_hstdet	= { 0x6006c, 15, 15, 0, 1 }
1521
+			}
1522
+		},
1523
+		.chg_det = {
1524
+			.opmode		= { 0x6004c, 3, 0, 5, 1 },
1525
+			.cp_det		= { 0x6006c, 19, 19, 0, 1 },
1526
+			.dcp_det	= { 0x6006c, 18, 18, 0, 1 },
1527
+			.dp_det		= { 0x6006c, 20, 20, 0, 1 },
1528
+			.idm_sink_en	= { 0x60058, 1, 1, 0, 1 },
1529
+			.idp_sink_en	= { 0x60058, 0, 0, 0, 1 },
1530
+			.idp_src_en	= { 0x60058, 2, 2, 0, 1 },
1531
+			.rdm_pdwn_en	= { 0x60058, 3, 3, 0, 1 },
1532
+			.vdm_src_en	= { 0x60058, 5, 5, 0, 1 },
1533
+			.vdp_src_en	= { 0x60058, 4, 4, 0, 1 },
1534
+		},
1535
+	}
1536
+};
1537
+
1538
+static const struct rockchip_usb2phy_cfg rk3562_phy_cfgs[] = {
1539
+	{
1540
+		.reg = 0xff740000,
1541
+		.num_ports	= 2,
1542
+		.phy_tuning	= rk3562_usb2phy_tuning,
1543
+		.clkout_ctl	= { 0x0108, 4, 4, 1, 0 },
1544
+		.port_cfgs	= {
1545
+			[USB2PHY_PORT_OTG] = {
1546
+				.phy_sus	= { 0x0100, 8, 0, 0, 0x1d1 },
1547
+				.bvalid_det_en	= { 0x0110, 2, 2, 0, 1 },
1548
+				.bvalid_det_st	= { 0x0114, 2, 2, 0, 1 },
1549
+				.bvalid_det_clr = { 0x0118, 2, 2, 0, 1 },
1550
+				.iddig_output	= { 0x0100, 10, 10, 0, 1 },
1551
+				.iddig_en	= { 0x0100, 9, 9, 0, 1 },
1552
+				.idfall_det_en	= { 0x0110, 5, 5, 0, 1 },
1553
+				.idfall_det_st	= { 0x0114, 5, 5, 0, 1 },
1554
+				.idfall_det_clr = { 0x0118, 5, 5, 0, 1 },
1555
+				.idrise_det_en	= { 0x0110, 4, 4, 0, 1 },
1556
+				.idrise_det_st	= { 0x0114, 4, 4, 0, 1 },
1557
+				.idrise_det_clr = { 0x0118, 4, 4, 0, 1 },
1558
+				.ls_det_en	= { 0x0110, 0, 0, 0, 1 },
1559
+				.ls_det_st	= { 0x0114, 0, 0, 0, 1 },
1560
+				.ls_det_clr	= { 0x0118, 0, 0, 0, 1 },
1561
+				.utmi_avalid	= { 0x0120, 10, 10, 0, 1 },
1562
+				.utmi_bvalid	= { 0x0120, 9, 9, 0, 1 },
1563
+				.utmi_iddig	= { 0x0120, 6, 6, 0, 1 },
1564
+				.utmi_ls	= { 0x0120, 5, 4, 0, 1 },
1565
+			},
1566
+			[USB2PHY_PORT_HOST] = {
1567
+				.phy_sus	= { 0x0104, 8, 0, 0x1d2, 0x1d1 },
1568
+				.ls_det_en	= { 0x0110, 1, 1, 0, 1 },
1569
+				.ls_det_st	= { 0x0114, 1, 1, 0, 1 },
1570
+				.ls_det_clr	= { 0x0118, 1, 1, 0, 1 },
1571
+				.utmi_ls	= { 0x0120, 17, 16, 0, 1 },
1572
+				.utmi_hstdet	= { 0x0120, 19, 19, 0, 1 }
1573
+			}
1574
+		},
1575
+		.chg_det = {
1576
+			.opmode		= { 0x0100, 3, 0, 5, 1 },
1577
+			.cp_det		= { 0x0120, 24, 24, 0, 1 },
1578
+			.dcp_det	= { 0x0120, 23, 23, 0, 1 },
1579
+			.dp_det		= { 0x0120, 25, 25, 0, 1 },
1580
+			.idm_sink_en	= { 0x0108, 8, 8, 0, 1 },
1581
+			.idp_sink_en	= { 0x0108, 7, 7, 0, 1 },
1582
+			.idp_src_en	= { 0x0108, 9, 9, 0, 1 },
1583
+			.rdm_pdwn_en	= { 0x0108, 10, 10, 0, 1 },
1584
+			.vdm_src_en	= { 0x0108, 12, 12, 0, 1 },
1585
+			.vdp_src_en	= { 0x0108, 11, 11, 0, 1 },
13121586 		},
13131587 	},
13141588 	{ /* sentinel */ }
....@@ -1401,6 +1675,8 @@
14011675 				.ls_det_en	= { 0x0080, 0, 0, 0, 1 },
14021676 				.ls_det_st	= { 0x0084, 0, 0, 0, 1 },
14031677 				.ls_det_clr	= { 0x0088, 0, 0, 0, 1 },
1678
+				.utmi_avalid	= { 0x00c0, 7, 7, 0, 1 },
1679
+				.utmi_bvalid	= { 0x00c0, 6, 6, 0, 1 },
14041680 				.utmi_iddig	= { 0x00c0, 5, 5, 0, 1 },
14051681 				.utmi_ls	= { 0x00c0, 10, 9, 0, 1 },
14061682 			}
....@@ -1468,16 +1744,48 @@
14681744 };
14691745 
14701746 static const struct udevice_id rockchip_usb2phy_ids[] = {
1747
+#ifdef CONFIG_ROCKCHIP_RK1808
14711748 	{ .compatible = "rockchip,rk1808-usb2phy", .data = (ulong)&rk1808_phy_cfgs },
1749
+#endif
1750
+#ifdef CONFIG_ROCKCHIP_RK3036
1751
+	{ .compatible = "rockchip,rk3036-usb2phy", .data = (ulong)&rk3036_phy_cfgs },
1752
+#endif
1753
+#if defined CONFIG_ROCKCHIP_RK3128 || defined CONFIG_ROCKCHIP_RK3126
14721754 	{ .compatible = "rockchip,rk3128-usb2phy", .data = (ulong)&rk312x_phy_cfgs },
1755
+#endif
1756
+#ifdef CONFIG_ROCKCHIP_RK322X
14731757 	{ .compatible = "rockchip,rk322x-usb2phy", .data = (ulong)&rk322x_phy_cfgs },
1758
+#endif
1759
+#ifdef CONFIG_ROCKCHIP_RK3308
14741760 	{ .compatible = "rockchip,rk3308-usb2phy", .data = (ulong)&rk3308_phy_cfgs },
1761
+#endif
1762
+#if defined CONFIG_ROCKCHIP_RK3328 || defined CONFIG_ROCKCHIP_PX30
14751763 	{ .compatible = "rockchip,rk3328-usb2phy", .data = (ulong)&rk3328_phy_cfgs },
1764
+#endif
1765
+#ifdef CONFIG_ROCKCHIP_RK3368
14761766 	{ .compatible = "rockchip,rk3368-usb2phy", .data = (ulong)&rk3368_phy_cfgs },
1767
+#endif
1768
+#ifdef CONFIG_ROCKCHIP_RK3399
14771769 	{ .compatible = "rockchip,rk3399-usb2phy", .data = (ulong)&rk3399_phy_cfgs },
1770
+#endif
1771
+#ifdef CONFIG_ROCKCHIP_RK3528
1772
+	{ .compatible = "rockchip,rk3528-usb2phy", .data = (ulong)&rk3528_phy_cfgs },
1773
+#endif
1774
+#ifdef CONFIG_ROCKCHIP_RK3562
1775
+	{ .compatible = "rockchip,rk3562-usb2phy", .data = (ulong)&rk3562_phy_cfgs },
1776
+#endif
1777
+#ifdef CONFIG_ROCKCHIP_RK3568
14781778 	{ .compatible = "rockchip,rk3568-usb2phy", .data = (ulong)&rk3568_phy_cfgs },
1779
+#endif
1780
+#ifdef CONFIG_ROCKCHIP_RK3588
14791781 	{ .compatible = "rockchip,rk3588-usb2phy", .data = (ulong)&rk3588_phy_cfgs },
1782
+#endif
1783
+#ifdef CONFIG_ROCKCHIP_RV1106
1784
+	{ .compatible = "rockchip,rv1106-usb2phy", .data = (ulong)&rv1106_phy_cfgs },
1785
+#endif
1786
+#ifdef CONFIG_ROCKCHIP_RV1108
14801787 	{ .compatible = "rockchip,rv1108-usb2phy", .data = (ulong)&rv1108_phy_cfgs },
1788
+#endif
14811789 	{ }
14821790 };
14831791