~hc/RK356X_SDK_RELEASE.git

..	..	@@ -311,7 +311,7 @@
311	311	},
312	312	{
313	313	"PEBS": "2",
314		- "PublicDescription": "This event counts loads with latency value being above four.",
	314	+ "PublicDescription": "Counts randomly selected loads with latency value being above four.",
315	315	"EventCode": "0xCD",
316	316	"MSRValue": "0x4",
317	317	"Counter": "3",
..	..	@@ -320,13 +320,13 @@
320	320	"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
321	321	"MSRIndex": "0x3F6",
322	322	"SampleAfterValue": "100003",
323		- "BriefDescription": "Loads with latency value being above 4",
	323	+ "BriefDescription": "Randomly selected loads with latency value being above 4",
324	324	"TakenAlone": "1",
325	325	"CounterHTOff": "3"
326	326	},
327	327	{
328	328	"PEBS": "2",
329		- "PublicDescription": "This event counts loads with latency value being above eight.",
	329	+ "PublicDescription": "Counts randomly selected loads with latency value being above eight.",
330	330	"EventCode": "0xCD",
331	331	"MSRValue": "0x8",
332	332	"Counter": "3",
..	..	@@ -335,13 +335,13 @@
335	335	"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
336	336	"MSRIndex": "0x3F6",
337	337	"SampleAfterValue": "50021",
338		- "BriefDescription": "Loads with latency value being above 8",
	338	+ "BriefDescription": "Randomly selected loads with latency value being above 8",
339	339	"TakenAlone": "1",
340	340	"CounterHTOff": "3"
341	341	},
342	342	{
343	343	"PEBS": "2",
344		- "PublicDescription": "This event counts loads with latency value being above 16.",
	344	+ "PublicDescription": "Counts randomly selected loads with latency value being above 16.",
345	345	"EventCode": "0xCD",
346	346	"MSRValue": "0x10",
347	347	"Counter": "3",
..	..	@@ -350,13 +350,13 @@
350	350	"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
351	351	"MSRIndex": "0x3F6",
352	352	"SampleAfterValue": "20011",
353		- "BriefDescription": "Loads with latency value being above 16",
	353	+ "BriefDescription": "Randomly selected loads with latency value being above 16",
354	354	"TakenAlone": "1",
355	355	"CounterHTOff": "3"
356	356	},
357	357	{
358	358	"PEBS": "2",
359		- "PublicDescription": "This event counts loads with latency value being above 32.",
	359	+ "PublicDescription": "Counts randomly selected loads with latency value being above 32.",
360	360	"EventCode": "0xCD",
361	361	"MSRValue": "0x20",
362	362	"Counter": "3",
..	..	@@ -365,13 +365,13 @@
365	365	"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
366	366	"MSRIndex": "0x3F6",
367	367	"SampleAfterValue": "100007",
368		- "BriefDescription": "Loads with latency value being above 32",
	368	+ "BriefDescription": "Randomly selected loads with latency value being above 32",
369	369	"TakenAlone": "1",
370	370	"CounterHTOff": "3"
371	371	},
372	372	{
373	373	"PEBS": "2",
374		- "PublicDescription": "This event counts loads with latency value being above 64.",
	374	+ "PublicDescription": "Counts randomly selected loads with latency value being above 64.",
375	375	"EventCode": "0xCD",
376	376	"MSRValue": "0x40",
377	377	"Counter": "3",
..	..	@@ -380,13 +380,13 @@
380	380	"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
381	381	"MSRIndex": "0x3F6",
382	382	"SampleAfterValue": "2003",
383		- "BriefDescription": "Loads with latency value being above 64",
	383	+ "BriefDescription": "Randomly selected loads with latency value being above 64",
384	384	"TakenAlone": "1",
385	385	"CounterHTOff": "3"
386	386	},
387	387	{
388	388	"PEBS": "2",
389		- "PublicDescription": "This event counts loads with latency value being above 128.",
	389	+ "PublicDescription": "Counts randomly selected loads with latency value being above 128.",
390	390	"EventCode": "0xCD",
391	391	"MSRValue": "0x80",
392	392	"Counter": "3",
..	..	@@ -395,13 +395,13 @@
395	395	"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
396	396	"MSRIndex": "0x3F6",
397	397	"SampleAfterValue": "1009",
398		- "BriefDescription": "Loads with latency value being above 128",
	398	+ "BriefDescription": "Randomly selected loads with latency value being above 128",
399	399	"TakenAlone": "1",
400	400	"CounterHTOff": "3"
401	401	},
402	402	{
403	403	"PEBS": "2",
404		- "PublicDescription": "This event counts loads with latency value being above 256.",
	404	+ "PublicDescription": "Counts randomly selected loads with latency value being above 256.",
405	405	"EventCode": "0xCD",
406	406	"MSRValue": "0x100",
407	407	"Counter": "3",
..	..	@@ -410,13 +410,13 @@
410	410	"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
411	411	"MSRIndex": "0x3F6",
412	412	"SampleAfterValue": "503",
413		- "BriefDescription": "Loads with latency value being above 256",
	413	+ "BriefDescription": "Randomly selected loads with latency value being above 256",
414	414	"TakenAlone": "1",
415	415	"CounterHTOff": "3"
416	416	},
417	417	{
418	418	"PEBS": "2",
419		- "PublicDescription": "This event counts loads with latency value being above 512.",
	419	+ "PublicDescription": "Counts randomly selected loads with latency value being above 512.",
420	420	"EventCode": "0xCD",
421	421	"MSRValue": "0x200",
422	422	"Counter": "3",
..	..	@@ -425,2620 +425,2620 @@
425	425	"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
426	426	"MSRIndex": "0x3F6",
427	427	"SampleAfterValue": "101",
428		- "BriefDescription": "Loads with latency value being above 512",
	428	+ "BriefDescription": "Randomly selected loads with latency value being above 512",
429	429	"TakenAlone": "1",
430	430	"CounterHTOff": "3"
431	431	},
432	432	{
433		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	433	+ "PublicDescription": "Counts demand data reads",
434	434	"EventCode": "0xB7, 0xBB",
435		- "MSRValue": "0x2000020001 ",
	435	+ "MSRValue": "0x2000020001",
436	436	"Counter": "0,1,2,3",
437	437	"UMask": "0x1",
438	438	"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NON_DRAM",
439		- "MSRIndex": "0x1a6,0x1a7",
	439	+ "MSRIndex": "0x1a6, 0x1a7",
440	440	"SampleAfterValue": "100003",
441		- "BriefDescription": "DEMAND_DATA_RD & SUPPLIER_NONE & SNOOP_NON_DRAM",
	441	+ "BriefDescription": "Counts demand data reads",
442	442	"Offcore": "1",
443	443	"CounterHTOff": "0,1,2,3"
444	444	},
445	445	{
446		- "PublicDescription": "Counts demand data reads that hit in the L3 and the target was non-DRAM system address. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	446	+ "PublicDescription": "Counts demand data reads",
447	447	"EventCode": "0xB7, 0xBB",
448		- "MSRValue": "0x20003c0001 ",
	448	+ "MSRValue": "0x20003C0001",
449	449	"Counter": "0,1,2,3",
450	450	"UMask": "0x1",
451	451	"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_NON_DRAM",
452		- "MSRIndex": "0x1a6,0x1a7",
	452	+ "MSRIndex": "0x1a6, 0x1a7",
453	453	"SampleAfterValue": "100003",
454		- "BriefDescription": "Counts demand data reads that hit in the L3 and the target was non-DRAM system address.",
	454	+ "BriefDescription": "Counts demand data reads",
455	455	"Offcore": "1",
456	456	"CounterHTOff": "0,1,2,3"
457	457	},
458	458	{
459		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	459	+ "PublicDescription": "Counts demand data reads",
460	460	"EventCode": "0xB7, 0xBB",
461		- "MSRValue": "0x0084000001 ",
	461	+ "MSRValue": "0x0084000001",
462	462	"Counter": "0,1,2,3",
463	463	"UMask": "0x1",
464	464	"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
465		- "MSRIndex": "0x1a6,0x1a7",
	465	+ "MSRIndex": "0x1a6, 0x1a7",
466	466	"SampleAfterValue": "100003",
467		- "BriefDescription": "DEMAND_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_NONE",
	467	+ "BriefDescription": "Counts demand data reads",
468	468	"Offcore": "1",
469	469	"CounterHTOff": "0,1,2,3"
470	470	},
471	471	{
472		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	472	+ "PublicDescription": "Counts demand data reads",
473	473	"EventCode": "0xB7, 0xBB",
474		- "MSRValue": "0x0104000001 ",
	474	+ "MSRValue": "0x0104000001",
475	475	"Counter": "0,1,2,3",
476	476	"UMask": "0x1",
477	477	"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",
478		- "MSRIndex": "0x1a6,0x1a7",
	478	+ "MSRIndex": "0x1a6, 0x1a7",
479	479	"SampleAfterValue": "100003",
480		- "BriefDescription": "DEMAND_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_NOT_NEEDED",
	480	+ "BriefDescription": "Counts demand data reads",
481	481	"Offcore": "1",
482	482	"CounterHTOff": "0,1,2,3"
483	483	},
484	484	{
485		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	485	+ "PublicDescription": "Counts demand data reads",
486	486	"EventCode": "0xB7, 0xBB",
487		- "MSRValue": "0x0204000001 ",
	487	+ "MSRValue": "0x0204000001",
488	488	"Counter": "0,1,2,3",
489	489	"UMask": "0x1",
490	490	"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
491		- "MSRIndex": "0x1a6,0x1a7",
	491	+ "MSRIndex": "0x1a6, 0x1a7",
492	492	"SampleAfterValue": "100003",
493		- "BriefDescription": "DEMAND_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_MISS",
	493	+ "BriefDescription": "Counts demand data reads",
494	494	"Offcore": "1",
495	495	"CounterHTOff": "0,1,2,3"
496	496	},
497	497	{
498		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	498	+ "PublicDescription": "Counts demand data reads",
499	499	"EventCode": "0xB7, 0xBB",
500		- "MSRValue": "0x0404000001 ",
	500	+ "MSRValue": "0x0404000001",
501	501	"Counter": "0,1,2,3",
502	502	"UMask": "0x1",
503	503	"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",
504		- "MSRIndex": "0x1a6,0x1a7",
	504	+ "MSRIndex": "0x1a6, 0x1a7",
505	505	"SampleAfterValue": "100003",
506		- "BriefDescription": "DEMAND_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_HIT_NO_FWD",
	506	+ "BriefDescription": "Counts demand data reads",
507	507	"Offcore": "1",
508	508	"CounterHTOff": "0,1,2,3"
509	509	},
510	510	{
511		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	511	+ "PublicDescription": "Counts demand data reads",
512	512	"EventCode": "0xB7, 0xBB",
513		- "MSRValue": "0x1004000001 ",
	513	+ "MSRValue": "0x1004000001",
514	514	"Counter": "0,1,2,3",
515	515	"UMask": "0x1",
516	516	"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM",
517		- "MSRIndex": "0x1a6,0x1a7",
	517	+ "MSRIndex": "0x1a6, 0x1a7",
518	518	"SampleAfterValue": "100003",
519		- "BriefDescription": "DEMAND_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_HITM",
	519	+ "BriefDescription": "Counts demand data reads",
520	520	"Offcore": "1",
521	521	"CounterHTOff": "0,1,2,3"
522	522	},
523	523	{
524		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	524	+ "PublicDescription": "Counts demand data reads",
525	525	"EventCode": "0xB7, 0xBB",
526		- "MSRValue": "0x2004000001 ",
	526	+ "MSRValue": "0x2004000001",
527	527	"Counter": "0,1,2,3",
528	528	"UMask": "0x1",
529	529	"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",
530		- "MSRIndex": "0x1a6,0x1a7",
	530	+ "MSRIndex": "0x1a6, 0x1a7",
531	531	"SampleAfterValue": "100003",
532		- "BriefDescription": "DEMAND_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_NON_DRAM",
	532	+ "BriefDescription": "Counts demand data reads",
533	533	"Offcore": "1",
534	534	"CounterHTOff": "0,1,2,3"
535	535	},
536	536	{
537		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	537	+ "PublicDescription": "Counts demand data reads",
538	538	"EventCode": "0xB7, 0xBB",
539		- "MSRValue": "0x3f84000001 ",
	539	+ "MSRValue": "0x3F84000001",
540	540	"Counter": "0,1,2,3",
541	541	"UMask": "0x1",
542	542	"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
543		- "MSRIndex": "0x1a6,0x1a7",
	543	+ "MSRIndex": "0x1a6, 0x1a7",
544	544	"SampleAfterValue": "100003",
545		- "BriefDescription": "DEMAND_DATA_RD & L3_MISS_LOCAL_DRAM & ANY_SNOOP",
	545	+ "BriefDescription": "Counts demand data reads",
546	546	"Offcore": "1",
547	547	"CounterHTOff": "0,1,2,3"
548	548	},
549	549	{
550		- "PublicDescription": "Counts demand data reads that miss the L3 with no details on snoop-related information. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	550	+ "PublicDescription": "Counts demand data reads",
551	551	"EventCode": "0xB7, 0xBB",
552		- "MSRValue": "0x00bc000001 ",
	552	+ "MSRValue": "0x00BC000001",
553	553	"Counter": "0,1,2,3",
554	554	"UMask": "0x1",
555	555	"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_NONE",
556		- "MSRIndex": "0x1a6,0x1a7",
	556	+ "MSRIndex": "0x1a6, 0x1a7",
557	557	"SampleAfterValue": "100003",
558		- "BriefDescription": "Counts demand data reads that miss the L3 with no details on snoop-related information.",
	558	+ "BriefDescription": "Counts demand data reads",
559	559	"Offcore": "1",
560	560	"CounterHTOff": "0,1,2,3"
561	561	},
562	562	{
563		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	563	+ "PublicDescription": "Counts demand data reads",
564	564	"EventCode": "0xB7, 0xBB",
565		- "MSRValue": "0x013c000001 ",
	565	+ "MSRValue": "0x013C000001",
566	566	"Counter": "0,1,2,3",
567	567	"UMask": "0x1",
568	568	"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_NOT_NEEDED",
569		- "MSRIndex": "0x1a6,0x1a7",
	569	+ "MSRIndex": "0x1a6, 0x1a7",
570	570	"SampleAfterValue": "100003",
571		- "BriefDescription": "DEMAND_DATA_RD & L3_MISS & SNOOP_NOT_NEEDED",
	571	+ "BriefDescription": "Counts demand data reads",
572	572	"Offcore": "1",
573	573	"CounterHTOff": "0,1,2,3"
574	574	},
575	575	{
576		- "PublicDescription": "Counts demand data reads that miss the L3 with a snoop miss response. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	576	+ "PublicDescription": "Counts demand data reads",
577	577	"EventCode": "0xB7, 0xBB",
578		- "MSRValue": "0x023c000001 ",
	578	+ "MSRValue": "0x023C000001",
579	579	"Counter": "0,1,2,3",
580	580	"UMask": "0x1",
581	581	"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_MISS",
582		- "MSRIndex": "0x1a6,0x1a7",
	582	+ "MSRIndex": "0x1a6, 0x1a7",
583	583	"SampleAfterValue": "100003",
584		- "BriefDescription": "Counts demand data reads that miss the L3 with a snoop miss response.",
	584	+ "BriefDescription": "Counts demand data reads",
585	585	"Offcore": "1",
586	586	"CounterHTOff": "0,1,2,3"
587	587	},
588	588	{
589		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	589	+ "PublicDescription": "Counts demand data reads",
590	590	"EventCode": "0xB7, 0xBB",
591		- "MSRValue": "0x043c000001 ",
	591	+ "MSRValue": "0x043C000001",
592	592	"Counter": "0,1,2,3",
593	593	"UMask": "0x1",
594	594	"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_HIT_NO_FWD",
595		- "MSRIndex": "0x1a6,0x1a7",
	595	+ "MSRIndex": "0x1a6, 0x1a7",
596	596	"SampleAfterValue": "100003",
597		- "BriefDescription": "DEMAND_DATA_RD & L3_MISS & SNOOP_HIT_NO_FWD",
	597	+ "BriefDescription": "Counts demand data reads",
598	598	"Offcore": "1",
599	599	"CounterHTOff": "0,1,2,3"
600	600	},
601	601	{
602		- "PublicDescription": "Counts all demand data writes (RFOs) that hit in the L3 and the target was non-DRAM system address. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	602	+ "PublicDescription": "Counts all demand data writes (RFOs)",
603	603	"EventCode": "0xB7, 0xBB",
604		- "MSRValue": "0x20003c0002 ",
	604	+ "MSRValue": "0x20003C0002",
605	605	"Counter": "0,1,2,3",
606	606	"UMask": "0x1",
607	607	"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_NON_DRAM",
608		- "MSRIndex": "0x1a6,0x1a7",
	608	+ "MSRIndex": "0x1a6, 0x1a7",
609	609	"SampleAfterValue": "100003",
610		- "BriefDescription": "Counts all demand data writes (RFOs) that hit in the L3 and the target was non-DRAM system address.",
	610	+ "BriefDescription": "Counts all demand data writes (RFOs)",
611	611	"Offcore": "1",
612	612	"CounterHTOff": "0,1,2,3"
613	613	},
614	614	{
615		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	615	+ "PublicDescription": "Counts all demand data writes (RFOs)",
616	616	"EventCode": "0xB7, 0xBB",
617		- "MSRValue": "0x3f84000002 ",
	617	+ "MSRValue": "0x3F84000002",
618	618	"Counter": "0,1,2,3",
619	619	"UMask": "0x1",
620	620	"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
621		- "MSRIndex": "0x1a6,0x1a7",
	621	+ "MSRIndex": "0x1a6, 0x1a7",
622	622	"SampleAfterValue": "100003",
623		- "BriefDescription": "DEMAND_RFO & L3_MISS_LOCAL_DRAM & ANY_SNOOP",
	623	+ "BriefDescription": "Counts all demand data writes (RFOs)",
624	624	"Offcore": "1",
625	625	"CounterHTOff": "0,1,2,3"
626	626	},
627	627	{
628		- "PublicDescription": "Counts all demand data writes (RFOs) that miss the L3 with no details on snoop-related information. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	628	+ "PublicDescription": "Counts all demand data writes (RFOs)",
629	629	"EventCode": "0xB7, 0xBB",
630		- "MSRValue": "0x00bc000002 ",
	630	+ "MSRValue": "0x00BC000002",
631	631	"Counter": "0,1,2,3",
632	632	"UMask": "0x1",
633	633	"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_NONE",
634		- "MSRIndex": "0x1a6,0x1a7",
	634	+ "MSRIndex": "0x1a6, 0x1a7",
635	635	"SampleAfterValue": "100003",
636		- "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 with no details on snoop-related information.",
	636	+ "BriefDescription": "Counts all demand data writes (RFOs)",
637	637	"Offcore": "1",
638	638	"CounterHTOff": "0,1,2,3"
639	639	},
640	640	{
641		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	641	+ "PublicDescription": "Counts all demand data writes (RFOs)",
642	642	"EventCode": "0xB7, 0xBB",
643		- "MSRValue": "0x013c000002 ",
	643	+ "MSRValue": "0x013C000002",
644	644	"Counter": "0,1,2,3",
645	645	"UMask": "0x1",
646	646	"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_NOT_NEEDED",
647		- "MSRIndex": "0x1a6,0x1a7",
	647	+ "MSRIndex": "0x1a6, 0x1a7",
648	648	"SampleAfterValue": "100003",
649		- "BriefDescription": "DEMAND_RFO & L3_MISS & SNOOP_NOT_NEEDED",
	649	+ "BriefDescription": "Counts all demand data writes (RFOs)",
650	650	"Offcore": "1",
651	651	"CounterHTOff": "0,1,2,3"
652	652	},
653	653	{
654		- "PublicDescription": "Counts all demand data writes (RFOs) that miss the L3 with a snoop miss response. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	654	+ "PublicDescription": "Counts all demand data writes (RFOs)",
655	655	"EventCode": "0xB7, 0xBB",
656		- "MSRValue": "0x023c000002 ",
	656	+ "MSRValue": "0x023C000002",
657	657	"Counter": "0,1,2,3",
658	658	"UMask": "0x1",
659	659	"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_MISS",
660		- "MSRIndex": "0x1a6,0x1a7",
	660	+ "MSRIndex": "0x1a6, 0x1a7",
661	661	"SampleAfterValue": "100003",
662		- "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 with a snoop miss response.",
	662	+ "BriefDescription": "Counts all demand data writes (RFOs)",
663	663	"Offcore": "1",
664	664	"CounterHTOff": "0,1,2,3"
665	665	},
666	666	{
667		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	667	+ "PublicDescription": "Counts all demand data writes (RFOs)",
668	668	"EventCode": "0xB7, 0xBB",
669		- "MSRValue": "0x043c000002 ",
	669	+ "MSRValue": "0x043C000002",
670	670	"Counter": "0,1,2,3",
671	671	"UMask": "0x1",
672	672	"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_HIT_NO_FWD",
673		- "MSRIndex": "0x1a6,0x1a7",
	673	+ "MSRIndex": "0x1a6, 0x1a7",
674	674	"SampleAfterValue": "100003",
675		- "BriefDescription": "DEMAND_RFO & L3_MISS & SNOOP_HIT_NO_FWD",
	675	+ "BriefDescription": "Counts all demand data writes (RFOs)",
676	676	"Offcore": "1",
677	677	"CounterHTOff": "0,1,2,3"
678	678	},
679	679	{
680		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	680	+ "PublicDescription": "Counts all demand code reads",
681	681	"EventCode": "0xB7, 0xBB",
682		- "MSRValue": "0x2000020004 ",
	682	+ "MSRValue": "0x2000020004",
683	683	"Counter": "0,1,2,3",
684	684	"UMask": "0x1",
685	685	"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NON_DRAM",
686		- "MSRIndex": "0x1a6,0x1a7",
	686	+ "MSRIndex": "0x1a6, 0x1a7",
687	687	"SampleAfterValue": "100003",
688		- "BriefDescription": "DEMAND_CODE_RD & SUPPLIER_NONE & SNOOP_NON_DRAM",
	688	+ "BriefDescription": "Counts all demand code reads",
689	689	"Offcore": "1",
690	690	"CounterHTOff": "0,1,2,3"
691	691	},
692	692	{
693		- "PublicDescription": "Counts all demand code reads that hit in the L3 and the target was non-DRAM system address. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	693	+ "PublicDescription": "Counts all demand code reads",
694	694	"EventCode": "0xB7, 0xBB",
695		- "MSRValue": "0x20003c0004 ",
	695	+ "MSRValue": "0x20003C0004",
696	696	"Counter": "0,1,2,3",
697	697	"UMask": "0x1",
698	698	"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_NON_DRAM",
699		- "MSRIndex": "0x1a6,0x1a7",
	699	+ "MSRIndex": "0x1a6, 0x1a7",
700	700	"SampleAfterValue": "100003",
701		- "BriefDescription": "Counts all demand code reads that hit in the L3 and the target was non-DRAM system address.",
	701	+ "BriefDescription": "Counts all demand code reads",
702	702	"Offcore": "1",
703	703	"CounterHTOff": "0,1,2,3"
704	704	},
705	705	{
706		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	706	+ "PublicDescription": "Counts all demand code reads",
707	707	"EventCode": "0xB7, 0xBB",
708		- "MSRValue": "0x0084000004 ",
	708	+ "MSRValue": "0x0084000004",
709	709	"Counter": "0,1,2,3",
710	710	"UMask": "0x1",
711	711	"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
712		- "MSRIndex": "0x1a6,0x1a7",
	712	+ "MSRIndex": "0x1a6, 0x1a7",
713	713	"SampleAfterValue": "100003",
714		- "BriefDescription": "DEMAND_CODE_RD & L3_MISS_LOCAL_DRAM & SNOOP_NONE",
	714	+ "BriefDescription": "Counts all demand code reads",
715	715	"Offcore": "1",
716	716	"CounterHTOff": "0,1,2,3"
717	717	},
718	718	{
719		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	719	+ "PublicDescription": "Counts all demand code reads",
720	720	"EventCode": "0xB7, 0xBB",
721		- "MSRValue": "0x0104000004 ",
	721	+ "MSRValue": "0x0104000004",
722	722	"Counter": "0,1,2,3",
723	723	"UMask": "0x1",
724	724	"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",
725		- "MSRIndex": "0x1a6,0x1a7",
	725	+ "MSRIndex": "0x1a6, 0x1a7",
726	726	"SampleAfterValue": "100003",
727		- "BriefDescription": "DEMAND_CODE_RD & L3_MISS_LOCAL_DRAM & SNOOP_NOT_NEEDED",
	727	+ "BriefDescription": "Counts all demand code reads",
728	728	"Offcore": "1",
729	729	"CounterHTOff": "0,1,2,3"
730	730	},
731	731	{
732		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	732	+ "PublicDescription": "Counts all demand code reads",
733	733	"EventCode": "0xB7, 0xBB",
734		- "MSRValue": "0x0204000004 ",
	734	+ "MSRValue": "0x0204000004",
735	735	"Counter": "0,1,2,3",
736	736	"UMask": "0x1",
737	737	"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
738		- "MSRIndex": "0x1a6,0x1a7",
	738	+ "MSRIndex": "0x1a6, 0x1a7",
739	739	"SampleAfterValue": "100003",
740		- "BriefDescription": "DEMAND_CODE_RD & L3_MISS_LOCAL_DRAM & SNOOP_MISS",
	740	+ "BriefDescription": "Counts all demand code reads",
741	741	"Offcore": "1",
742	742	"CounterHTOff": "0,1,2,3"
743	743	},
744	744	{
745		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	745	+ "PublicDescription": "Counts all demand code reads",
746	746	"EventCode": "0xB7, 0xBB",
747		- "MSRValue": "0x0404000004 ",
	747	+ "MSRValue": "0x0404000004",
748	748	"Counter": "0,1,2,3",
749	749	"UMask": "0x1",
750	750	"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",
751		- "MSRIndex": "0x1a6,0x1a7",
	751	+ "MSRIndex": "0x1a6, 0x1a7",
752	752	"SampleAfterValue": "100003",
753		- "BriefDescription": "DEMAND_CODE_RD & L3_MISS_LOCAL_DRAM & SNOOP_HIT_NO_FWD",
	753	+ "BriefDescription": "Counts all demand code reads",
754	754	"Offcore": "1",
755	755	"CounterHTOff": "0,1,2,3"
756	756	},
757	757	{
758		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	758	+ "PublicDescription": "Counts all demand code reads",
759	759	"EventCode": "0xB7, 0xBB",
760		- "MSRValue": "0x1004000004 ",
	760	+ "MSRValue": "0x1004000004",
761	761	"Counter": "0,1,2,3",
762	762	"UMask": "0x1",
763	763	"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM",
764		- "MSRIndex": "0x1a6,0x1a7",
	764	+ "MSRIndex": "0x1a6, 0x1a7",
765	765	"SampleAfterValue": "100003",
766		- "BriefDescription": "DEMAND_CODE_RD & L3_MISS_LOCAL_DRAM & SNOOP_HITM",
	766	+ "BriefDescription": "Counts all demand code reads",
767	767	"Offcore": "1",
768	768	"CounterHTOff": "0,1,2,3"
769	769	},
770	770	{
771		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	771	+ "PublicDescription": "Counts all demand code reads",
772	772	"EventCode": "0xB7, 0xBB",
773		- "MSRValue": "0x2004000004 ",
	773	+ "MSRValue": "0x2004000004",
774	774	"Counter": "0,1,2,3",
775	775	"UMask": "0x1",
776	776	"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",
777		- "MSRIndex": "0x1a6,0x1a7",
	777	+ "MSRIndex": "0x1a6, 0x1a7",
778	778	"SampleAfterValue": "100003",
779		- "BriefDescription": "DEMAND_CODE_RD & L3_MISS_LOCAL_DRAM & SNOOP_NON_DRAM",
	779	+ "BriefDescription": "Counts all demand code reads",
780	780	"Offcore": "1",
781	781	"CounterHTOff": "0,1,2,3"
782	782	},
783	783	{
784		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	784	+ "PublicDescription": "Counts all demand code reads",
785	785	"EventCode": "0xB7, 0xBB",
786		- "MSRValue": "0x3f84000004 ",
	786	+ "MSRValue": "0x3F84000004",
787	787	"Counter": "0,1,2,3",
788	788	"UMask": "0x1",
789	789	"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
790		- "MSRIndex": "0x1a6,0x1a7",
	790	+ "MSRIndex": "0x1a6, 0x1a7",
791	791	"SampleAfterValue": "100003",
792		- "BriefDescription": "DEMAND_CODE_RD & L3_MISS_LOCAL_DRAM & ANY_SNOOP",
	792	+ "BriefDescription": "Counts all demand code reads",
793	793	"Offcore": "1",
794	794	"CounterHTOff": "0,1,2,3"
795	795	},
796	796	{
797		- "PublicDescription": "Counts all demand code reads that miss the L3 with no details on snoop-related information. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	797	+ "PublicDescription": "Counts all demand code reads",
798	798	"EventCode": "0xB7, 0xBB",
799		- "MSRValue": "0x00bc000004 ",
	799	+ "MSRValue": "0x00BC000004",
800	800	"Counter": "0,1,2,3",
801	801	"UMask": "0x1",
802	802	"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_NONE",
803		- "MSRIndex": "0x1a6,0x1a7",
	803	+ "MSRIndex": "0x1a6, 0x1a7",
804	804	"SampleAfterValue": "100003",
805		- "BriefDescription": "Counts all demand code reads that miss the L3 with no details on snoop-related information.",
	805	+ "BriefDescription": "Counts all demand code reads",
806	806	"Offcore": "1",
807	807	"CounterHTOff": "0,1,2,3"
808	808	},
809	809	{
810		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	810	+ "PublicDescription": "Counts all demand code reads",
811	811	"EventCode": "0xB7, 0xBB",
812		- "MSRValue": "0x013c000004 ",
	812	+ "MSRValue": "0x013C000004",
813	813	"Counter": "0,1,2,3",
814	814	"UMask": "0x1",
815	815	"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_NOT_NEEDED",
816		- "MSRIndex": "0x1a6,0x1a7",
	816	+ "MSRIndex": "0x1a6, 0x1a7",
817	817	"SampleAfterValue": "100003",
818		- "BriefDescription": "DEMAND_CODE_RD & L3_MISS & SNOOP_NOT_NEEDED",
	818	+ "BriefDescription": "Counts all demand code reads",
819	819	"Offcore": "1",
820	820	"CounterHTOff": "0,1,2,3"
821	821	},
822	822	{
823		- "PublicDescription": "Counts all demand code reads that miss the L3 with a snoop miss response. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	823	+ "PublicDescription": "Counts all demand code reads",
824	824	"EventCode": "0xB7, 0xBB",
825		- "MSRValue": "0x023c000004 ",
	825	+ "MSRValue": "0x023C000004",
826	826	"Counter": "0,1,2,3",
827	827	"UMask": "0x1",
828	828	"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_MISS",
829		- "MSRIndex": "0x1a6,0x1a7",
	829	+ "MSRIndex": "0x1a6, 0x1a7",
830	830	"SampleAfterValue": "100003",
831		- "BriefDescription": "Counts all demand code reads that miss the L3 with a snoop miss response.",
	831	+ "BriefDescription": "Counts all demand code reads",
832	832	"Offcore": "1",
833	833	"CounterHTOff": "0,1,2,3"
834	834	},
835	835	{
836		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	836	+ "PublicDescription": "Counts all demand code reads",
837	837	"EventCode": "0xB7, 0xBB",
838		- "MSRValue": "0x043c000004 ",
	838	+ "MSRValue": "0x043C000004",
839	839	"Counter": "0,1,2,3",
840	840	"UMask": "0x1",
841	841	"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_HIT_NO_FWD",
842		- "MSRIndex": "0x1a6,0x1a7",
	842	+ "MSRIndex": "0x1a6, 0x1a7",
843	843	"SampleAfterValue": "100003",
844		- "BriefDescription": "DEMAND_CODE_RD & L3_MISS & SNOOP_HIT_NO_FWD",
	844	+ "BriefDescription": "Counts all demand code reads",
845	845	"Offcore": "1",
846	846	"CounterHTOff": "0,1,2,3"
847	847	},
848	848	{
849		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	849	+ "PublicDescription": "Counts writebacks (modified to exclusive)",
850	850	"EventCode": "0xB7, 0xBB",
851		- "MSRValue": "0x2000020008 ",
	851	+ "MSRValue": "0x2000020008",
852	852	"Counter": "0,1,2,3",
853	853	"UMask": "0x1",
854	854	"EventName": "OFFCORE_RESPONSE.COREWB.SUPPLIER_NONE.SNOOP_NON_DRAM",
855		- "MSRIndex": "0x1a6,0x1a7",
	855	+ "MSRIndex": "0x1a6, 0x1a7",
856	856	"SampleAfterValue": "100003",
857		- "BriefDescription": "COREWB & SUPPLIER_NONE & SNOOP_NON_DRAM",
	857	+ "BriefDescription": "Counts writebacks (modified to exclusive)",
858	858	"Offcore": "1",
859	859	"CounterHTOff": "0,1,2,3"
860	860	},
861	861	{
862		- "PublicDescription": "Counts writebacks (modified to exclusive) that hit in the L3 and the target was non-DRAM system address. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	862	+ "PublicDescription": "Counts writebacks (modified to exclusive)",
863	863	"EventCode": "0xB7, 0xBB",
864		- "MSRValue": "0x20003c0008 ",
	864	+ "MSRValue": "0x20003C0008",
865	865	"Counter": "0,1,2,3",
866	866	"UMask": "0x1",
867	867	"EventName": "OFFCORE_RESPONSE.COREWB.L3_HIT.SNOOP_NON_DRAM",
868		- "MSRIndex": "0x1a6,0x1a7",
	868	+ "MSRIndex": "0x1a6, 0x1a7",
869	869	"SampleAfterValue": "100003",
870		- "BriefDescription": "Counts writebacks (modified to exclusive) that hit in the L3 and the target was non-DRAM system address.",
	870	+ "BriefDescription": "Counts writebacks (modified to exclusive)",
871	871	"Offcore": "1",
872	872	"CounterHTOff": "0,1,2,3"
873	873	},
874	874	{
875		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	875	+ "PublicDescription": "Counts writebacks (modified to exclusive)",
876	876	"EventCode": "0xB7, 0xBB",
877		- "MSRValue": "0x0084000008 ",
	877	+ "MSRValue": "0x0084000008",
878	878	"Counter": "0,1,2,3",
879	879	"UMask": "0x1",
880	880	"EventName": "OFFCORE_RESPONSE.COREWB.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
881		- "MSRIndex": "0x1a6,0x1a7",
	881	+ "MSRIndex": "0x1a6, 0x1a7",
882	882	"SampleAfterValue": "100003",
883		- "BriefDescription": "COREWB & L3_MISS_LOCAL_DRAM & SNOOP_NONE",
	883	+ "BriefDescription": "Counts writebacks (modified to exclusive)",
884	884	"Offcore": "1",
885	885	"CounterHTOff": "0,1,2,3"
886	886	},
887	887	{
888		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	888	+ "PublicDescription": "Counts writebacks (modified to exclusive)",
889	889	"EventCode": "0xB7, 0xBB",
890		- "MSRValue": "0x0104000008 ",
	890	+ "MSRValue": "0x0104000008",
891	891	"Counter": "0,1,2,3",
892	892	"UMask": "0x1",
893	893	"EventName": "OFFCORE_RESPONSE.COREWB.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",
894		- "MSRIndex": "0x1a6,0x1a7",
	894	+ "MSRIndex": "0x1a6, 0x1a7",
895	895	"SampleAfterValue": "100003",
896		- "BriefDescription": "COREWB & L3_MISS_LOCAL_DRAM & SNOOP_NOT_NEEDED",
	896	+ "BriefDescription": "Counts writebacks (modified to exclusive)",
897	897	"Offcore": "1",
898	898	"CounterHTOff": "0,1,2,3"
899	899	},
900	900	{
901		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	901	+ "PublicDescription": "Counts writebacks (modified to exclusive)",
902	902	"EventCode": "0xB7, 0xBB",
903		- "MSRValue": "0x0204000008 ",
	903	+ "MSRValue": "0x0204000008",
904	904	"Counter": "0,1,2,3",
905	905	"UMask": "0x1",
906	906	"EventName": "OFFCORE_RESPONSE.COREWB.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
907		- "MSRIndex": "0x1a6,0x1a7",
	907	+ "MSRIndex": "0x1a6, 0x1a7",
908	908	"SampleAfterValue": "100003",
909		- "BriefDescription": "COREWB & L3_MISS_LOCAL_DRAM & SNOOP_MISS",
	909	+ "BriefDescription": "Counts writebacks (modified to exclusive)",
910	910	"Offcore": "1",
911	911	"CounterHTOff": "0,1,2,3"
912	912	},
913	913	{
914		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	914	+ "PublicDescription": "Counts writebacks (modified to exclusive)",
915	915	"EventCode": "0xB7, 0xBB",
916		- "MSRValue": "0x0404000008 ",
	916	+ "MSRValue": "0x0404000008",
917	917	"Counter": "0,1,2,3",
918	918	"UMask": "0x1",
919	919	"EventName": "OFFCORE_RESPONSE.COREWB.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",
920		- "MSRIndex": "0x1a6,0x1a7",
	920	+ "MSRIndex": "0x1a6, 0x1a7",
921	921	"SampleAfterValue": "100003",
922		- "BriefDescription": "COREWB & L3_MISS_LOCAL_DRAM & SNOOP_HIT_NO_FWD",
	922	+ "BriefDescription": "Counts writebacks (modified to exclusive)",
923	923	"Offcore": "1",
924	924	"CounterHTOff": "0,1,2,3"
925	925	},
926	926	{
927		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	927	+ "PublicDescription": "Counts writebacks (modified to exclusive)",
928	928	"EventCode": "0xB7, 0xBB",
929		- "MSRValue": "0x1004000008 ",
	929	+ "MSRValue": "0x1004000008",
930	930	"Counter": "0,1,2,3",
931	931	"UMask": "0x1",
932	932	"EventName": "OFFCORE_RESPONSE.COREWB.L3_MISS_LOCAL_DRAM.SNOOP_HITM",
933		- "MSRIndex": "0x1a6,0x1a7",
	933	+ "MSRIndex": "0x1a6, 0x1a7",
934	934	"SampleAfterValue": "100003",
935		- "BriefDescription": "COREWB & L3_MISS_LOCAL_DRAM & SNOOP_HITM",
	935	+ "BriefDescription": "Counts writebacks (modified to exclusive)",
936	936	"Offcore": "1",
937	937	"CounterHTOff": "0,1,2,3"
938	938	},
939	939	{
940		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	940	+ "PublicDescription": "Counts writebacks (modified to exclusive)",
941	941	"EventCode": "0xB7, 0xBB",
942		- "MSRValue": "0x2004000008 ",
	942	+ "MSRValue": "0x2004000008",
943	943	"Counter": "0,1,2,3",
944	944	"UMask": "0x1",
945	945	"EventName": "OFFCORE_RESPONSE.COREWB.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",
946		- "MSRIndex": "0x1a6,0x1a7",
	946	+ "MSRIndex": "0x1a6, 0x1a7",
947	947	"SampleAfterValue": "100003",
948		- "BriefDescription": "COREWB & L3_MISS_LOCAL_DRAM & SNOOP_NON_DRAM",
	948	+ "BriefDescription": "Counts writebacks (modified to exclusive)",
949	949	"Offcore": "1",
950	950	"CounterHTOff": "0,1,2,3"
951	951	},
952	952	{
953		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	953	+ "PublicDescription": "Counts writebacks (modified to exclusive)",
954	954	"EventCode": "0xB7, 0xBB",
955		- "MSRValue": "0x3f84000008 ",
	955	+ "MSRValue": "0x3F84000008",
956	956	"Counter": "0,1,2,3",
957	957	"UMask": "0x1",
958	958	"EventName": "OFFCORE_RESPONSE.COREWB.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
959		- "MSRIndex": "0x1a6,0x1a7",
	959	+ "MSRIndex": "0x1a6, 0x1a7",
960	960	"SampleAfterValue": "100003",
961		- "BriefDescription": "COREWB & L3_MISS_LOCAL_DRAM & ANY_SNOOP",
	961	+ "BriefDescription": "Counts writebacks (modified to exclusive)",
962	962	"Offcore": "1",
963	963	"CounterHTOff": "0,1,2,3"
964	964	},
965	965	{
966		- "PublicDescription": "Counts writebacks (modified to exclusive) that miss the L3 with no details on snoop-related information. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	966	+ "PublicDescription": "Counts writebacks (modified to exclusive)",
967	967	"EventCode": "0xB7, 0xBB",
968		- "MSRValue": "0x00bc000008 ",
	968	+ "MSRValue": "0x00BC000008",
969	969	"Counter": "0,1,2,3",
970	970	"UMask": "0x1",
971	971	"EventName": "OFFCORE_RESPONSE.COREWB.L3_MISS.SNOOP_NONE",
972		- "MSRIndex": "0x1a6,0x1a7",
	972	+ "MSRIndex": "0x1a6, 0x1a7",
973	973	"SampleAfterValue": "100003",
974		- "BriefDescription": "Counts writebacks (modified to exclusive) that miss the L3 with no details on snoop-related information.",
	974	+ "BriefDescription": "Counts writebacks (modified to exclusive)",
975	975	"Offcore": "1",
976	976	"CounterHTOff": "0,1,2,3"
977	977	},
978	978	{
979		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	979	+ "PublicDescription": "Counts writebacks (modified to exclusive)",
980	980	"EventCode": "0xB7, 0xBB",
981		- "MSRValue": "0x013c000008 ",
	981	+ "MSRValue": "0x013C000008",
982	982	"Counter": "0,1,2,3",
983	983	"UMask": "0x1",
984	984	"EventName": "OFFCORE_RESPONSE.COREWB.L3_MISS.SNOOP_NOT_NEEDED",
985		- "MSRIndex": "0x1a6,0x1a7",
	985	+ "MSRIndex": "0x1a6, 0x1a7",
986	986	"SampleAfterValue": "100003",
987		- "BriefDescription": "COREWB & L3_MISS & SNOOP_NOT_NEEDED",
	987	+ "BriefDescription": "Counts writebacks (modified to exclusive)",
988	988	"Offcore": "1",
989	989	"CounterHTOff": "0,1,2,3"
990	990	},
991	991	{
992		- "PublicDescription": "Counts writebacks (modified to exclusive) that miss the L3 with a snoop miss response. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	992	+ "PublicDescription": "Counts writebacks (modified to exclusive)",
993	993	"EventCode": "0xB7, 0xBB",
994		- "MSRValue": "0x023c000008 ",
	994	+ "MSRValue": "0x023C000008",
995	995	"Counter": "0,1,2,3",
996	996	"UMask": "0x1",
997	997	"EventName": "OFFCORE_RESPONSE.COREWB.L3_MISS.SNOOP_MISS",
998		- "MSRIndex": "0x1a6,0x1a7",
	998	+ "MSRIndex": "0x1a6, 0x1a7",
999	999	"SampleAfterValue": "100003",
1000		- "BriefDescription": "Counts writebacks (modified to exclusive) that miss the L3 with a snoop miss response.",
	1000	+ "BriefDescription": "Counts writebacks (modified to exclusive)",
1001	1001	"Offcore": "1",
1002	1002	"CounterHTOff": "0,1,2,3"
1003	1003	},
1004	1004	{
1005		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1005	+ "PublicDescription": "Counts writebacks (modified to exclusive)",
1006	1006	"EventCode": "0xB7, 0xBB",
1007		- "MSRValue": "0x043c000008 ",
	1007	+ "MSRValue": "0x043C000008",
1008	1008	"Counter": "0,1,2,3",
1009	1009	"UMask": "0x1",
1010	1010	"EventName": "OFFCORE_RESPONSE.COREWB.L3_MISS.SNOOP_HIT_NO_FWD",
1011		- "MSRIndex": "0x1a6,0x1a7",
	1011	+ "MSRIndex": "0x1a6, 0x1a7",
1012	1012	"SampleAfterValue": "100003",
1013		- "BriefDescription": "COREWB & L3_MISS & SNOOP_HIT_NO_FWD",
	1013	+ "BriefDescription": "Counts writebacks (modified to exclusive)",
1014	1014	"Offcore": "1",
1015	1015	"CounterHTOff": "0,1,2,3"
1016	1016	},
1017	1017	{
1018		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1018	+ "PublicDescription": "Counts prefetch (that bring data to L2) data reads",
1019	1019	"EventCode": "0xB7, 0xBB",
1020		- "MSRValue": "0x2000020010 ",
	1020	+ "MSRValue": "0x2000020010",
1021	1021	"Counter": "0,1,2,3",
1022	1022	"UMask": "0x1",
1023	1023	"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_NON_DRAM",
1024		- "MSRIndex": "0x1a6,0x1a7",
	1024	+ "MSRIndex": "0x1a6, 0x1a7",
1025	1025	"SampleAfterValue": "100003",
1026		- "BriefDescription": "PF_L2_DATA_RD & SUPPLIER_NONE & SNOOP_NON_DRAM",
	1026	+ "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
1027	1027	"Offcore": "1",
1028	1028	"CounterHTOff": "0,1,2,3"
1029	1029	},
1030	1030	{
1031		- "PublicDescription": "Counts prefetch (that bring data to L2) data reads that hit in the L3 and the target was non-DRAM system address. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1031	+ "PublicDescription": "Counts prefetch (that bring data to L2) data reads",
1032	1032	"EventCode": "0xB7, 0xBB",
1033		- "MSRValue": "0x20003c0010 ",
	1033	+ "MSRValue": "0x20003C0010",
1034	1034	"Counter": "0,1,2,3",
1035	1035	"UMask": "0x1",
1036	1036	"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_NON_DRAM",
1037		- "MSRIndex": "0x1a6,0x1a7",
	1037	+ "MSRIndex": "0x1a6, 0x1a7",
1038	1038	"SampleAfterValue": "100003",
1039		- "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the L3 and the target was non-DRAM system address.",
	1039	+ "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
1040	1040	"Offcore": "1",
1041	1041	"CounterHTOff": "0,1,2,3"
1042	1042	},
1043	1043	{
1044		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1044	+ "PublicDescription": "Counts prefetch (that bring data to L2) data reads",
1045	1045	"EventCode": "0xB7, 0xBB",
1046		- "MSRValue": "0x0084000010 ",
	1046	+ "MSRValue": "0x0084000010",
1047	1047	"Counter": "0,1,2,3",
1048	1048	"UMask": "0x1",
1049	1049	"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
1050		- "MSRIndex": "0x1a6,0x1a7",
	1050	+ "MSRIndex": "0x1a6, 0x1a7",
1051	1051	"SampleAfterValue": "100003",
1052		- "BriefDescription": "PF_L2_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_NONE",
	1052	+ "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
1053	1053	"Offcore": "1",
1054	1054	"CounterHTOff": "0,1,2,3"
1055	1055	},
1056	1056	{
1057		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1057	+ "PublicDescription": "Counts prefetch (that bring data to L2) data reads",
1058	1058	"EventCode": "0xB7, 0xBB",
1059		- "MSRValue": "0x0104000010 ",
	1059	+ "MSRValue": "0x0104000010",
1060	1060	"Counter": "0,1,2,3",
1061	1061	"UMask": "0x1",
1062	1062	"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",
1063		- "MSRIndex": "0x1a6,0x1a7",
	1063	+ "MSRIndex": "0x1a6, 0x1a7",
1064	1064	"SampleAfterValue": "100003",
1065		- "BriefDescription": "PF_L2_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_NOT_NEEDED",
	1065	+ "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
1066	1066	"Offcore": "1",
1067	1067	"CounterHTOff": "0,1,2,3"
1068	1068	},
1069	1069	{
1070		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1070	+ "PublicDescription": "Counts prefetch (that bring data to L2) data reads",
1071	1071	"EventCode": "0xB7, 0xBB",
1072		- "MSRValue": "0x0204000010 ",
	1072	+ "MSRValue": "0x0204000010",
1073	1073	"Counter": "0,1,2,3",
1074	1074	"UMask": "0x1",
1075	1075	"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
1076		- "MSRIndex": "0x1a6,0x1a7",
	1076	+ "MSRIndex": "0x1a6, 0x1a7",
1077	1077	"SampleAfterValue": "100003",
1078		- "BriefDescription": "PF_L2_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_MISS",
	1078	+ "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
1079	1079	"Offcore": "1",
1080	1080	"CounterHTOff": "0,1,2,3"
1081	1081	},
1082	1082	{
1083		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1083	+ "PublicDescription": "Counts prefetch (that bring data to L2) data reads",
1084	1084	"EventCode": "0xB7, 0xBB",
1085		- "MSRValue": "0x0404000010 ",
	1085	+ "MSRValue": "0x0404000010",
1086	1086	"Counter": "0,1,2,3",
1087	1087	"UMask": "0x1",
1088	1088	"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",
1089		- "MSRIndex": "0x1a6,0x1a7",
	1089	+ "MSRIndex": "0x1a6, 0x1a7",
1090	1090	"SampleAfterValue": "100003",
1091		- "BriefDescription": "PF_L2_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_HIT_NO_FWD",
	1091	+ "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
1092	1092	"Offcore": "1",
1093	1093	"CounterHTOff": "0,1,2,3"
1094	1094	},
1095	1095	{
1096		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1096	+ "PublicDescription": "Counts prefetch (that bring data to L2) data reads",
1097	1097	"EventCode": "0xB7, 0xBB",
1098		- "MSRValue": "0x1004000010 ",
	1098	+ "MSRValue": "0x1004000010",
1099	1099	"Counter": "0,1,2,3",
1100	1100	"UMask": "0x1",
1101	1101	"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM",
1102		- "MSRIndex": "0x1a6,0x1a7",
	1102	+ "MSRIndex": "0x1a6, 0x1a7",
1103	1103	"SampleAfterValue": "100003",
1104		- "BriefDescription": "PF_L2_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_HITM",
	1104	+ "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
1105	1105	"Offcore": "1",
1106	1106	"CounterHTOff": "0,1,2,3"
1107	1107	},
1108	1108	{
1109		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1109	+ "PublicDescription": "Counts prefetch (that bring data to L2) data reads",
1110	1110	"EventCode": "0xB7, 0xBB",
1111		- "MSRValue": "0x2004000010 ",
	1111	+ "MSRValue": "0x2004000010",
1112	1112	"Counter": "0,1,2,3",
1113	1113	"UMask": "0x1",
1114	1114	"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",
1115		- "MSRIndex": "0x1a6,0x1a7",
	1115	+ "MSRIndex": "0x1a6, 0x1a7",
1116	1116	"SampleAfterValue": "100003",
1117		- "BriefDescription": "PF_L2_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_NON_DRAM",
	1117	+ "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
1118	1118	"Offcore": "1",
1119	1119	"CounterHTOff": "0,1,2,3"
1120	1120	},
1121	1121	{
1122		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1122	+ "PublicDescription": "Counts prefetch (that bring data to L2) data reads",
1123	1123	"EventCode": "0xB7, 0xBB",
1124		- "MSRValue": "0x3f84000010 ",
	1124	+ "MSRValue": "0x3F84000010",
1125	1125	"Counter": "0,1,2,3",
1126	1126	"UMask": "0x1",
1127	1127	"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
1128		- "MSRIndex": "0x1a6,0x1a7",
	1128	+ "MSRIndex": "0x1a6, 0x1a7",
1129	1129	"SampleAfterValue": "100003",
1130		- "BriefDescription": "PF_L2_DATA_RD & L3_MISS_LOCAL_DRAM & ANY_SNOOP",
	1130	+ "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
1131	1131	"Offcore": "1",
1132	1132	"CounterHTOff": "0,1,2,3"
1133	1133	},
1134	1134	{
1135		- "PublicDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 with no details on snoop-related information. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1135	+ "PublicDescription": "Counts prefetch (that bring data to L2) data reads",
1136	1136	"EventCode": "0xB7, 0xBB",
1137		- "MSRValue": "0x00bc000010 ",
	1137	+ "MSRValue": "0x00BC000010",
1138	1138	"Counter": "0,1,2,3",
1139	1139	"UMask": "0x1",
1140	1140	"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.SNOOP_NONE",
1141		- "MSRIndex": "0x1a6,0x1a7",
	1141	+ "MSRIndex": "0x1a6, 0x1a7",
1142	1142	"SampleAfterValue": "100003",
1143		- "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 with no details on snoop-related information.",
	1143	+ "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
1144	1144	"Offcore": "1",
1145	1145	"CounterHTOff": "0,1,2,3"
1146	1146	},
1147	1147	{
1148		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1148	+ "PublicDescription": "Counts prefetch (that bring data to L2) data reads",
1149	1149	"EventCode": "0xB7, 0xBB",
1150		- "MSRValue": "0x013c000010 ",
	1150	+ "MSRValue": "0x013C000010",
1151	1151	"Counter": "0,1,2,3",
1152	1152	"UMask": "0x1",
1153	1153	"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.SNOOP_NOT_NEEDED",
1154		- "MSRIndex": "0x1a6,0x1a7",
	1154	+ "MSRIndex": "0x1a6, 0x1a7",
1155	1155	"SampleAfterValue": "100003",
1156		- "BriefDescription": "PF_L2_DATA_RD & L3_MISS & SNOOP_NOT_NEEDED",
	1156	+ "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
1157	1157	"Offcore": "1",
1158	1158	"CounterHTOff": "0,1,2,3"
1159	1159	},
1160	1160	{
1161		- "PublicDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 with a snoop miss response. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1161	+ "PublicDescription": "Counts prefetch (that bring data to L2) data reads",
1162	1162	"EventCode": "0xB7, 0xBB",
1163		- "MSRValue": "0x023c000010 ",
	1163	+ "MSRValue": "0x023C000010",
1164	1164	"Counter": "0,1,2,3",
1165	1165	"UMask": "0x1",
1166	1166	"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.SNOOP_MISS",
1167		- "MSRIndex": "0x1a6,0x1a7",
	1167	+ "MSRIndex": "0x1a6, 0x1a7",
1168	1168	"SampleAfterValue": "100003",
1169		- "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 with a snoop miss response.",
	1169	+ "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
1170	1170	"Offcore": "1",
1171	1171	"CounterHTOff": "0,1,2,3"
1172	1172	},
1173	1173	{
1174		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1174	+ "PublicDescription": "Counts prefetch (that bring data to L2) data reads",
1175	1175	"EventCode": "0xB7, 0xBB",
1176		- "MSRValue": "0x043c000010 ",
	1176	+ "MSRValue": "0x043C000010",
1177	1177	"Counter": "0,1,2,3",
1178	1178	"UMask": "0x1",
1179	1179	"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.SNOOP_HIT_NO_FWD",
1180		- "MSRIndex": "0x1a6,0x1a7",
	1180	+ "MSRIndex": "0x1a6, 0x1a7",
1181	1181	"SampleAfterValue": "100003",
1182		- "BriefDescription": "PF_L2_DATA_RD & L3_MISS & SNOOP_HIT_NO_FWD",
	1182	+ "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
1183	1183	"Offcore": "1",
1184	1184	"CounterHTOff": "0,1,2,3"
1185	1185	},
1186	1186	{
1187		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1187	+ "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs",
1188	1188	"EventCode": "0xB7, 0xBB",
1189		- "MSRValue": "0x2000020020 ",
	1189	+ "MSRValue": "0x2000020020",
1190	1190	"Counter": "0,1,2,3",
1191	1191	"UMask": "0x1",
1192	1192	"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.SNOOP_NON_DRAM",
1193		- "MSRIndex": "0x1a6,0x1a7",
	1193	+ "MSRIndex": "0x1a6, 0x1a7",
1194	1194	"SampleAfterValue": "100003",
1195		- "BriefDescription": "PF_L2_RFO & SUPPLIER_NONE & SNOOP_NON_DRAM",
	1195	+ "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
1196	1196	"Offcore": "1",
1197	1197	"CounterHTOff": "0,1,2,3"
1198	1198	},
1199	1199	{
1200		- "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs that hit in the L3 and the target was non-DRAM system address. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1200	+ "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs",
1201	1201	"EventCode": "0xB7, 0xBB",
1202		- "MSRValue": "0x20003c0020 ",
	1202	+ "MSRValue": "0x20003C0020",
1203	1203	"Counter": "0,1,2,3",
1204	1204	"UMask": "0x1",
1205	1205	"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_NON_DRAM",
1206		- "MSRIndex": "0x1a6,0x1a7",
	1206	+ "MSRIndex": "0x1a6, 0x1a7",
1207	1207	"SampleAfterValue": "100003",
1208		- "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that hit in the L3 and the target was non-DRAM system address.",
	1208	+ "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
1209	1209	"Offcore": "1",
1210	1210	"CounterHTOff": "0,1,2,3"
1211	1211	},
1212	1212	{
1213		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1213	+ "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs",
1214	1214	"EventCode": "0xB7, 0xBB",
1215		- "MSRValue": "0x0084000020 ",
	1215	+ "MSRValue": "0x0084000020",
1216	1216	"Counter": "0,1,2,3",
1217	1217	"UMask": "0x1",
1218	1218	"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
1219		- "MSRIndex": "0x1a6,0x1a7",
	1219	+ "MSRIndex": "0x1a6, 0x1a7",
1220	1220	"SampleAfterValue": "100003",
1221		- "BriefDescription": "PF_L2_RFO & L3_MISS_LOCAL_DRAM & SNOOP_NONE",
	1221	+ "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
1222	1222	"Offcore": "1",
1223	1223	"CounterHTOff": "0,1,2,3"
1224	1224	},
1225	1225	{
1226		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1226	+ "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs",
1227	1227	"EventCode": "0xB7, 0xBB",
1228		- "MSRValue": "0x0104000020 ",
	1228	+ "MSRValue": "0x0104000020",
1229	1229	"Counter": "0,1,2,3",
1230	1230	"UMask": "0x1",
1231	1231	"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",
1232		- "MSRIndex": "0x1a6,0x1a7",
	1232	+ "MSRIndex": "0x1a6, 0x1a7",
1233	1233	"SampleAfterValue": "100003",
1234		- "BriefDescription": "PF_L2_RFO & L3_MISS_LOCAL_DRAM & SNOOP_NOT_NEEDED",
	1234	+ "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
1235	1235	"Offcore": "1",
1236	1236	"CounterHTOff": "0,1,2,3"
1237	1237	},
1238	1238	{
1239		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1239	+ "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs",
1240	1240	"EventCode": "0xB7, 0xBB",
1241		- "MSRValue": "0x0204000020 ",
	1241	+ "MSRValue": "0x0204000020",
1242	1242	"Counter": "0,1,2,3",
1243	1243	"UMask": "0x1",
1244	1244	"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
1245		- "MSRIndex": "0x1a6,0x1a7",
	1245	+ "MSRIndex": "0x1a6, 0x1a7",
1246	1246	"SampleAfterValue": "100003",
1247		- "BriefDescription": "PF_L2_RFO & L3_MISS_LOCAL_DRAM & SNOOP_MISS",
	1247	+ "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
1248	1248	"Offcore": "1",
1249	1249	"CounterHTOff": "0,1,2,3"
1250	1250	},
1251	1251	{
1252		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1252	+ "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs",
1253	1253	"EventCode": "0xB7, 0xBB",
1254		- "MSRValue": "0x0404000020 ",
	1254	+ "MSRValue": "0x0404000020",
1255	1255	"Counter": "0,1,2,3",
1256	1256	"UMask": "0x1",
1257	1257	"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",
1258		- "MSRIndex": "0x1a6,0x1a7",
	1258	+ "MSRIndex": "0x1a6, 0x1a7",
1259	1259	"SampleAfterValue": "100003",
1260		- "BriefDescription": "PF_L2_RFO & L3_MISS_LOCAL_DRAM & SNOOP_HIT_NO_FWD",
	1260	+ "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
1261	1261	"Offcore": "1",
1262	1262	"CounterHTOff": "0,1,2,3"
1263	1263	},
1264	1264	{
1265		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1265	+ "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs",
1266	1266	"EventCode": "0xB7, 0xBB",
1267		- "MSRValue": "0x1004000020 ",
	1267	+ "MSRValue": "0x1004000020",
1268	1268	"Counter": "0,1,2,3",
1269	1269	"UMask": "0x1",
1270	1270	"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HITM",
1271		- "MSRIndex": "0x1a6,0x1a7",
	1271	+ "MSRIndex": "0x1a6, 0x1a7",
1272	1272	"SampleAfterValue": "100003",
1273		- "BriefDescription": "PF_L2_RFO & L3_MISS_LOCAL_DRAM & SNOOP_HITM",
	1273	+ "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
1274	1274	"Offcore": "1",
1275	1275	"CounterHTOff": "0,1,2,3"
1276	1276	},
1277	1277	{
1278		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1278	+ "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs",
1279	1279	"EventCode": "0xB7, 0xBB",
1280		- "MSRValue": "0x2004000020 ",
	1280	+ "MSRValue": "0x2004000020",
1281	1281	"Counter": "0,1,2,3",
1282	1282	"UMask": "0x1",
1283	1283	"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",
1284		- "MSRIndex": "0x1a6,0x1a7",
	1284	+ "MSRIndex": "0x1a6, 0x1a7",
1285	1285	"SampleAfterValue": "100003",
1286		- "BriefDescription": "PF_L2_RFO & L3_MISS_LOCAL_DRAM & SNOOP_NON_DRAM",
	1286	+ "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
1287	1287	"Offcore": "1",
1288	1288	"CounterHTOff": "0,1,2,3"
1289	1289	},
1290	1290	{
1291		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1291	+ "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs",
1292	1292	"EventCode": "0xB7, 0xBB",
1293		- "MSRValue": "0x3f84000020 ",
	1293	+ "MSRValue": "0x3F84000020",
1294	1294	"Counter": "0,1,2,3",
1295	1295	"UMask": "0x1",
1296	1296	"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
1297		- "MSRIndex": "0x1a6,0x1a7",
	1297	+ "MSRIndex": "0x1a6, 0x1a7",
1298	1298	"SampleAfterValue": "100003",
1299		- "BriefDescription": "PF_L2_RFO & L3_MISS_LOCAL_DRAM & ANY_SNOOP",
	1299	+ "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
1300	1300	"Offcore": "1",
1301	1301	"CounterHTOff": "0,1,2,3"
1302	1302	},
1303	1303	{
1304		- "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 with no details on snoop-related information. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1304	+ "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs",
1305	1305	"EventCode": "0xB7, 0xBB",
1306		- "MSRValue": "0x00bc000020 ",
	1306	+ "MSRValue": "0x00BC000020",
1307	1307	"Counter": "0,1,2,3",
1308	1308	"UMask": "0x1",
1309	1309	"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.SNOOP_NONE",
1310		- "MSRIndex": "0x1a6,0x1a7",
	1310	+ "MSRIndex": "0x1a6, 0x1a7",
1311	1311	"SampleAfterValue": "100003",
1312		- "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 with no details on snoop-related information.",
	1312	+ "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
1313	1313	"Offcore": "1",
1314	1314	"CounterHTOff": "0,1,2,3"
1315	1315	},
1316	1316	{
1317		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1317	+ "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs",
1318	1318	"EventCode": "0xB7, 0xBB",
1319		- "MSRValue": "0x013c000020 ",
	1319	+ "MSRValue": "0x013C000020",
1320	1320	"Counter": "0,1,2,3",
1321	1321	"UMask": "0x1",
1322	1322	"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.SNOOP_NOT_NEEDED",
1323		- "MSRIndex": "0x1a6,0x1a7",
	1323	+ "MSRIndex": "0x1a6, 0x1a7",
1324	1324	"SampleAfterValue": "100003",
1325		- "BriefDescription": "PF_L2_RFO & L3_MISS & SNOOP_NOT_NEEDED",
	1325	+ "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
1326	1326	"Offcore": "1",
1327	1327	"CounterHTOff": "0,1,2,3"
1328	1328	},
1329	1329	{
1330		- "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 with a snoop miss response. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1330	+ "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs",
1331	1331	"EventCode": "0xB7, 0xBB",
1332		- "MSRValue": "0x023c000020 ",
	1332	+ "MSRValue": "0x023C000020",
1333	1333	"Counter": "0,1,2,3",
1334	1334	"UMask": "0x1",
1335	1335	"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.SNOOP_MISS",
1336		- "MSRIndex": "0x1a6,0x1a7",
	1336	+ "MSRIndex": "0x1a6, 0x1a7",
1337	1337	"SampleAfterValue": "100003",
1338		- "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 with a snoop miss response.",
	1338	+ "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
1339	1339	"Offcore": "1",
1340	1340	"CounterHTOff": "0,1,2,3"
1341	1341	},
1342	1342	{
1343		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1343	+ "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs",
1344	1344	"EventCode": "0xB7, 0xBB",
1345		- "MSRValue": "0x043c000020 ",
	1345	+ "MSRValue": "0x043C000020",
1346	1346	"Counter": "0,1,2,3",
1347	1347	"UMask": "0x1",
1348	1348	"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.SNOOP_HIT_NO_FWD",
1349		- "MSRIndex": "0x1a6,0x1a7",
	1349	+ "MSRIndex": "0x1a6, 0x1a7",
1350	1350	"SampleAfterValue": "100003",
1351		- "BriefDescription": "PF_L2_RFO & L3_MISS & SNOOP_HIT_NO_FWD",
	1351	+ "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
1352	1352	"Offcore": "1",
1353	1353	"CounterHTOff": "0,1,2,3"
1354	1354	},
1355	1355	{
1356		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1356	+ "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads",
1357	1357	"EventCode": "0xB7, 0xBB",
1358		- "MSRValue": "0x2000020040 ",
	1358	+ "MSRValue": "0x2000020040",
1359	1359	"Counter": "0,1,2,3",
1360	1360	"UMask": "0x1",
1361	1361	"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.SUPPLIER_NONE.SNOOP_NON_DRAM",
1362		- "MSRIndex": "0x1a6,0x1a7",
	1362	+ "MSRIndex": "0x1a6, 0x1a7",
1363	1363	"SampleAfterValue": "100003",
1364		- "BriefDescription": "PF_L2_CODE_RD & SUPPLIER_NONE & SNOOP_NON_DRAM",
	1364	+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads",
1365	1365	"Offcore": "1",
1366	1366	"CounterHTOff": "0,1,2,3"
1367	1367	},
1368	1368	{
1369		- "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads that hit in the L3 and the target was non-DRAM system address. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1369	+ "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads",
1370	1370	"EventCode": "0xB7, 0xBB",
1371		- "MSRValue": "0x20003c0040 ",
	1371	+ "MSRValue": "0x20003C0040",
1372	1372	"Counter": "0,1,2,3",
1373	1373	"UMask": "0x1",
1374	1374	"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_HIT.SNOOP_NON_DRAM",
1375		- "MSRIndex": "0x1a6,0x1a7",
	1375	+ "MSRIndex": "0x1a6, 0x1a7",
1376	1376	"SampleAfterValue": "100003",
1377		- "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that hit in the L3 and the target was non-DRAM system address.",
	1377	+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads",
1378	1378	"Offcore": "1",
1379	1379	"CounterHTOff": "0,1,2,3"
1380	1380	},
1381	1381	{
1382		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1382	+ "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads",
1383	1383	"EventCode": "0xB7, 0xBB",
1384		- "MSRValue": "0x0084000040 ",
	1384	+ "MSRValue": "0x0084000040",
1385	1385	"Counter": "0,1,2,3",
1386	1386	"UMask": "0x1",
1387	1387	"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
1388		- "MSRIndex": "0x1a6,0x1a7",
	1388	+ "MSRIndex": "0x1a6, 0x1a7",
1389	1389	"SampleAfterValue": "100003",
1390		- "BriefDescription": "PF_L2_CODE_RD & L3_MISS_LOCAL_DRAM & SNOOP_NONE",
	1390	+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads",
1391	1391	"Offcore": "1",
1392	1392	"CounterHTOff": "0,1,2,3"
1393	1393	},
1394	1394	{
1395		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1395	+ "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads",
1396	1396	"EventCode": "0xB7, 0xBB",
1397		- "MSRValue": "0x0104000040 ",
	1397	+ "MSRValue": "0x0104000040",
1398	1398	"Counter": "0,1,2,3",
1399	1399	"UMask": "0x1",
1400	1400	"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",
1401		- "MSRIndex": "0x1a6,0x1a7",
	1401	+ "MSRIndex": "0x1a6, 0x1a7",
1402	1402	"SampleAfterValue": "100003",
1403		- "BriefDescription": "PF_L2_CODE_RD & L3_MISS_LOCAL_DRAM & SNOOP_NOT_NEEDED",
	1403	+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads",
1404	1404	"Offcore": "1",
1405	1405	"CounterHTOff": "0,1,2,3"
1406	1406	},
1407	1407	{
1408		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1408	+ "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads",
1409	1409	"EventCode": "0xB7, 0xBB",
1410		- "MSRValue": "0x0204000040 ",
	1410	+ "MSRValue": "0x0204000040",
1411	1411	"Counter": "0,1,2,3",
1412	1412	"UMask": "0x1",
1413	1413	"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
1414		- "MSRIndex": "0x1a6,0x1a7",
	1414	+ "MSRIndex": "0x1a6, 0x1a7",
1415	1415	"SampleAfterValue": "100003",
1416		- "BriefDescription": "PF_L2_CODE_RD & L3_MISS_LOCAL_DRAM & SNOOP_MISS",
	1416	+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads",
1417	1417	"Offcore": "1",
1418	1418	"CounterHTOff": "0,1,2,3"
1419	1419	},
1420	1420	{
1421		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1421	+ "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads",
1422	1422	"EventCode": "0xB7, 0xBB",
1423		- "MSRValue": "0x0404000040 ",
	1423	+ "MSRValue": "0x0404000040",
1424	1424	"Counter": "0,1,2,3",
1425	1425	"UMask": "0x1",
1426	1426	"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",
1427		- "MSRIndex": "0x1a6,0x1a7",
	1427	+ "MSRIndex": "0x1a6, 0x1a7",
1428	1428	"SampleAfterValue": "100003",
1429		- "BriefDescription": "PF_L2_CODE_RD & L3_MISS_LOCAL_DRAM & SNOOP_HIT_NO_FWD",
	1429	+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads",
1430	1430	"Offcore": "1",
1431	1431	"CounterHTOff": "0,1,2,3"
1432	1432	},
1433	1433	{
1434		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1434	+ "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads",
1435	1435	"EventCode": "0xB7, 0xBB",
1436		- "MSRValue": "0x1004000040 ",
	1436	+ "MSRValue": "0x1004000040",
1437	1437	"Counter": "0,1,2,3",
1438	1438	"UMask": "0x1",
1439	1439	"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM",
1440		- "MSRIndex": "0x1a6,0x1a7",
	1440	+ "MSRIndex": "0x1a6, 0x1a7",
1441	1441	"SampleAfterValue": "100003",
1442		- "BriefDescription": "PF_L2_CODE_RD & L3_MISS_LOCAL_DRAM & SNOOP_HITM",
	1442	+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads",
1443	1443	"Offcore": "1",
1444	1444	"CounterHTOff": "0,1,2,3"
1445	1445	},
1446	1446	{
1447		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1447	+ "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads",
1448	1448	"EventCode": "0xB7, 0xBB",
1449		- "MSRValue": "0x2004000040 ",
	1449	+ "MSRValue": "0x2004000040",
1450	1450	"Counter": "0,1,2,3",
1451	1451	"UMask": "0x1",
1452	1452	"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",
1453		- "MSRIndex": "0x1a6,0x1a7",
	1453	+ "MSRIndex": "0x1a6, 0x1a7",
1454	1454	"SampleAfterValue": "100003",
1455		- "BriefDescription": "PF_L2_CODE_RD & L3_MISS_LOCAL_DRAM & SNOOP_NON_DRAM",
	1455	+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads",
1456	1456	"Offcore": "1",
1457	1457	"CounterHTOff": "0,1,2,3"
1458	1458	},
1459	1459	{
1460		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1460	+ "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads",
1461	1461	"EventCode": "0xB7, 0xBB",
1462		- "MSRValue": "0x3f84000040 ",
	1462	+ "MSRValue": "0x3F84000040",
1463	1463	"Counter": "0,1,2,3",
1464	1464	"UMask": "0x1",
1465	1465	"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
1466		- "MSRIndex": "0x1a6,0x1a7",
	1466	+ "MSRIndex": "0x1a6, 0x1a7",
1467	1467	"SampleAfterValue": "100003",
1468		- "BriefDescription": "PF_L2_CODE_RD & L3_MISS_LOCAL_DRAM & ANY_SNOOP",
	1468	+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads",
1469	1469	"Offcore": "1",
1470	1470	"CounterHTOff": "0,1,2,3"
1471	1471	},
1472	1472	{
1473		- "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads that miss the L3 with no details on snoop-related information. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1473	+ "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads",
1474	1474	"EventCode": "0xB7, 0xBB",
1475		- "MSRValue": "0x00bc000040 ",
	1475	+ "MSRValue": "0x00BC000040",
1476	1476	"Counter": "0,1,2,3",
1477	1477	"UMask": "0x1",
1478	1478	"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS.SNOOP_NONE",
1479		- "MSRIndex": "0x1a6,0x1a7",
	1479	+ "MSRIndex": "0x1a6, 0x1a7",
1480	1480	"SampleAfterValue": "100003",
1481		- "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that miss the L3 with no details on snoop-related information.",
	1481	+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads",
1482	1482	"Offcore": "1",
1483	1483	"CounterHTOff": "0,1,2,3"
1484	1484	},
1485	1485	{
1486		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1486	+ "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads",
1487	1487	"EventCode": "0xB7, 0xBB",
1488		- "MSRValue": "0x013c000040 ",
	1488	+ "MSRValue": "0x013C000040",
1489	1489	"Counter": "0,1,2,3",
1490	1490	"UMask": "0x1",
1491	1491	"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS.SNOOP_NOT_NEEDED",
1492		- "MSRIndex": "0x1a6,0x1a7",
	1492	+ "MSRIndex": "0x1a6, 0x1a7",
1493	1493	"SampleAfterValue": "100003",
1494		- "BriefDescription": "PF_L2_CODE_RD & L3_MISS & SNOOP_NOT_NEEDED",
	1494	+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads",
1495	1495	"Offcore": "1",
1496	1496	"CounterHTOff": "0,1,2,3"
1497	1497	},
1498	1498	{
1499		- "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads that miss the L3 with a snoop miss response. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1499	+ "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads",
1500	1500	"EventCode": "0xB7, 0xBB",
1501		- "MSRValue": "0x023c000040 ",
	1501	+ "MSRValue": "0x023C000040",
1502	1502	"Counter": "0,1,2,3",
1503	1503	"UMask": "0x1",
1504	1504	"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS.SNOOP_MISS",
1505		- "MSRIndex": "0x1a6,0x1a7",
	1505	+ "MSRIndex": "0x1a6, 0x1a7",
1506	1506	"SampleAfterValue": "100003",
1507		- "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that miss the L3 with a snoop miss response.",
	1507	+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads",
1508	1508	"Offcore": "1",
1509	1509	"CounterHTOff": "0,1,2,3"
1510	1510	},
1511	1511	{
1512		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1512	+ "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads",
1513	1513	"EventCode": "0xB7, 0xBB",
1514		- "MSRValue": "0x043c000040 ",
	1514	+ "MSRValue": "0x043C000040",
1515	1515	"Counter": "0,1,2,3",
1516	1516	"UMask": "0x1",
1517	1517	"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS.SNOOP_HIT_NO_FWD",
1518		- "MSRIndex": "0x1a6,0x1a7",
	1518	+ "MSRIndex": "0x1a6, 0x1a7",
1519	1519	"SampleAfterValue": "100003",
1520		- "BriefDescription": "PF_L2_CODE_RD & L3_MISS & SNOOP_HIT_NO_FWD",
	1520	+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads",
1521	1521	"Offcore": "1",
1522	1522	"CounterHTOff": "0,1,2,3"
1523	1523	},
1524	1524	{
1525		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1525	+ "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads",
1526	1526	"EventCode": "0xB7, 0xBB",
1527		- "MSRValue": "0x2000020080 ",
	1527	+ "MSRValue": "0x2000020080",
1528	1528	"Counter": "0,1,2,3",
1529	1529	"UMask": "0x1",
1530	1530	"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_NON_DRAM",
1531		- "MSRIndex": "0x1a6,0x1a7",
	1531	+ "MSRIndex": "0x1a6, 0x1a7",
1532	1532	"SampleAfterValue": "100003",
1533		- "BriefDescription": "PF_L3_DATA_RD & SUPPLIER_NONE & SNOOP_NON_DRAM",
	1533	+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
1534	1534	"Offcore": "1",
1535	1535	"CounterHTOff": "0,1,2,3"
1536	1536	},
1537	1537	{
1538		- "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 and the target was non-DRAM system address. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1538	+ "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads",
1539	1539	"EventCode": "0xB7, 0xBB",
1540		- "MSRValue": "0x20003c0080 ",
	1540	+ "MSRValue": "0x20003C0080",
1541	1541	"Counter": "0,1,2,3",
1542	1542	"UMask": "0x1",
1543	1543	"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_NON_DRAM",
1544		- "MSRIndex": "0x1a6,0x1a7",
	1544	+ "MSRIndex": "0x1a6, 0x1a7",
1545	1545	"SampleAfterValue": "100003",
1546		- "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 and the target was non-DRAM system address.",
	1546	+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
1547	1547	"Offcore": "1",
1548	1548	"CounterHTOff": "0,1,2,3"
1549	1549	},
1550	1550	{
1551		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1551	+ "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads",
1552	1552	"EventCode": "0xB7, 0xBB",
1553		- "MSRValue": "0x0084000080 ",
	1553	+ "MSRValue": "0x0084000080",
1554	1554	"Counter": "0,1,2,3",
1555	1555	"UMask": "0x1",
1556	1556	"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
1557		- "MSRIndex": "0x1a6,0x1a7",
	1557	+ "MSRIndex": "0x1a6, 0x1a7",
1558	1558	"SampleAfterValue": "100003",
1559		- "BriefDescription": "PF_L3_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_NONE",
	1559	+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
1560	1560	"Offcore": "1",
1561	1561	"CounterHTOff": "0,1,2,3"
1562	1562	},
1563	1563	{
1564		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1564	+ "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads",
1565	1565	"EventCode": "0xB7, 0xBB",
1566		- "MSRValue": "0x0104000080 ",
	1566	+ "MSRValue": "0x0104000080",
1567	1567	"Counter": "0,1,2,3",
1568	1568	"UMask": "0x1",
1569	1569	"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",
1570		- "MSRIndex": "0x1a6,0x1a7",
	1570	+ "MSRIndex": "0x1a6, 0x1a7",
1571	1571	"SampleAfterValue": "100003",
1572		- "BriefDescription": "PF_L3_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_NOT_NEEDED",
	1572	+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
1573	1573	"Offcore": "1",
1574	1574	"CounterHTOff": "0,1,2,3"
1575	1575	},
1576	1576	{
1577		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1577	+ "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads",
1578	1578	"EventCode": "0xB7, 0xBB",
1579		- "MSRValue": "0x0204000080 ",
	1579	+ "MSRValue": "0x0204000080",
1580	1580	"Counter": "0,1,2,3",
1581	1581	"UMask": "0x1",
1582	1582	"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
1583		- "MSRIndex": "0x1a6,0x1a7",
	1583	+ "MSRIndex": "0x1a6, 0x1a7",
1584	1584	"SampleAfterValue": "100003",
1585		- "BriefDescription": "PF_L3_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_MISS",
	1585	+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
1586	1586	"Offcore": "1",
1587	1587	"CounterHTOff": "0,1,2,3"
1588	1588	},
1589	1589	{
1590		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1590	+ "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads",
1591	1591	"EventCode": "0xB7, 0xBB",
1592		- "MSRValue": "0x0404000080 ",
	1592	+ "MSRValue": "0x0404000080",
1593	1593	"Counter": "0,1,2,3",
1594	1594	"UMask": "0x1",
1595	1595	"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",
1596		- "MSRIndex": "0x1a6,0x1a7",
	1596	+ "MSRIndex": "0x1a6, 0x1a7",
1597	1597	"SampleAfterValue": "100003",
1598		- "BriefDescription": "PF_L3_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_HIT_NO_FWD",
	1598	+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
1599	1599	"Offcore": "1",
1600	1600	"CounterHTOff": "0,1,2,3"
1601	1601	},
1602	1602	{
1603		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1603	+ "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads",
1604	1604	"EventCode": "0xB7, 0xBB",
1605		- "MSRValue": "0x1004000080 ",
	1605	+ "MSRValue": "0x1004000080",
1606	1606	"Counter": "0,1,2,3",
1607	1607	"UMask": "0x1",
1608	1608	"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM",
1609		- "MSRIndex": "0x1a6,0x1a7",
	1609	+ "MSRIndex": "0x1a6, 0x1a7",
1610	1610	"SampleAfterValue": "100003",
1611		- "BriefDescription": "PF_L3_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_HITM",
	1611	+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
1612	1612	"Offcore": "1",
1613	1613	"CounterHTOff": "0,1,2,3"
1614	1614	},
1615	1615	{
1616		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1616	+ "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads",
1617	1617	"EventCode": "0xB7, 0xBB",
1618		- "MSRValue": "0x2004000080 ",
	1618	+ "MSRValue": "0x2004000080",
1619	1619	"Counter": "0,1,2,3",
1620	1620	"UMask": "0x1",
1621	1621	"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",
1622		- "MSRIndex": "0x1a6,0x1a7",
	1622	+ "MSRIndex": "0x1a6, 0x1a7",
1623	1623	"SampleAfterValue": "100003",
1624		- "BriefDescription": "PF_L3_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_NON_DRAM",
	1624	+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
1625	1625	"Offcore": "1",
1626	1626	"CounterHTOff": "0,1,2,3"
1627	1627	},
1628	1628	{
1629		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1629	+ "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads",
1630	1630	"EventCode": "0xB7, 0xBB",
1631		- "MSRValue": "0x3f84000080 ",
	1631	+ "MSRValue": "0x3F84000080",
1632	1632	"Counter": "0,1,2,3",
1633	1633	"UMask": "0x1",
1634	1634	"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
1635		- "MSRIndex": "0x1a6,0x1a7",
	1635	+ "MSRIndex": "0x1a6, 0x1a7",
1636	1636	"SampleAfterValue": "100003",
1637		- "BriefDescription": "PF_L3_DATA_RD & L3_MISS_LOCAL_DRAM & ANY_SNOOP",
	1637	+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
1638	1638	"Offcore": "1",
1639	1639	"CounterHTOff": "0,1,2,3"
1640	1640	},
1641	1641	{
1642		- "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 with no details on snoop-related information. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1642	+ "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads",
1643	1643	"EventCode": "0xB7, 0xBB",
1644		- "MSRValue": "0x00bc000080 ",
	1644	+ "MSRValue": "0x00BC000080",
1645	1645	"Counter": "0,1,2,3",
1646	1646	"UMask": "0x1",
1647	1647	"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_NONE",
1648		- "MSRIndex": "0x1a6,0x1a7",
	1648	+ "MSRIndex": "0x1a6, 0x1a7",
1649	1649	"SampleAfterValue": "100003",
1650		- "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 with no details on snoop-related information.",
	1650	+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
1651	1651	"Offcore": "1",
1652	1652	"CounterHTOff": "0,1,2,3"
1653	1653	},
1654	1654	{
1655		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1655	+ "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads",
1656	1656	"EventCode": "0xB7, 0xBB",
1657		- "MSRValue": "0x013c000080 ",
	1657	+ "MSRValue": "0x013C000080",
1658	1658	"Counter": "0,1,2,3",
1659	1659	"UMask": "0x1",
1660	1660	"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_NOT_NEEDED",
1661		- "MSRIndex": "0x1a6,0x1a7",
	1661	+ "MSRIndex": "0x1a6, 0x1a7",
1662	1662	"SampleAfterValue": "100003",
1663		- "BriefDescription": "PF_L3_DATA_RD & L3_MISS & SNOOP_NOT_NEEDED",
	1663	+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
1664	1664	"Offcore": "1",
1665	1665	"CounterHTOff": "0,1,2,3"
1666	1666	},
1667	1667	{
1668		- "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 with a snoop miss response. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1668	+ "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads",
1669	1669	"EventCode": "0xB7, 0xBB",
1670		- "MSRValue": "0x023c000080 ",
	1670	+ "MSRValue": "0x023C000080",
1671	1671	"Counter": "0,1,2,3",
1672	1672	"UMask": "0x1",
1673	1673	"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_MISS",
1674		- "MSRIndex": "0x1a6,0x1a7",
	1674	+ "MSRIndex": "0x1a6, 0x1a7",
1675	1675	"SampleAfterValue": "100003",
1676		- "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 with a snoop miss response.",
	1676	+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
1677	1677	"Offcore": "1",
1678	1678	"CounterHTOff": "0,1,2,3"
1679	1679	},
1680	1680	{
1681		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1681	+ "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads",
1682	1682	"EventCode": "0xB7, 0xBB",
1683		- "MSRValue": "0x043c000080 ",
	1683	+ "MSRValue": "0x043C000080",
1684	1684	"Counter": "0,1,2,3",
1685	1685	"UMask": "0x1",
1686	1686	"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_HIT_NO_FWD",
1687		- "MSRIndex": "0x1a6,0x1a7",
	1687	+ "MSRIndex": "0x1a6, 0x1a7",
1688	1688	"SampleAfterValue": "100003",
1689		- "BriefDescription": "PF_L3_DATA_RD & L3_MISS & SNOOP_HIT_NO_FWD",
	1689	+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
1690	1690	"Offcore": "1",
1691	1691	"CounterHTOff": "0,1,2,3"
1692	1692	},
1693	1693	{
1694		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1694	+ "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
1695	1695	"EventCode": "0xB7, 0xBB",
1696		- "MSRValue": "0x2000020100 ",
	1696	+ "MSRValue": "0x2000020100",
1697	1697	"Counter": "0,1,2,3",
1698	1698	"UMask": "0x1",
1699	1699	"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_NON_DRAM",
1700		- "MSRIndex": "0x1a6,0x1a7",
	1700	+ "MSRIndex": "0x1a6, 0x1a7",
1701	1701	"SampleAfterValue": "100003",
1702		- "BriefDescription": "PF_L3_RFO & SUPPLIER_NONE & SNOOP_NON_DRAM",
	1702	+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
1703	1703	"Offcore": "1",
1704	1704	"CounterHTOff": "0,1,2,3"
1705	1705	},
1706	1706	{
1707		- "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 and the target was non-DRAM system address. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1707	+ "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
1708	1708	"EventCode": "0xB7, 0xBB",
1709		- "MSRValue": "0x20003c0100 ",
	1709	+ "MSRValue": "0x20003C0100",
1710	1710	"Counter": "0,1,2,3",
1711	1711	"UMask": "0x1",
1712	1712	"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_NON_DRAM",
1713		- "MSRIndex": "0x1a6,0x1a7",
	1713	+ "MSRIndex": "0x1a6, 0x1a7",
1714	1714	"SampleAfterValue": "100003",
1715		- "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 and the target was non-DRAM system address.",
	1715	+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
1716	1716	"Offcore": "1",
1717	1717	"CounterHTOff": "0,1,2,3"
1718	1718	},
1719	1719	{
1720		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1720	+ "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
1721	1721	"EventCode": "0xB7, 0xBB",
1722		- "MSRValue": "0x0084000100 ",
	1722	+ "MSRValue": "0x0084000100",
1723	1723	"Counter": "0,1,2,3",
1724	1724	"UMask": "0x1",
1725	1725	"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
1726		- "MSRIndex": "0x1a6,0x1a7",
	1726	+ "MSRIndex": "0x1a6, 0x1a7",
1727	1727	"SampleAfterValue": "100003",
1728		- "BriefDescription": "PF_L3_RFO & L3_MISS_LOCAL_DRAM & SNOOP_NONE",
	1728	+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
1729	1729	"Offcore": "1",
1730	1730	"CounterHTOff": "0,1,2,3"
1731	1731	},
1732	1732	{
1733		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1733	+ "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
1734	1734	"EventCode": "0xB7, 0xBB",
1735		- "MSRValue": "0x0104000100 ",
	1735	+ "MSRValue": "0x0104000100",
1736	1736	"Counter": "0,1,2,3",
1737	1737	"UMask": "0x1",
1738	1738	"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",
1739		- "MSRIndex": "0x1a6,0x1a7",
	1739	+ "MSRIndex": "0x1a6, 0x1a7",
1740	1740	"SampleAfterValue": "100003",
1741		- "BriefDescription": "PF_L3_RFO & L3_MISS_LOCAL_DRAM & SNOOP_NOT_NEEDED",
	1741	+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
1742	1742	"Offcore": "1",
1743	1743	"CounterHTOff": "0,1,2,3"
1744	1744	},
1745	1745	{
1746		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1746	+ "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
1747	1747	"EventCode": "0xB7, 0xBB",
1748		- "MSRValue": "0x0204000100 ",
	1748	+ "MSRValue": "0x0204000100",
1749	1749	"Counter": "0,1,2,3",
1750	1750	"UMask": "0x1",
1751	1751	"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
1752		- "MSRIndex": "0x1a6,0x1a7",
	1752	+ "MSRIndex": "0x1a6, 0x1a7",
1753	1753	"SampleAfterValue": "100003",
1754		- "BriefDescription": "PF_L3_RFO & L3_MISS_LOCAL_DRAM & SNOOP_MISS",
	1754	+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
1755	1755	"Offcore": "1",
1756	1756	"CounterHTOff": "0,1,2,3"
1757	1757	},
1758	1758	{
1759		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1759	+ "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
1760	1760	"EventCode": "0xB7, 0xBB",
1761		- "MSRValue": "0x0404000100 ",
	1761	+ "MSRValue": "0x0404000100",
1762	1762	"Counter": "0,1,2,3",
1763	1763	"UMask": "0x1",
1764	1764	"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",
1765		- "MSRIndex": "0x1a6,0x1a7",
	1765	+ "MSRIndex": "0x1a6, 0x1a7",
1766	1766	"SampleAfterValue": "100003",
1767		- "BriefDescription": "PF_L3_RFO & L3_MISS_LOCAL_DRAM & SNOOP_HIT_NO_FWD",
	1767	+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
1768	1768	"Offcore": "1",
1769	1769	"CounterHTOff": "0,1,2,3"
1770	1770	},
1771	1771	{
1772		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1772	+ "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
1773	1773	"EventCode": "0xB7, 0xBB",
1774		- "MSRValue": "0x1004000100 ",
	1774	+ "MSRValue": "0x1004000100",
1775	1775	"Counter": "0,1,2,3",
1776	1776	"UMask": "0x1",
1777	1777	"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HITM",
1778		- "MSRIndex": "0x1a6,0x1a7",
	1778	+ "MSRIndex": "0x1a6, 0x1a7",
1779	1779	"SampleAfterValue": "100003",
1780		- "BriefDescription": "PF_L3_RFO & L3_MISS_LOCAL_DRAM & SNOOP_HITM",
	1780	+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
1781	1781	"Offcore": "1",
1782	1782	"CounterHTOff": "0,1,2,3"
1783	1783	},
1784	1784	{
1785		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1785	+ "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
1786	1786	"EventCode": "0xB7, 0xBB",
1787		- "MSRValue": "0x2004000100 ",
	1787	+ "MSRValue": "0x2004000100",
1788	1788	"Counter": "0,1,2,3",
1789	1789	"UMask": "0x1",
1790	1790	"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",
1791		- "MSRIndex": "0x1a6,0x1a7",
	1791	+ "MSRIndex": "0x1a6, 0x1a7",
1792	1792	"SampleAfterValue": "100003",
1793		- "BriefDescription": "PF_L3_RFO & L3_MISS_LOCAL_DRAM & SNOOP_NON_DRAM",
	1793	+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
1794	1794	"Offcore": "1",
1795	1795	"CounterHTOff": "0,1,2,3"
1796	1796	},
1797	1797	{
1798		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1798	+ "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
1799	1799	"EventCode": "0xB7, 0xBB",
1800		- "MSRValue": "0x3f84000100 ",
	1800	+ "MSRValue": "0x3F84000100",
1801	1801	"Counter": "0,1,2,3",
1802	1802	"UMask": "0x1",
1803	1803	"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
1804		- "MSRIndex": "0x1a6,0x1a7",
	1804	+ "MSRIndex": "0x1a6, 0x1a7",
1805	1805	"SampleAfterValue": "100003",
1806		- "BriefDescription": "PF_L3_RFO & L3_MISS_LOCAL_DRAM & ANY_SNOOP",
	1806	+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
1807	1807	"Offcore": "1",
1808	1808	"CounterHTOff": "0,1,2,3"
1809	1809	},
1810	1810	{
1811		- "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 with no details on snoop-related information. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1811	+ "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
1812	1812	"EventCode": "0xB7, 0xBB",
1813		- "MSRValue": "0x00bc000100 ",
	1813	+ "MSRValue": "0x00BC000100",
1814	1814	"Counter": "0,1,2,3",
1815	1815	"UMask": "0x1",
1816	1816	"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_NONE",
1817		- "MSRIndex": "0x1a6,0x1a7",
	1817	+ "MSRIndex": "0x1a6, 0x1a7",
1818	1818	"SampleAfterValue": "100003",
1819		- "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 with no details on snoop-related information.",
	1819	+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
1820	1820	"Offcore": "1",
1821	1821	"CounterHTOff": "0,1,2,3"
1822	1822	},
1823	1823	{
1824		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1824	+ "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
1825	1825	"EventCode": "0xB7, 0xBB",
1826		- "MSRValue": "0x013c000100 ",
	1826	+ "MSRValue": "0x013C000100",
1827	1827	"Counter": "0,1,2,3",
1828	1828	"UMask": "0x1",
1829	1829	"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_NOT_NEEDED",
1830		- "MSRIndex": "0x1a6,0x1a7",
	1830	+ "MSRIndex": "0x1a6, 0x1a7",
1831	1831	"SampleAfterValue": "100003",
1832		- "BriefDescription": "PF_L3_RFO & L3_MISS & SNOOP_NOT_NEEDED",
	1832	+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
1833	1833	"Offcore": "1",
1834	1834	"CounterHTOff": "0,1,2,3"
1835	1835	},
1836	1836	{
1837		- "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 with a snoop miss response. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1837	+ "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
1838	1838	"EventCode": "0xB7, 0xBB",
1839		- "MSRValue": "0x023c000100 ",
	1839	+ "MSRValue": "0x023C000100",
1840	1840	"Counter": "0,1,2,3",
1841	1841	"UMask": "0x1",
1842	1842	"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_MISS",
1843		- "MSRIndex": "0x1a6,0x1a7",
	1843	+ "MSRIndex": "0x1a6, 0x1a7",
1844	1844	"SampleAfterValue": "100003",
1845		- "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 with a snoop miss response.",
	1845	+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
1846	1846	"Offcore": "1",
1847	1847	"CounterHTOff": "0,1,2,3"
1848	1848	},
1849	1849	{
1850		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1850	+ "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
1851	1851	"EventCode": "0xB7, 0xBB",
1852		- "MSRValue": "0x043c000100 ",
	1852	+ "MSRValue": "0x043C000100",
1853	1853	"Counter": "0,1,2,3",
1854	1854	"UMask": "0x1",
1855	1855	"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_HIT_NO_FWD",
1856		- "MSRIndex": "0x1a6,0x1a7",
	1856	+ "MSRIndex": "0x1a6, 0x1a7",
1857	1857	"SampleAfterValue": "100003",
1858		- "BriefDescription": "PF_L3_RFO & L3_MISS & SNOOP_HIT_NO_FWD",
	1858	+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
1859	1859	"Offcore": "1",
1860	1860	"CounterHTOff": "0,1,2,3"
1861	1861	},
1862	1862	{
1863		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1863	+ "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads",
1864	1864	"EventCode": "0xB7, 0xBB",
1865		- "MSRValue": "0x2000020200 ",
	1865	+ "MSRValue": "0x2000020200",
1866	1866	"Counter": "0,1,2,3",
1867	1867	"UMask": "0x1",
1868	1868	"EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.SUPPLIER_NONE.SNOOP_NON_DRAM",
1869		- "MSRIndex": "0x1a6,0x1a7",
	1869	+ "MSRIndex": "0x1a6, 0x1a7",
1870	1870	"SampleAfterValue": "100003",
1871		- "BriefDescription": "PF_L3_CODE_RD & SUPPLIER_NONE & SNOOP_NON_DRAM",
	1871	+ "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads",
1872	1872	"Offcore": "1",
1873	1873	"CounterHTOff": "0,1,2,3"
1874	1874	},
1875	1875	{
1876		- "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads that hit in the L3 and the target was non-DRAM system address. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1876	+ "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads",
1877	1877	"EventCode": "0xB7, 0xBB",
1878		- "MSRValue": "0x20003c0200 ",
	1878	+ "MSRValue": "0x20003C0200",
1879	1879	"Counter": "0,1,2,3",
1880	1880	"UMask": "0x1",
1881	1881	"EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_HIT.SNOOP_NON_DRAM",
1882		- "MSRIndex": "0x1a6,0x1a7",
	1882	+ "MSRIndex": "0x1a6, 0x1a7",
1883	1883	"SampleAfterValue": "100003",
1884		- "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads that hit in the L3 and the target was non-DRAM system address.",
	1884	+ "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads",
1885	1885	"Offcore": "1",
1886	1886	"CounterHTOff": "0,1,2,3"
1887	1887	},
1888	1888	{
1889		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1889	+ "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads",
1890	1890	"EventCode": "0xB7, 0xBB",
1891		- "MSRValue": "0x0084000200 ",
	1891	+ "MSRValue": "0x0084000200",
1892	1892	"Counter": "0,1,2,3",
1893	1893	"UMask": "0x1",
1894	1894	"EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
1895		- "MSRIndex": "0x1a6,0x1a7",
	1895	+ "MSRIndex": "0x1a6, 0x1a7",
1896	1896	"SampleAfterValue": "100003",
1897		- "BriefDescription": "PF_L3_CODE_RD & L3_MISS_LOCAL_DRAM & SNOOP_NONE",
	1897	+ "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads",
1898	1898	"Offcore": "1",
1899	1899	"CounterHTOff": "0,1,2,3"
1900	1900	},
1901	1901	{
1902		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1902	+ "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads",
1903	1903	"EventCode": "0xB7, 0xBB",
1904		- "MSRValue": "0x0104000200 ",
	1904	+ "MSRValue": "0x0104000200",
1905	1905	"Counter": "0,1,2,3",
1906	1906	"UMask": "0x1",
1907	1907	"EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",
1908		- "MSRIndex": "0x1a6,0x1a7",
	1908	+ "MSRIndex": "0x1a6, 0x1a7",
1909	1909	"SampleAfterValue": "100003",
1910		- "BriefDescription": "PF_L3_CODE_RD & L3_MISS_LOCAL_DRAM & SNOOP_NOT_NEEDED",
	1910	+ "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads",
1911	1911	"Offcore": "1",
1912	1912	"CounterHTOff": "0,1,2,3"
1913	1913	},
1914	1914	{
1915		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1915	+ "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads",
1916	1916	"EventCode": "0xB7, 0xBB",
1917		- "MSRValue": "0x0204000200 ",
	1917	+ "MSRValue": "0x0204000200",
1918	1918	"Counter": "0,1,2,3",
1919	1919	"UMask": "0x1",
1920	1920	"EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
1921		- "MSRIndex": "0x1a6,0x1a7",
	1921	+ "MSRIndex": "0x1a6, 0x1a7",
1922	1922	"SampleAfterValue": "100003",
1923		- "BriefDescription": "PF_L3_CODE_RD & L3_MISS_LOCAL_DRAM & SNOOP_MISS",
	1923	+ "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads",
1924	1924	"Offcore": "1",
1925	1925	"CounterHTOff": "0,1,2,3"
1926	1926	},
1927	1927	{
1928		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1928	+ "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads",
1929	1929	"EventCode": "0xB7, 0xBB",
1930		- "MSRValue": "0x0404000200 ",
	1930	+ "MSRValue": "0x0404000200",
1931	1931	"Counter": "0,1,2,3",
1932	1932	"UMask": "0x1",
1933	1933	"EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",
1934		- "MSRIndex": "0x1a6,0x1a7",
	1934	+ "MSRIndex": "0x1a6, 0x1a7",
1935	1935	"SampleAfterValue": "100003",
1936		- "BriefDescription": "PF_L3_CODE_RD & L3_MISS_LOCAL_DRAM & SNOOP_HIT_NO_FWD",
	1936	+ "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads",
1937	1937	"Offcore": "1",
1938	1938	"CounterHTOff": "0,1,2,3"
1939	1939	},
1940	1940	{
1941		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1941	+ "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads",
1942	1942	"EventCode": "0xB7, 0xBB",
1943		- "MSRValue": "0x1004000200 ",
	1943	+ "MSRValue": "0x1004000200",
1944	1944	"Counter": "0,1,2,3",
1945	1945	"UMask": "0x1",
1946	1946	"EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM",
1947		- "MSRIndex": "0x1a6,0x1a7",
	1947	+ "MSRIndex": "0x1a6, 0x1a7",
1948	1948	"SampleAfterValue": "100003",
1949		- "BriefDescription": "PF_L3_CODE_RD & L3_MISS_LOCAL_DRAM & SNOOP_HITM",
	1949	+ "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads",
1950	1950	"Offcore": "1",
1951	1951	"CounterHTOff": "0,1,2,3"
1952	1952	},
1953	1953	{
1954		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1954	+ "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads",
1955	1955	"EventCode": "0xB7, 0xBB",
1956		- "MSRValue": "0x2004000200 ",
	1956	+ "MSRValue": "0x2004000200",
1957	1957	"Counter": "0,1,2,3",
1958	1958	"UMask": "0x1",
1959	1959	"EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",
1960		- "MSRIndex": "0x1a6,0x1a7",
	1960	+ "MSRIndex": "0x1a6, 0x1a7",
1961	1961	"SampleAfterValue": "100003",
1962		- "BriefDescription": "PF_L3_CODE_RD & L3_MISS_LOCAL_DRAM & SNOOP_NON_DRAM",
	1962	+ "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads",
1963	1963	"Offcore": "1",
1964	1964	"CounterHTOff": "0,1,2,3"
1965	1965	},
1966	1966	{
1967		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1967	+ "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads",
1968	1968	"EventCode": "0xB7, 0xBB",
1969		- "MSRValue": "0x3f84000200 ",
	1969	+ "MSRValue": "0x3F84000200",
1970	1970	"Counter": "0,1,2,3",
1971	1971	"UMask": "0x1",
1972	1972	"EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
1973		- "MSRIndex": "0x1a6,0x1a7",
	1973	+ "MSRIndex": "0x1a6, 0x1a7",
1974	1974	"SampleAfterValue": "100003",
1975		- "BriefDescription": "PF_L3_CODE_RD & L3_MISS_LOCAL_DRAM & ANY_SNOOP",
	1975	+ "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads",
1976	1976	"Offcore": "1",
1977	1977	"CounterHTOff": "0,1,2,3"
1978	1978	},
1979	1979	{
1980		- "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads that miss the L3 with no details on snoop-related information. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1980	+ "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads",
1981	1981	"EventCode": "0xB7, 0xBB",
1982		- "MSRValue": "0x00bc000200 ",
	1982	+ "MSRValue": "0x00BC000200",
1983	1983	"Counter": "0,1,2,3",
1984	1984	"UMask": "0x1",
1985	1985	"EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS.SNOOP_NONE",
1986		- "MSRIndex": "0x1a6,0x1a7",
	1986	+ "MSRIndex": "0x1a6, 0x1a7",
1987	1987	"SampleAfterValue": "100003",
1988		- "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads that miss the L3 with no details on snoop-related information.",
	1988	+ "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads",
1989	1989	"Offcore": "1",
1990	1990	"CounterHTOff": "0,1,2,3"
1991	1991	},
1992	1992	{
1993		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1993	+ "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads",
1994	1994	"EventCode": "0xB7, 0xBB",
1995		- "MSRValue": "0x013c000200 ",
	1995	+ "MSRValue": "0x013C000200",
1996	1996	"Counter": "0,1,2,3",
1997	1997	"UMask": "0x1",
1998	1998	"EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS.SNOOP_NOT_NEEDED",
1999		- "MSRIndex": "0x1a6,0x1a7",
	1999	+ "MSRIndex": "0x1a6, 0x1a7",
2000	2000	"SampleAfterValue": "100003",
2001		- "BriefDescription": "PF_L3_CODE_RD & L3_MISS & SNOOP_NOT_NEEDED",
	2001	+ "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads",
2002	2002	"Offcore": "1",
2003	2003	"CounterHTOff": "0,1,2,3"
2004	2004	},
2005	2005	{
2006		- "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads that miss the L3 with a snoop miss response. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2006	+ "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads",
2007	2007	"EventCode": "0xB7, 0xBB",
2008		- "MSRValue": "0x023c000200 ",
	2008	+ "MSRValue": "0x023C000200",
2009	2009	"Counter": "0,1,2,3",
2010	2010	"UMask": "0x1",
2011	2011	"EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS.SNOOP_MISS",
2012		- "MSRIndex": "0x1a6,0x1a7",
	2012	+ "MSRIndex": "0x1a6, 0x1a7",
2013	2013	"SampleAfterValue": "100003",
2014		- "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads that miss the L3 with a snoop miss response.",
	2014	+ "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads",
2015	2015	"Offcore": "1",
2016	2016	"CounterHTOff": "0,1,2,3"
2017	2017	},
2018	2018	{
2019		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2019	+ "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads",
2020	2020	"EventCode": "0xB7, 0xBB",
2021		- "MSRValue": "0x043c000200 ",
	2021	+ "MSRValue": "0x043C000200",
2022	2022	"Counter": "0,1,2,3",
2023	2023	"UMask": "0x1",
2024	2024	"EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS.SNOOP_HIT_NO_FWD",
2025		- "MSRIndex": "0x1a6,0x1a7",
	2025	+ "MSRIndex": "0x1a6, 0x1a7",
2026	2026	"SampleAfterValue": "100003",
2027		- "BriefDescription": "PF_L3_CODE_RD & L3_MISS & SNOOP_HIT_NO_FWD",
	2027	+ "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads",
2028	2028	"Offcore": "1",
2029	2029	"CounterHTOff": "0,1,2,3"
2030	2030	},
2031	2031	{
2032		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2032	+ "PublicDescription": "Counts any other requests",
2033	2033	"EventCode": "0xB7, 0xBB",
2034		- "MSRValue": "0x2000028000 ",
	2034	+ "MSRValue": "0x2000028000",
2035	2035	"Counter": "0,1,2,3",
2036	2036	"UMask": "0x1",
2037	2037	"EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_NON_DRAM",
2038		- "MSRIndex": "0x1a6,0x1a7",
	2038	+ "MSRIndex": "0x1a6, 0x1a7",
2039	2039	"SampleAfterValue": "100003",
2040		- "BriefDescription": "OTHER & SUPPLIER_NONE & SNOOP_NON_DRAM",
	2040	+ "BriefDescription": "Counts any other requests",
2041	2041	"Offcore": "1",
2042	2042	"CounterHTOff": "0,1,2,3"
2043	2043	},
2044	2044	{
2045		- "PublicDescription": "Counts any other requests that hit in the L3 and the target was non-DRAM system address. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2045	+ "PublicDescription": "Counts any other requests",
2046	2046	"EventCode": "0xB7, 0xBB",
2047		- "MSRValue": "0x20003c8000 ",
	2047	+ "MSRValue": "0x20003C8000",
2048	2048	"Counter": "0,1,2,3",
2049	2049	"UMask": "0x1",
2050	2050	"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_NON_DRAM",
2051		- "MSRIndex": "0x1a6,0x1a7",
	2051	+ "MSRIndex": "0x1a6, 0x1a7",
2052	2052	"SampleAfterValue": "100003",
2053		- "BriefDescription": "Counts any other requests that hit in the L3 and the target was non-DRAM system address.",
	2053	+ "BriefDescription": "Counts any other requests",
2054	2054	"Offcore": "1",
2055	2055	"CounterHTOff": "0,1,2,3"
2056	2056	},
2057	2057	{
2058		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2058	+ "PublicDescription": "Counts any other requests",
2059	2059	"EventCode": "0xB7, 0xBB",
2060		- "MSRValue": "0x0084008000 ",
	2060	+ "MSRValue": "0x0084008000",
2061	2061	"Counter": "0,1,2,3",
2062	2062	"UMask": "0x1",
2063	2063	"EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
2064		- "MSRIndex": "0x1a6,0x1a7",
	2064	+ "MSRIndex": "0x1a6, 0x1a7",
2065	2065	"SampleAfterValue": "100003",
2066		- "BriefDescription": "OTHER & L3_MISS_LOCAL_DRAM & SNOOP_NONE",
	2066	+ "BriefDescription": "Counts any other requests",
2067	2067	"Offcore": "1",
2068	2068	"CounterHTOff": "0,1,2,3"
2069	2069	},
2070	2070	{
2071		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2071	+ "PublicDescription": "Counts any other requests",
2072	2072	"EventCode": "0xB7, 0xBB",
2073		- "MSRValue": "0x0104008000 ",
	2073	+ "MSRValue": "0x0104008000",
2074	2074	"Counter": "0,1,2,3",
2075	2075	"UMask": "0x1",
2076	2076	"EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",
2077		- "MSRIndex": "0x1a6,0x1a7",
	2077	+ "MSRIndex": "0x1a6, 0x1a7",
2078	2078	"SampleAfterValue": "100003",
2079		- "BriefDescription": "OTHER & L3_MISS_LOCAL_DRAM & SNOOP_NOT_NEEDED",
	2079	+ "BriefDescription": "Counts any other requests",
2080	2080	"Offcore": "1",
2081	2081	"CounterHTOff": "0,1,2,3"
2082	2082	},
2083	2083	{
2084		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2084	+ "PublicDescription": "Counts any other requests",
2085	2085	"EventCode": "0xB7, 0xBB",
2086		- "MSRValue": "0x0204008000 ",
	2086	+ "MSRValue": "0x0204008000",
2087	2087	"Counter": "0,1,2,3",
2088	2088	"UMask": "0x1",
2089	2089	"EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
2090		- "MSRIndex": "0x1a6,0x1a7",
	2090	+ "MSRIndex": "0x1a6, 0x1a7",
2091	2091	"SampleAfterValue": "100003",
2092		- "BriefDescription": "OTHER & L3_MISS_LOCAL_DRAM & SNOOP_MISS",
	2092	+ "BriefDescription": "Counts any other requests",
2093	2093	"Offcore": "1",
2094	2094	"CounterHTOff": "0,1,2,3"
2095	2095	},
2096	2096	{
2097		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2097	+ "PublicDescription": "Counts any other requests",
2098	2098	"EventCode": "0xB7, 0xBB",
2099		- "MSRValue": "0x0404008000 ",
	2099	+ "MSRValue": "0x0404008000",
2100	2100	"Counter": "0,1,2,3",
2101	2101	"UMask": "0x1",
2102	2102	"EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",
2103		- "MSRIndex": "0x1a6,0x1a7",
	2103	+ "MSRIndex": "0x1a6, 0x1a7",
2104	2104	"SampleAfterValue": "100003",
2105		- "BriefDescription": "OTHER & L3_MISS_LOCAL_DRAM & SNOOP_HIT_NO_FWD",
	2105	+ "BriefDescription": "Counts any other requests",
2106	2106	"Offcore": "1",
2107	2107	"CounterHTOff": "0,1,2,3"
2108	2108	},
2109	2109	{
2110		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2110	+ "PublicDescription": "Counts any other requests",
2111	2111	"EventCode": "0xB7, 0xBB",
2112		- "MSRValue": "0x1004008000 ",
	2112	+ "MSRValue": "0x1004008000",
2113	2113	"Counter": "0,1,2,3",
2114	2114	"UMask": "0x1",
2115	2115	"EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_HITM",
2116		- "MSRIndex": "0x1a6,0x1a7",
	2116	+ "MSRIndex": "0x1a6, 0x1a7",
2117	2117	"SampleAfterValue": "100003",
2118		- "BriefDescription": "OTHER & L3_MISS_LOCAL_DRAM & SNOOP_HITM",
	2118	+ "BriefDescription": "Counts any other requests",
2119	2119	"Offcore": "1",
2120	2120	"CounterHTOff": "0,1,2,3"
2121	2121	},
2122	2122	{
2123		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2123	+ "PublicDescription": "Counts any other requests",
2124	2124	"EventCode": "0xB7, 0xBB",
2125		- "MSRValue": "0x2004008000 ",
	2125	+ "MSRValue": "0x2004008000",
2126	2126	"Counter": "0,1,2,3",
2127	2127	"UMask": "0x1",
2128	2128	"EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",
2129		- "MSRIndex": "0x1a6,0x1a7",
	2129	+ "MSRIndex": "0x1a6, 0x1a7",
2130	2130	"SampleAfterValue": "100003",
2131		- "BriefDescription": "OTHER & L3_MISS_LOCAL_DRAM & SNOOP_NON_DRAM",
	2131	+ "BriefDescription": "Counts any other requests",
2132	2132	"Offcore": "1",
2133	2133	"CounterHTOff": "0,1,2,3"
2134	2134	},
2135	2135	{
2136		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2136	+ "PublicDescription": "Counts any other requests",
2137	2137	"EventCode": "0xB7, 0xBB",
2138		- "MSRValue": "0x3f84008000 ",
	2138	+ "MSRValue": "0x3F84008000",
2139	2139	"Counter": "0,1,2,3",
2140	2140	"UMask": "0x1",
2141	2141	"EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
2142		- "MSRIndex": "0x1a6,0x1a7",
	2142	+ "MSRIndex": "0x1a6, 0x1a7",
2143	2143	"SampleAfterValue": "100003",
2144		- "BriefDescription": "OTHER & L3_MISS_LOCAL_DRAM & ANY_SNOOP",
	2144	+ "BriefDescription": "Counts any other requests",
2145	2145	"Offcore": "1",
2146	2146	"CounterHTOff": "0,1,2,3"
2147	2147	},
2148	2148	{
2149		- "PublicDescription": "Counts any other requests that miss the L3 with no details on snoop-related information. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2149	+ "PublicDescription": "Counts any other requests",
2150	2150	"EventCode": "0xB7, 0xBB",
2151		- "MSRValue": "0x00bc008000 ",
	2151	+ "MSRValue": "0x00BC008000",
2152	2152	"Counter": "0,1,2,3",
2153	2153	"UMask": "0x1",
2154	2154	"EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_NONE",
2155		- "MSRIndex": "0x1a6,0x1a7",
	2155	+ "MSRIndex": "0x1a6, 0x1a7",
2156	2156	"SampleAfterValue": "100003",
2157		- "BriefDescription": "Counts any other requests that miss the L3 with no details on snoop-related information.",
	2157	+ "BriefDescription": "Counts any other requests",
2158	2158	"Offcore": "1",
2159	2159	"CounterHTOff": "0,1,2,3"
2160	2160	},
2161	2161	{
2162		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2162	+ "PublicDescription": "Counts any other requests",
2163	2163	"EventCode": "0xB7, 0xBB",
2164		- "MSRValue": "0x013c008000 ",
	2164	+ "MSRValue": "0x013C008000",
2165	2165	"Counter": "0,1,2,3",
2166	2166	"UMask": "0x1",
2167	2167	"EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_NOT_NEEDED",
2168		- "MSRIndex": "0x1a6,0x1a7",
	2168	+ "MSRIndex": "0x1a6, 0x1a7",
2169	2169	"SampleAfterValue": "100003",
2170		- "BriefDescription": "OTHER & L3_MISS & SNOOP_NOT_NEEDED",
	2170	+ "BriefDescription": "Counts any other requests",
2171	2171	"Offcore": "1",
2172	2172	"CounterHTOff": "0,1,2,3"
2173	2173	},
2174	2174	{
2175		- "PublicDescription": "Counts any other requests that miss the L3 with a snoop miss response. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2175	+ "PublicDescription": "Counts any other requests",
2176	2176	"EventCode": "0xB7, 0xBB",
2177		- "MSRValue": "0x023c008000 ",
	2177	+ "MSRValue": "0x023C008000",
2178	2178	"Counter": "0,1,2,3",
2179	2179	"UMask": "0x1",
2180	2180	"EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_MISS",
2181		- "MSRIndex": "0x1a6,0x1a7",
	2181	+ "MSRIndex": "0x1a6, 0x1a7",
2182	2182	"SampleAfterValue": "100003",
2183		- "BriefDescription": "Counts any other requests that miss the L3 with a snoop miss response.",
	2183	+ "BriefDescription": "Counts any other requests",
2184	2184	"Offcore": "1",
2185	2185	"CounterHTOff": "0,1,2,3"
2186	2186	},
2187	2187	{
2188		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2188	+ "PublicDescription": "Counts any other requests",
2189	2189	"EventCode": "0xB7, 0xBB",
2190		- "MSRValue": "0x043c008000 ",
	2190	+ "MSRValue": "0x043C008000",
2191	2191	"Counter": "0,1,2,3",
2192	2192	"UMask": "0x1",
2193	2193	"EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_HIT_NO_FWD",
2194		- "MSRIndex": "0x1a6,0x1a7",
	2194	+ "MSRIndex": "0x1a6, 0x1a7",
2195	2195	"SampleAfterValue": "100003",
2196		- "BriefDescription": "OTHER & L3_MISS & SNOOP_HIT_NO_FWD",
	2196	+ "BriefDescription": "Counts any other requests",
2197	2197	"Offcore": "1",
2198	2198	"CounterHTOff": "0,1,2,3"
2199	2199	},
2200	2200	{
2201		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2201	+ "PublicDescription": "Counts all prefetch data reads",
2202	2202	"EventCode": "0xB7, 0xBB",
2203		- "MSRValue": "0x2000020090 ",
	2203	+ "MSRValue": "0x2000020090",
2204	2204	"Counter": "0,1,2,3",
2205	2205	"UMask": "0x1",
2206	2206	"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_NON_DRAM",
2207		- "MSRIndex": "0x1a6,0x1a7",
	2207	+ "MSRIndex": "0x1a6, 0x1a7",
2208	2208	"SampleAfterValue": "100003",
2209		- "BriefDescription": "ALL_PF_DATA_RD & SUPPLIER_NONE & SNOOP_NON_DRAM",
	2209	+ "BriefDescription": "Counts all prefetch data reads",
2210	2210	"Offcore": "1",
2211	2211	"CounterHTOff": "0,1,2,3"
2212	2212	},
2213	2213	{
2214		- "PublicDescription": "Counts all prefetch data reads that hit in the L3 and the target was non-DRAM system address. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2214	+ "PublicDescription": "Counts all prefetch data reads",
2215	2215	"EventCode": "0xB7, 0xBB",
2216		- "MSRValue": "0x20003c0090 ",
	2216	+ "MSRValue": "0x20003C0090",
2217	2217	"Counter": "0,1,2,3",
2218	2218	"UMask": "0x1",
2219	2219	"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_NON_DRAM",
2220		- "MSRIndex": "0x1a6,0x1a7",
	2220	+ "MSRIndex": "0x1a6, 0x1a7",
2221	2221	"SampleAfterValue": "100003",
2222		- "BriefDescription": "Counts all prefetch data reads that hit in the L3 and the target was non-DRAM system address.",
	2222	+ "BriefDescription": "Counts all prefetch data reads",
2223	2223	"Offcore": "1",
2224	2224	"CounterHTOff": "0,1,2,3"
2225	2225	},
2226	2226	{
2227		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2227	+ "PublicDescription": "Counts all prefetch data reads",
2228	2228	"EventCode": "0xB7, 0xBB",
2229		- "MSRValue": "0x0084000090 ",
	2229	+ "MSRValue": "0x0084000090",
2230	2230	"Counter": "0,1,2,3",
2231	2231	"UMask": "0x1",
2232	2232	"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
2233		- "MSRIndex": "0x1a6,0x1a7",
	2233	+ "MSRIndex": "0x1a6, 0x1a7",
2234	2234	"SampleAfterValue": "100003",
2235		- "BriefDescription": "ALL_PF_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_NONE",
	2235	+ "BriefDescription": "Counts all prefetch data reads",
2236	2236	"Offcore": "1",
2237	2237	"CounterHTOff": "0,1,2,3"
2238	2238	},
2239	2239	{
2240		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2240	+ "PublicDescription": "Counts all prefetch data reads",
2241	2241	"EventCode": "0xB7, 0xBB",
2242		- "MSRValue": "0x0104000090 ",
	2242	+ "MSRValue": "0x0104000090",
2243	2243	"Counter": "0,1,2,3",
2244	2244	"UMask": "0x1",
2245	2245	"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",
2246		- "MSRIndex": "0x1a6,0x1a7",
	2246	+ "MSRIndex": "0x1a6, 0x1a7",
2247	2247	"SampleAfterValue": "100003",
2248		- "BriefDescription": "ALL_PF_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_NOT_NEEDED",
	2248	+ "BriefDescription": "Counts all prefetch data reads",
2249	2249	"Offcore": "1",
2250	2250	"CounterHTOff": "0,1,2,3"
2251	2251	},
2252	2252	{
2253		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2253	+ "PublicDescription": "Counts all prefetch data reads",
2254	2254	"EventCode": "0xB7, 0xBB",
2255		- "MSRValue": "0x0204000090 ",
	2255	+ "MSRValue": "0x0204000090",
2256	2256	"Counter": "0,1,2,3",
2257	2257	"UMask": "0x1",
2258	2258	"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
2259		- "MSRIndex": "0x1a6,0x1a7",
	2259	+ "MSRIndex": "0x1a6, 0x1a7",
2260	2260	"SampleAfterValue": "100003",
2261		- "BriefDescription": "ALL_PF_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_MISS",
	2261	+ "BriefDescription": "Counts all prefetch data reads",
2262	2262	"Offcore": "1",
2263	2263	"CounterHTOff": "0,1,2,3"
2264	2264	},
2265	2265	{
2266		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2266	+ "PublicDescription": "Counts all prefetch data reads",
2267	2267	"EventCode": "0xB7, 0xBB",
2268		- "MSRValue": "0x0404000090 ",
	2268	+ "MSRValue": "0x0404000090",
2269	2269	"Counter": "0,1,2,3",
2270	2270	"UMask": "0x1",
2271	2271	"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",
2272		- "MSRIndex": "0x1a6,0x1a7",
	2272	+ "MSRIndex": "0x1a6, 0x1a7",
2273	2273	"SampleAfterValue": "100003",
2274		- "BriefDescription": "ALL_PF_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_HIT_NO_FWD",
	2274	+ "BriefDescription": "Counts all prefetch data reads",
2275	2275	"Offcore": "1",
2276	2276	"CounterHTOff": "0,1,2,3"
2277	2277	},
2278	2278	{
2279		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2279	+ "PublicDescription": "Counts all prefetch data reads",
2280	2280	"EventCode": "0xB7, 0xBB",
2281		- "MSRValue": "0x1004000090 ",
	2281	+ "MSRValue": "0x1004000090",
2282	2282	"Counter": "0,1,2,3",
2283	2283	"UMask": "0x1",
2284	2284	"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM",
2285		- "MSRIndex": "0x1a6,0x1a7",
	2285	+ "MSRIndex": "0x1a6, 0x1a7",
2286	2286	"SampleAfterValue": "100003",
2287		- "BriefDescription": "ALL_PF_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_HITM",
	2287	+ "BriefDescription": "Counts all prefetch data reads",
2288	2288	"Offcore": "1",
2289	2289	"CounterHTOff": "0,1,2,3"
2290	2290	},
2291	2291	{
2292		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2292	+ "PublicDescription": "Counts all prefetch data reads",
2293	2293	"EventCode": "0xB7, 0xBB",
2294		- "MSRValue": "0x2004000090 ",
	2294	+ "MSRValue": "0x2004000090",
2295	2295	"Counter": "0,1,2,3",
2296	2296	"UMask": "0x1",
2297	2297	"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",
2298		- "MSRIndex": "0x1a6,0x1a7",
	2298	+ "MSRIndex": "0x1a6, 0x1a7",
2299	2299	"SampleAfterValue": "100003",
2300		- "BriefDescription": "ALL_PF_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_NON_DRAM",
	2300	+ "BriefDescription": "Counts all prefetch data reads",
2301	2301	"Offcore": "1",
2302	2302	"CounterHTOff": "0,1,2,3"
2303	2303	},
2304	2304	{
2305		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2305	+ "PublicDescription": "Counts all prefetch data reads",
2306	2306	"EventCode": "0xB7, 0xBB",
2307		- "MSRValue": "0x3f84000090 ",
	2307	+ "MSRValue": "0x3F84000090",
2308	2308	"Counter": "0,1,2,3",
2309	2309	"UMask": "0x1",
2310	2310	"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
2311		- "MSRIndex": "0x1a6,0x1a7",
	2311	+ "MSRIndex": "0x1a6, 0x1a7",
2312	2312	"SampleAfterValue": "100003",
2313		- "BriefDescription": "ALL_PF_DATA_RD & L3_MISS_LOCAL_DRAM & ANY_SNOOP",
	2313	+ "BriefDescription": "Counts all prefetch data reads",
2314	2314	"Offcore": "1",
2315	2315	"CounterHTOff": "0,1,2,3"
2316	2316	},
2317	2317	{
2318		- "PublicDescription": "Counts all prefetch data reads that miss the L3 with no details on snoop-related information. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2318	+ "PublicDescription": "Counts all prefetch data reads",
2319	2319	"EventCode": "0xB7, 0xBB",
2320		- "MSRValue": "0x00bc000090 ",
	2320	+ "MSRValue": "0x00BC000090",
2321	2321	"Counter": "0,1,2,3",
2322	2322	"UMask": "0x1",
2323	2323	"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.SNOOP_NONE",
2324		- "MSRIndex": "0x1a6,0x1a7",
	2324	+ "MSRIndex": "0x1a6, 0x1a7",
2325	2325	"SampleAfterValue": "100003",
2326		- "BriefDescription": "Counts all prefetch data reads that miss the L3 with no details on snoop-related information.",
	2326	+ "BriefDescription": "Counts all prefetch data reads",
2327	2327	"Offcore": "1",
2328	2328	"CounterHTOff": "0,1,2,3"
2329	2329	},
2330	2330	{
2331		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2331	+ "PublicDescription": "Counts all prefetch data reads",
2332	2332	"EventCode": "0xB7, 0xBB",
2333		- "MSRValue": "0x013c000090 ",
	2333	+ "MSRValue": "0x013C000090",
2334	2334	"Counter": "0,1,2,3",
2335	2335	"UMask": "0x1",
2336	2336	"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.SNOOP_NOT_NEEDED",
2337		- "MSRIndex": "0x1a6,0x1a7",
	2337	+ "MSRIndex": "0x1a6, 0x1a7",
2338	2338	"SampleAfterValue": "100003",
2339		- "BriefDescription": "ALL_PF_DATA_RD & L3_MISS & SNOOP_NOT_NEEDED",
	2339	+ "BriefDescription": "Counts all prefetch data reads",
2340	2340	"Offcore": "1",
2341	2341	"CounterHTOff": "0,1,2,3"
2342	2342	},
2343	2343	{
2344		- "PublicDescription": "Counts all prefetch data reads that miss the L3 with a snoop miss response. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2344	+ "PublicDescription": "Counts all prefetch data reads",
2345	2345	"EventCode": "0xB7, 0xBB",
2346		- "MSRValue": "0x023c000090 ",
	2346	+ "MSRValue": "0x023C000090",
2347	2347	"Counter": "0,1,2,3",
2348	2348	"UMask": "0x1",
2349	2349	"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.SNOOP_MISS",
2350		- "MSRIndex": "0x1a6,0x1a7",
	2350	+ "MSRIndex": "0x1a6, 0x1a7",
2351	2351	"SampleAfterValue": "100003",
2352		- "BriefDescription": "Counts all prefetch data reads that miss the L3 with a snoop miss response.",
	2352	+ "BriefDescription": "Counts all prefetch data reads",
2353	2353	"Offcore": "1",
2354	2354	"CounterHTOff": "0,1,2,3"
2355	2355	},
2356	2356	{
2357		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2357	+ "PublicDescription": "Counts all prefetch data reads",
2358	2358	"EventCode": "0xB7, 0xBB",
2359		- "MSRValue": "0x043c000090 ",
	2359	+ "MSRValue": "0x043C000090",
2360	2360	"Counter": "0,1,2,3",
2361	2361	"UMask": "0x1",
2362	2362	"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.SNOOP_HIT_NO_FWD",
2363		- "MSRIndex": "0x1a6,0x1a7",
	2363	+ "MSRIndex": "0x1a6, 0x1a7",
2364	2364	"SampleAfterValue": "100003",
2365		- "BriefDescription": "ALL_PF_DATA_RD & L3_MISS & SNOOP_HIT_NO_FWD",
	2365	+ "BriefDescription": "Counts all prefetch data reads",
2366	2366	"Offcore": "1",
2367	2367	"CounterHTOff": "0,1,2,3"
2368	2368	},
2369	2369	{
2370		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2370	+ "PublicDescription": "Counts prefetch RFOs",
2371	2371	"EventCode": "0xB7, 0xBB",
2372		- "MSRValue": "0x2000020120 ",
	2372	+ "MSRValue": "0x2000020120",
2373	2373	"Counter": "0,1,2,3",
2374	2374	"UMask": "0x1",
2375	2375	"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_NON_DRAM",
2376		- "MSRIndex": "0x1a6,0x1a7",
	2376	+ "MSRIndex": "0x1a6, 0x1a7",
2377	2377	"SampleAfterValue": "100003",
2378		- "BriefDescription": "ALL_PF_RFO & SUPPLIER_NONE & SNOOP_NON_DRAM",
	2378	+ "BriefDescription": "Counts prefetch RFOs",
2379	2379	"Offcore": "1",
2380	2380	"CounterHTOff": "0,1,2,3"
2381	2381	},
2382	2382	{
2383		- "PublicDescription": "Counts prefetch RFOs that hit in the L3 and the target was non-DRAM system address. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2383	+ "PublicDescription": "Counts prefetch RFOs",
2384	2384	"EventCode": "0xB7, 0xBB",
2385		- "MSRValue": "0x20003c0120 ",
	2385	+ "MSRValue": "0x20003C0120",
2386	2386	"Counter": "0,1,2,3",
2387	2387	"UMask": "0x1",
2388	2388	"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_NON_DRAM",
2389		- "MSRIndex": "0x1a6,0x1a7",
	2389	+ "MSRIndex": "0x1a6, 0x1a7",
2390	2390	"SampleAfterValue": "100003",
2391		- "BriefDescription": "Counts prefetch RFOs that hit in the L3 and the target was non-DRAM system address.",
	2391	+ "BriefDescription": "Counts prefetch RFOs",
2392	2392	"Offcore": "1",
2393	2393	"CounterHTOff": "0,1,2,3"
2394	2394	},
2395	2395	{
2396		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2396	+ "PublicDescription": "Counts prefetch RFOs",
2397	2397	"EventCode": "0xB7, 0xBB",
2398		- "MSRValue": "0x0084000120 ",
	2398	+ "MSRValue": "0x0084000120",
2399	2399	"Counter": "0,1,2,3",
2400	2400	"UMask": "0x1",
2401	2401	"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
2402		- "MSRIndex": "0x1a6,0x1a7",
	2402	+ "MSRIndex": "0x1a6, 0x1a7",
2403	2403	"SampleAfterValue": "100003",
2404		- "BriefDescription": "ALL_PF_RFO & L3_MISS_LOCAL_DRAM & SNOOP_NONE",
	2404	+ "BriefDescription": "Counts prefetch RFOs",
2405	2405	"Offcore": "1",
2406	2406	"CounterHTOff": "0,1,2,3"
2407	2407	},
2408	2408	{
2409		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2409	+ "PublicDescription": "Counts prefetch RFOs",
2410	2410	"EventCode": "0xB7, 0xBB",
2411		- "MSRValue": "0x0104000120 ",
	2411	+ "MSRValue": "0x0104000120",
2412	2412	"Counter": "0,1,2,3",
2413	2413	"UMask": "0x1",
2414	2414	"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",
2415		- "MSRIndex": "0x1a6,0x1a7",
	2415	+ "MSRIndex": "0x1a6, 0x1a7",
2416	2416	"SampleAfterValue": "100003",
2417		- "BriefDescription": "ALL_PF_RFO & L3_MISS_LOCAL_DRAM & SNOOP_NOT_NEEDED",
	2417	+ "BriefDescription": "Counts prefetch RFOs",
2418	2418	"Offcore": "1",
2419	2419	"CounterHTOff": "0,1,2,3"
2420	2420	},
2421	2421	{
2422		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2422	+ "PublicDescription": "Counts prefetch RFOs",
2423	2423	"EventCode": "0xB7, 0xBB",
2424		- "MSRValue": "0x0204000120 ",
	2424	+ "MSRValue": "0x0204000120",
2425	2425	"Counter": "0,1,2,3",
2426	2426	"UMask": "0x1",
2427	2427	"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
2428		- "MSRIndex": "0x1a6,0x1a7",
	2428	+ "MSRIndex": "0x1a6, 0x1a7",
2429	2429	"SampleAfterValue": "100003",
2430		- "BriefDescription": "ALL_PF_RFO & L3_MISS_LOCAL_DRAM & SNOOP_MISS",
	2430	+ "BriefDescription": "Counts prefetch RFOs",
2431	2431	"Offcore": "1",
2432	2432	"CounterHTOff": "0,1,2,3"
2433	2433	},
2434	2434	{
2435		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2435	+ "PublicDescription": "Counts prefetch RFOs",
2436	2436	"EventCode": "0xB7, 0xBB",
2437		- "MSRValue": "0x0404000120 ",
	2437	+ "MSRValue": "0x0404000120",
2438	2438	"Counter": "0,1,2,3",
2439	2439	"UMask": "0x1",
2440	2440	"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",
2441		- "MSRIndex": "0x1a6,0x1a7",
	2441	+ "MSRIndex": "0x1a6, 0x1a7",
2442	2442	"SampleAfterValue": "100003",
2443		- "BriefDescription": "ALL_PF_RFO & L3_MISS_LOCAL_DRAM & SNOOP_HIT_NO_FWD",
	2443	+ "BriefDescription": "Counts prefetch RFOs",
2444	2444	"Offcore": "1",
2445	2445	"CounterHTOff": "0,1,2,3"
2446	2446	},
2447	2447	{
2448		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2448	+ "PublicDescription": "Counts prefetch RFOs",
2449	2449	"EventCode": "0xB7, 0xBB",
2450		- "MSRValue": "0x1004000120 ",
	2450	+ "MSRValue": "0x1004000120",
2451	2451	"Counter": "0,1,2,3",
2452	2452	"UMask": "0x1",
2453	2453	"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HITM",
2454		- "MSRIndex": "0x1a6,0x1a7",
	2454	+ "MSRIndex": "0x1a6, 0x1a7",
2455	2455	"SampleAfterValue": "100003",
2456		- "BriefDescription": "ALL_PF_RFO & L3_MISS_LOCAL_DRAM & SNOOP_HITM",
	2456	+ "BriefDescription": "Counts prefetch RFOs",
2457	2457	"Offcore": "1",
2458	2458	"CounterHTOff": "0,1,2,3"
2459	2459	},
2460	2460	{
2461		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2461	+ "PublicDescription": "Counts prefetch RFOs",
2462	2462	"EventCode": "0xB7, 0xBB",
2463		- "MSRValue": "0x2004000120 ",
	2463	+ "MSRValue": "0x2004000120",
2464	2464	"Counter": "0,1,2,3",
2465	2465	"UMask": "0x1",
2466	2466	"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",
2467		- "MSRIndex": "0x1a6,0x1a7",
	2467	+ "MSRIndex": "0x1a6, 0x1a7",
2468	2468	"SampleAfterValue": "100003",
2469		- "BriefDescription": "ALL_PF_RFO & L3_MISS_LOCAL_DRAM & SNOOP_NON_DRAM",
	2469	+ "BriefDescription": "Counts prefetch RFOs",
2470	2470	"Offcore": "1",
2471	2471	"CounterHTOff": "0,1,2,3"
2472	2472	},
2473	2473	{
2474		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2474	+ "PublicDescription": "Counts prefetch RFOs",
2475	2475	"EventCode": "0xB7, 0xBB",
2476		- "MSRValue": "0x3f84000120 ",
	2476	+ "MSRValue": "0x3F84000120",
2477	2477	"Counter": "0,1,2,3",
2478	2478	"UMask": "0x1",
2479	2479	"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
2480		- "MSRIndex": "0x1a6,0x1a7",
	2480	+ "MSRIndex": "0x1a6, 0x1a7",
2481	2481	"SampleAfterValue": "100003",
2482		- "BriefDescription": "ALL_PF_RFO & L3_MISS_LOCAL_DRAM & ANY_SNOOP",
	2482	+ "BriefDescription": "Counts prefetch RFOs",
2483	2483	"Offcore": "1",
2484	2484	"CounterHTOff": "0,1,2,3"
2485	2485	},
2486	2486	{
2487		- "PublicDescription": "Counts prefetch RFOs that miss the L3 with no details on snoop-related information. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2487	+ "PublicDescription": "Counts prefetch RFOs",
2488	2488	"EventCode": "0xB7, 0xBB",
2489		- "MSRValue": "0x00bc000120 ",
	2489	+ "MSRValue": "0x00BC000120",
2490	2490	"Counter": "0,1,2,3",
2491	2491	"UMask": "0x1",
2492	2492	"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.SNOOP_NONE",
2493		- "MSRIndex": "0x1a6,0x1a7",
	2493	+ "MSRIndex": "0x1a6, 0x1a7",
2494	2494	"SampleAfterValue": "100003",
2495		- "BriefDescription": "Counts prefetch RFOs that miss the L3 with no details on snoop-related information.",
	2495	+ "BriefDescription": "Counts prefetch RFOs",
2496	2496	"Offcore": "1",
2497	2497	"CounterHTOff": "0,1,2,3"
2498	2498	},
2499	2499	{
2500		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2500	+ "PublicDescription": "Counts prefetch RFOs",
2501	2501	"EventCode": "0xB7, 0xBB",
2502		- "MSRValue": "0x013c000120 ",
	2502	+ "MSRValue": "0x013C000120",
2503	2503	"Counter": "0,1,2,3",
2504	2504	"UMask": "0x1",
2505	2505	"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.SNOOP_NOT_NEEDED",
2506		- "MSRIndex": "0x1a6,0x1a7",
	2506	+ "MSRIndex": "0x1a6, 0x1a7",
2507	2507	"SampleAfterValue": "100003",
2508		- "BriefDescription": "ALL_PF_RFO & L3_MISS & SNOOP_NOT_NEEDED",
	2508	+ "BriefDescription": "Counts prefetch RFOs",
2509	2509	"Offcore": "1",
2510	2510	"CounterHTOff": "0,1,2,3"
2511	2511	},
2512	2512	{
2513		- "PublicDescription": "Counts prefetch RFOs that miss the L3 with a snoop miss response. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2513	+ "PublicDescription": "Counts prefetch RFOs",
2514	2514	"EventCode": "0xB7, 0xBB",
2515		- "MSRValue": "0x023c000120 ",
	2515	+ "MSRValue": "0x023C000120",
2516	2516	"Counter": "0,1,2,3",
2517	2517	"UMask": "0x1",
2518	2518	"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.SNOOP_MISS",
2519		- "MSRIndex": "0x1a6,0x1a7",
	2519	+ "MSRIndex": "0x1a6, 0x1a7",
2520	2520	"SampleAfterValue": "100003",
2521		- "BriefDescription": "Counts prefetch RFOs that miss the L3 with a snoop miss response.",
	2521	+ "BriefDescription": "Counts prefetch RFOs",
2522	2522	"Offcore": "1",
2523	2523	"CounterHTOff": "0,1,2,3"
2524	2524	},
2525	2525	{
2526		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2526	+ "PublicDescription": "Counts prefetch RFOs",
2527	2527	"EventCode": "0xB7, 0xBB",
2528		- "MSRValue": "0x043c000120 ",
	2528	+ "MSRValue": "0x043C000120",
2529	2529	"Counter": "0,1,2,3",
2530	2530	"UMask": "0x1",
2531	2531	"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.SNOOP_HIT_NO_FWD",
2532		- "MSRIndex": "0x1a6,0x1a7",
	2532	+ "MSRIndex": "0x1a6, 0x1a7",
2533	2533	"SampleAfterValue": "100003",
2534		- "BriefDescription": "ALL_PF_RFO & L3_MISS & SNOOP_HIT_NO_FWD",
	2534	+ "BriefDescription": "Counts prefetch RFOs",
2535	2535	"Offcore": "1",
2536	2536	"CounterHTOff": "0,1,2,3"
2537	2537	},
2538	2538	{
2539		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2539	+ "PublicDescription": "Counts all prefetch code reads",
2540	2540	"EventCode": "0xB7, 0xBB",
2541		- "MSRValue": "0x2000020240 ",
	2541	+ "MSRValue": "0x2000020240",
2542	2542	"Counter": "0,1,2,3",
2543	2543	"UMask": "0x1",
2544	2544	"EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.SUPPLIER_NONE.SNOOP_NON_DRAM",
2545		- "MSRIndex": "0x1a6,0x1a7",
	2545	+ "MSRIndex": "0x1a6, 0x1a7",
2546	2546	"SampleAfterValue": "100003",
2547		- "BriefDescription": "ALL_PF_CODE_RD & SUPPLIER_NONE & SNOOP_NON_DRAM",
	2547	+ "BriefDescription": "Counts all prefetch code reads",
2548	2548	"Offcore": "1",
2549	2549	"CounterHTOff": "0,1,2,3"
2550	2550	},
2551	2551	{
2552		- "PublicDescription": "Counts all prefetch code reads that hit in the L3 and the target was non-DRAM system address. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2552	+ "PublicDescription": "Counts all prefetch code reads",
2553	2553	"EventCode": "0xB7, 0xBB",
2554		- "MSRValue": "0x20003c0240 ",
	2554	+ "MSRValue": "0x20003C0240",
2555	2555	"Counter": "0,1,2,3",
2556	2556	"UMask": "0x1",
2557	2557	"EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_HIT.SNOOP_NON_DRAM",
2558		- "MSRIndex": "0x1a6,0x1a7",
	2558	+ "MSRIndex": "0x1a6, 0x1a7",
2559	2559	"SampleAfterValue": "100003",
2560		- "BriefDescription": "Counts all prefetch code reads that hit in the L3 and the target was non-DRAM system address.",
	2560	+ "BriefDescription": "Counts all prefetch code reads",
2561	2561	"Offcore": "1",
2562	2562	"CounterHTOff": "0,1,2,3"
2563	2563	},
2564	2564	{
2565		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2565	+ "PublicDescription": "Counts all prefetch code reads",
2566	2566	"EventCode": "0xB7, 0xBB",
2567		- "MSRValue": "0x0084000240 ",
	2567	+ "MSRValue": "0x0084000240",
2568	2568	"Counter": "0,1,2,3",
2569	2569	"UMask": "0x1",
2570	2570	"EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
2571		- "MSRIndex": "0x1a6,0x1a7",
	2571	+ "MSRIndex": "0x1a6, 0x1a7",
2572	2572	"SampleAfterValue": "100003",
2573		- "BriefDescription": "ALL_PF_CODE_RD & L3_MISS_LOCAL_DRAM & SNOOP_NONE",
	2573	+ "BriefDescription": "Counts all prefetch code reads",
2574	2574	"Offcore": "1",
2575	2575	"CounterHTOff": "0,1,2,3"
2576	2576	},
2577	2577	{
2578		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2578	+ "PublicDescription": "Counts all prefetch code reads",
2579	2579	"EventCode": "0xB7, 0xBB",
2580		- "MSRValue": "0x0104000240 ",
	2580	+ "MSRValue": "0x0104000240",
2581	2581	"Counter": "0,1,2,3",
2582	2582	"UMask": "0x1",
2583	2583	"EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",
2584		- "MSRIndex": "0x1a6,0x1a7",
	2584	+ "MSRIndex": "0x1a6, 0x1a7",
2585	2585	"SampleAfterValue": "100003",
2586		- "BriefDescription": "ALL_PF_CODE_RD & L3_MISS_LOCAL_DRAM & SNOOP_NOT_NEEDED",
	2586	+ "BriefDescription": "Counts all prefetch code reads",
2587	2587	"Offcore": "1",
2588	2588	"CounterHTOff": "0,1,2,3"
2589	2589	},
2590	2590	{
2591		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2591	+ "PublicDescription": "Counts all prefetch code reads",
2592	2592	"EventCode": "0xB7, 0xBB",
2593		- "MSRValue": "0x0204000240 ",
	2593	+ "MSRValue": "0x0204000240",
2594	2594	"Counter": "0,1,2,3",
2595	2595	"UMask": "0x1",
2596	2596	"EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
2597		- "MSRIndex": "0x1a6,0x1a7",
	2597	+ "MSRIndex": "0x1a6, 0x1a7",
2598	2598	"SampleAfterValue": "100003",
2599		- "BriefDescription": "ALL_PF_CODE_RD & L3_MISS_LOCAL_DRAM & SNOOP_MISS",
	2599	+ "BriefDescription": "Counts all prefetch code reads",
2600	2600	"Offcore": "1",
2601	2601	"CounterHTOff": "0,1,2,3"
2602	2602	},
2603	2603	{
2604		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2604	+ "PublicDescription": "Counts all prefetch code reads",
2605	2605	"EventCode": "0xB7, 0xBB",
2606		- "MSRValue": "0x0404000240 ",
	2606	+ "MSRValue": "0x0404000240",
2607	2607	"Counter": "0,1,2,3",
2608	2608	"UMask": "0x1",
2609	2609	"EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",
2610		- "MSRIndex": "0x1a6,0x1a7",
	2610	+ "MSRIndex": "0x1a6, 0x1a7",
2611	2611	"SampleAfterValue": "100003",
2612		- "BriefDescription": "ALL_PF_CODE_RD & L3_MISS_LOCAL_DRAM & SNOOP_HIT_NO_FWD",
	2612	+ "BriefDescription": "Counts all prefetch code reads",
2613	2613	"Offcore": "1",
2614	2614	"CounterHTOff": "0,1,2,3"
2615	2615	},
2616	2616	{
2617		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2617	+ "PublicDescription": "Counts all prefetch code reads",
2618	2618	"EventCode": "0xB7, 0xBB",
2619		- "MSRValue": "0x1004000240 ",
	2619	+ "MSRValue": "0x1004000240",
2620	2620	"Counter": "0,1,2,3",
2621	2621	"UMask": "0x1",
2622	2622	"EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM",
2623		- "MSRIndex": "0x1a6,0x1a7",
	2623	+ "MSRIndex": "0x1a6, 0x1a7",
2624	2624	"SampleAfterValue": "100003",
2625		- "BriefDescription": "ALL_PF_CODE_RD & L3_MISS_LOCAL_DRAM & SNOOP_HITM",
	2625	+ "BriefDescription": "Counts all prefetch code reads",
2626	2626	"Offcore": "1",
2627	2627	"CounterHTOff": "0,1,2,3"
2628	2628	},
2629	2629	{
2630		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2630	+ "PublicDescription": "Counts all prefetch code reads",
2631	2631	"EventCode": "0xB7, 0xBB",
2632		- "MSRValue": "0x2004000240 ",
	2632	+ "MSRValue": "0x2004000240",
2633	2633	"Counter": "0,1,2,3",
2634	2634	"UMask": "0x1",
2635	2635	"EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",
2636		- "MSRIndex": "0x1a6,0x1a7",
	2636	+ "MSRIndex": "0x1a6, 0x1a7",
2637	2637	"SampleAfterValue": "100003",
2638		- "BriefDescription": "ALL_PF_CODE_RD & L3_MISS_LOCAL_DRAM & SNOOP_NON_DRAM",
	2638	+ "BriefDescription": "Counts all prefetch code reads",
2639	2639	"Offcore": "1",
2640	2640	"CounterHTOff": "0,1,2,3"
2641	2641	},
2642	2642	{
2643		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2643	+ "PublicDescription": "Counts all prefetch code reads",
2644	2644	"EventCode": "0xB7, 0xBB",
2645		- "MSRValue": "0x3f84000240 ",
	2645	+ "MSRValue": "0x3F84000240",
2646	2646	"Counter": "0,1,2,3",
2647	2647	"UMask": "0x1",
2648	2648	"EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
2649		- "MSRIndex": "0x1a6,0x1a7",
	2649	+ "MSRIndex": "0x1a6, 0x1a7",
2650	2650	"SampleAfterValue": "100003",
2651		- "BriefDescription": "ALL_PF_CODE_RD & L3_MISS_LOCAL_DRAM & ANY_SNOOP",
	2651	+ "BriefDescription": "Counts all prefetch code reads",
2652	2652	"Offcore": "1",
2653	2653	"CounterHTOff": "0,1,2,3"
2654	2654	},
2655	2655	{
2656		- "PublicDescription": "Counts all prefetch code reads that miss the L3 with no details on snoop-related information. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2656	+ "PublicDescription": "Counts all prefetch code reads",
2657	2657	"EventCode": "0xB7, 0xBB",
2658		- "MSRValue": "0x00bc000240 ",
	2658	+ "MSRValue": "0x00BC000240",
2659	2659	"Counter": "0,1,2,3",
2660	2660	"UMask": "0x1",
2661	2661	"EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS.SNOOP_NONE",
2662		- "MSRIndex": "0x1a6,0x1a7",
	2662	+ "MSRIndex": "0x1a6, 0x1a7",
2663	2663	"SampleAfterValue": "100003",
2664		- "BriefDescription": "Counts all prefetch code reads that miss the L3 with no details on snoop-related information.",
	2664	+ "BriefDescription": "Counts all prefetch code reads",
2665	2665	"Offcore": "1",
2666	2666	"CounterHTOff": "0,1,2,3"
2667	2667	},
2668	2668	{
2669		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2669	+ "PublicDescription": "Counts all prefetch code reads",
2670	2670	"EventCode": "0xB7, 0xBB",
2671		- "MSRValue": "0x013c000240 ",
	2671	+ "MSRValue": "0x013C000240",
2672	2672	"Counter": "0,1,2,3",
2673	2673	"UMask": "0x1",
2674	2674	"EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS.SNOOP_NOT_NEEDED",
2675		- "MSRIndex": "0x1a6,0x1a7",
	2675	+ "MSRIndex": "0x1a6, 0x1a7",
2676	2676	"SampleAfterValue": "100003",
2677		- "BriefDescription": "ALL_PF_CODE_RD & L3_MISS & SNOOP_NOT_NEEDED",
	2677	+ "BriefDescription": "Counts all prefetch code reads",
2678	2678	"Offcore": "1",
2679	2679	"CounterHTOff": "0,1,2,3"
2680	2680	},
2681	2681	{
2682		- "PublicDescription": "Counts all prefetch code reads that miss the L3 with a snoop miss response. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2682	+ "PublicDescription": "Counts all prefetch code reads",
2683	2683	"EventCode": "0xB7, 0xBB",
2684		- "MSRValue": "0x023c000240 ",
	2684	+ "MSRValue": "0x023C000240",
2685	2685	"Counter": "0,1,2,3",
2686	2686	"UMask": "0x1",
2687	2687	"EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS.SNOOP_MISS",
2688		- "MSRIndex": "0x1a6,0x1a7",
	2688	+ "MSRIndex": "0x1a6, 0x1a7",
2689	2689	"SampleAfterValue": "100003",
2690		- "BriefDescription": "Counts all prefetch code reads that miss the L3 with a snoop miss response.",
	2690	+ "BriefDescription": "Counts all prefetch code reads",
2691	2691	"Offcore": "1",
2692	2692	"CounterHTOff": "0,1,2,3"
2693	2693	},
2694	2694	{
2695		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2695	+ "PublicDescription": "Counts all prefetch code reads",
2696	2696	"EventCode": "0xB7, 0xBB",
2697		- "MSRValue": "0x043c000240 ",
	2697	+ "MSRValue": "0x043C000240",
2698	2698	"Counter": "0,1,2,3",
2699	2699	"UMask": "0x1",
2700	2700	"EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS.SNOOP_HIT_NO_FWD",
2701		- "MSRIndex": "0x1a6,0x1a7",
	2701	+ "MSRIndex": "0x1a6, 0x1a7",
2702	2702	"SampleAfterValue": "100003",
2703		- "BriefDescription": "ALL_PF_CODE_RD & L3_MISS & SNOOP_HIT_NO_FWD",
	2703	+ "BriefDescription": "Counts all prefetch code reads",
2704	2704	"Offcore": "1",
2705	2705	"CounterHTOff": "0,1,2,3"
2706	2706	},
2707	2707	{
2708		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2708	+ "PublicDescription": "Counts all demand & prefetch data reads",
2709	2709	"EventCode": "0xB7, 0xBB",
2710		- "MSRValue": "0x2000020091 ",
	2710	+ "MSRValue": "0x2000020091",
2711	2711	"Counter": "0,1,2,3",
2712	2712	"UMask": "0x1",
2713	2713	"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NON_DRAM",
2714		- "MSRIndex": "0x1a6,0x1a7",
	2714	+ "MSRIndex": "0x1a6, 0x1a7",
2715	2715	"SampleAfterValue": "100003",
2716		- "BriefDescription": "ALL_DATA_RD & SUPPLIER_NONE & SNOOP_NON_DRAM",
	2716	+ "BriefDescription": "Counts all demand & prefetch data reads",
2717	2717	"Offcore": "1",
2718	2718	"CounterHTOff": "0,1,2,3"
2719	2719	},
2720	2720	{
2721		- "PublicDescription": "Counts all demand & prefetch data reads that hit in the L3 and the target was non-DRAM system address. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2721	+ "PublicDescription": "Counts all demand & prefetch data reads",
2722	2722	"EventCode": "0xB7, 0xBB",
2723		- "MSRValue": "0x20003c0091 ",
	2723	+ "MSRValue": "0x20003C0091",
2724	2724	"Counter": "0,1,2,3",
2725	2725	"UMask": "0x1",
2726	2726	"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_NON_DRAM",
2727		- "MSRIndex": "0x1a6,0x1a7",
	2727	+ "MSRIndex": "0x1a6, 0x1a7",
2728	2728	"SampleAfterValue": "100003",
2729		- "BriefDescription": "Counts all demand & prefetch data reads that hit in the L3 and the target was non-DRAM system address.",
	2729	+ "BriefDescription": "Counts all demand & prefetch data reads",
2730	2730	"Offcore": "1",
2731	2731	"CounterHTOff": "0,1,2,3"
2732	2732	},
2733	2733	{
2734		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2734	+ "PublicDescription": "Counts all demand & prefetch data reads",
2735	2735	"EventCode": "0xB7, 0xBB",
2736		- "MSRValue": "0x0084000091 ",
	2736	+ "MSRValue": "0x0084000091",
2737	2737	"Counter": "0,1,2,3",
2738	2738	"UMask": "0x1",
2739	2739	"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
2740		- "MSRIndex": "0x1a6,0x1a7",
	2740	+ "MSRIndex": "0x1a6, 0x1a7",
2741	2741	"SampleAfterValue": "100003",
2742		- "BriefDescription": "ALL_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_NONE",
	2742	+ "BriefDescription": "Counts all demand & prefetch data reads",
2743	2743	"Offcore": "1",
2744	2744	"CounterHTOff": "0,1,2,3"
2745	2745	},
2746	2746	{
2747		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2747	+ "PublicDescription": "Counts all demand & prefetch data reads",
2748	2748	"EventCode": "0xB7, 0xBB",
2749		- "MSRValue": "0x0104000091 ",
	2749	+ "MSRValue": "0x0104000091",
2750	2750	"Counter": "0,1,2,3",
2751	2751	"UMask": "0x1",
2752	2752	"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",
2753		- "MSRIndex": "0x1a6,0x1a7",
	2753	+ "MSRIndex": "0x1a6, 0x1a7",
2754	2754	"SampleAfterValue": "100003",
2755		- "BriefDescription": "ALL_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_NOT_NEEDED",
	2755	+ "BriefDescription": "Counts all demand & prefetch data reads",
2756	2756	"Offcore": "1",
2757	2757	"CounterHTOff": "0,1,2,3"
2758	2758	},
2759	2759	{
2760		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2760	+ "PublicDescription": "Counts all demand & prefetch data reads",
2761	2761	"EventCode": "0xB7, 0xBB",
2762		- "MSRValue": "0x0204000091 ",
	2762	+ "MSRValue": "0x0204000091",
2763	2763	"Counter": "0,1,2,3",
2764	2764	"UMask": "0x1",
2765	2765	"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
2766		- "MSRIndex": "0x1a6,0x1a7",
	2766	+ "MSRIndex": "0x1a6, 0x1a7",
2767	2767	"SampleAfterValue": "100003",
2768		- "BriefDescription": "ALL_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_MISS",
	2768	+ "BriefDescription": "Counts all demand & prefetch data reads",
2769	2769	"Offcore": "1",
2770	2770	"CounterHTOff": "0,1,2,3"
2771	2771	},
2772	2772	{
2773		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2773	+ "PublicDescription": "Counts all demand & prefetch data reads",
2774	2774	"EventCode": "0xB7, 0xBB",
2775		- "MSRValue": "0x0404000091 ",
	2775	+ "MSRValue": "0x0404000091",
2776	2776	"Counter": "0,1,2,3",
2777	2777	"UMask": "0x1",
2778	2778	"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",
2779		- "MSRIndex": "0x1a6,0x1a7",
	2779	+ "MSRIndex": "0x1a6, 0x1a7",
2780	2780	"SampleAfterValue": "100003",
2781		- "BriefDescription": "ALL_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_HIT_NO_FWD",
	2781	+ "BriefDescription": "Counts all demand & prefetch data reads",
2782	2782	"Offcore": "1",
2783	2783	"CounterHTOff": "0,1,2,3"
2784	2784	},
2785	2785	{
2786		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2786	+ "PublicDescription": "Counts all demand & prefetch data reads",
2787	2787	"EventCode": "0xB7, 0xBB",
2788		- "MSRValue": "0x1004000091 ",
	2788	+ "MSRValue": "0x1004000091",
2789	2789	"Counter": "0,1,2,3",
2790	2790	"UMask": "0x1",
2791	2791	"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM",
2792		- "MSRIndex": "0x1a6,0x1a7",
	2792	+ "MSRIndex": "0x1a6, 0x1a7",
2793	2793	"SampleAfterValue": "100003",
2794		- "BriefDescription": "ALL_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_HITM",
	2794	+ "BriefDescription": "Counts all demand & prefetch data reads",
2795	2795	"Offcore": "1",
2796	2796	"CounterHTOff": "0,1,2,3"
2797	2797	},
2798	2798	{
2799		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2799	+ "PublicDescription": "Counts all demand & prefetch data reads",
2800	2800	"EventCode": "0xB7, 0xBB",
2801		- "MSRValue": "0x2004000091 ",
	2801	+ "MSRValue": "0x2004000091",
2802	2802	"Counter": "0,1,2,3",
2803	2803	"UMask": "0x1",
2804	2804	"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",
2805		- "MSRIndex": "0x1a6,0x1a7",
	2805	+ "MSRIndex": "0x1a6, 0x1a7",
2806	2806	"SampleAfterValue": "100003",
2807		- "BriefDescription": "ALL_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_NON_DRAM",
	2807	+ "BriefDescription": "Counts all demand & prefetch data reads",
2808	2808	"Offcore": "1",
2809	2809	"CounterHTOff": "0,1,2,3"
2810	2810	},
2811	2811	{
2812		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2812	+ "PublicDescription": "Counts all demand & prefetch data reads",
2813	2813	"EventCode": "0xB7, 0xBB",
2814		- "MSRValue": "0x3f84000091 ",
	2814	+ "MSRValue": "0x3F84000091",
2815	2815	"Counter": "0,1,2,3",
2816	2816	"UMask": "0x1",
2817	2817	"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
2818		- "MSRIndex": "0x1a6,0x1a7",
	2818	+ "MSRIndex": "0x1a6, 0x1a7",
2819	2819	"SampleAfterValue": "100003",
2820		- "BriefDescription": "ALL_DATA_RD & L3_MISS_LOCAL_DRAM & ANY_SNOOP",
	2820	+ "BriefDescription": "Counts all demand & prefetch data reads",
2821	2821	"Offcore": "1",
2822	2822	"CounterHTOff": "0,1,2,3"
2823	2823	},
2824	2824	{
2825		- "PublicDescription": "Counts all demand & prefetch data reads that miss the L3 with no details on snoop-related information. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2825	+ "PublicDescription": "Counts all demand & prefetch data reads",
2826	2826	"EventCode": "0xB7, 0xBB",
2827		- "MSRValue": "0x00bc000091 ",
	2827	+ "MSRValue": "0x00BC000091",
2828	2828	"Counter": "0,1,2,3",
2829	2829	"UMask": "0x1",
2830	2830	"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.SNOOP_NONE",
2831		- "MSRIndex": "0x1a6,0x1a7",
	2831	+ "MSRIndex": "0x1a6, 0x1a7",
2832	2832	"SampleAfterValue": "100003",
2833		- "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 with no details on snoop-related information.",
	2833	+ "BriefDescription": "Counts all demand & prefetch data reads",
2834	2834	"Offcore": "1",
2835	2835	"CounterHTOff": "0,1,2,3"
2836	2836	},
2837	2837	{
2838		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2838	+ "PublicDescription": "Counts all demand & prefetch data reads",
2839	2839	"EventCode": "0xB7, 0xBB",
2840		- "MSRValue": "0x013c000091 ",
	2840	+ "MSRValue": "0x013C000091",
2841	2841	"Counter": "0,1,2,3",
2842	2842	"UMask": "0x1",
2843	2843	"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.SNOOP_NOT_NEEDED",
2844		- "MSRIndex": "0x1a6,0x1a7",
	2844	+ "MSRIndex": "0x1a6, 0x1a7",
2845	2845	"SampleAfterValue": "100003",
2846		- "BriefDescription": "ALL_DATA_RD & L3_MISS & SNOOP_NOT_NEEDED",
	2846	+ "BriefDescription": "Counts all demand & prefetch data reads",
2847	2847	"Offcore": "1",
2848	2848	"CounterHTOff": "0,1,2,3"
2849	2849	},
2850	2850	{
2851		- "PublicDescription": "Counts all demand & prefetch data reads that miss the L3 with a snoop miss response. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2851	+ "PublicDescription": "Counts all demand & prefetch data reads",
2852	2852	"EventCode": "0xB7, 0xBB",
2853		- "MSRValue": "0x023c000091 ",
	2853	+ "MSRValue": "0x023C000091",
2854	2854	"Counter": "0,1,2,3",
2855	2855	"UMask": "0x1",
2856	2856	"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.SNOOP_MISS",
2857		- "MSRIndex": "0x1a6,0x1a7",
	2857	+ "MSRIndex": "0x1a6, 0x1a7",
2858	2858	"SampleAfterValue": "100003",
2859		- "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 with a snoop miss response.",
	2859	+ "BriefDescription": "Counts all demand & prefetch data reads",
2860	2860	"Offcore": "1",
2861	2861	"CounterHTOff": "0,1,2,3"
2862	2862	},
2863	2863	{
2864		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2864	+ "PublicDescription": "Counts all demand & prefetch data reads",
2865	2865	"EventCode": "0xB7, 0xBB",
2866		- "MSRValue": "0x043c000091 ",
	2866	+ "MSRValue": "0x043C000091",
2867	2867	"Counter": "0,1,2,3",
2868	2868	"UMask": "0x1",
2869	2869	"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.SNOOP_HIT_NO_FWD",
2870		- "MSRIndex": "0x1a6,0x1a7",
	2870	+ "MSRIndex": "0x1a6, 0x1a7",
2871	2871	"SampleAfterValue": "100003",
2872		- "BriefDescription": "ALL_DATA_RD & L3_MISS & SNOOP_HIT_NO_FWD",
	2872	+ "BriefDescription": "Counts all demand & prefetch data reads",
2873	2873	"Offcore": "1",
2874	2874	"CounterHTOff": "0,1,2,3"
2875	2875	},
2876	2876	{
2877		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2877	+ "PublicDescription": "Counts all demand & prefetch RFOs",
2878	2878	"EventCode": "0xB7, 0xBB",
2879		- "MSRValue": "0x2000020122 ",
	2879	+ "MSRValue": "0x2000020122",
2880	2880	"Counter": "0,1,2,3",
2881	2881	"UMask": "0x1",
2882	2882	"EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.SNOOP_NON_DRAM",
2883		- "MSRIndex": "0x1a6,0x1a7",
	2883	+ "MSRIndex": "0x1a6, 0x1a7",
2884	2884	"SampleAfterValue": "100003",
2885		- "BriefDescription": "ALL_RFO & SUPPLIER_NONE & SNOOP_NON_DRAM",
	2885	+ "BriefDescription": "Counts all demand & prefetch RFOs",
2886	2886	"Offcore": "1",
2887	2887	"CounterHTOff": "0,1,2,3"
2888	2888	},
2889	2889	{
2890		- "PublicDescription": "Counts all demand & prefetch RFOs that hit in the L3 and the target was non-DRAM system address. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2890	+ "PublicDescription": "Counts all demand & prefetch RFOs",
2891	2891	"EventCode": "0xB7, 0xBB",
2892		- "MSRValue": "0x20003c0122 ",
	2892	+ "MSRValue": "0x20003C0122",
2893	2893	"Counter": "0,1,2,3",
2894	2894	"UMask": "0x1",
2895	2895	"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_NON_DRAM",
2896		- "MSRIndex": "0x1a6,0x1a7",
	2896	+ "MSRIndex": "0x1a6, 0x1a7",
2897	2897	"SampleAfterValue": "100003",
2898		- "BriefDescription": "Counts all demand & prefetch RFOs that hit in the L3 and the target was non-DRAM system address.",
	2898	+ "BriefDescription": "Counts all demand & prefetch RFOs",
2899	2899	"Offcore": "1",
2900	2900	"CounterHTOff": "0,1,2,3"
2901	2901	},
2902	2902	{
2903		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2903	+ "PublicDescription": "Counts all demand & prefetch RFOs",
2904	2904	"EventCode": "0xB7, 0xBB",
2905		- "MSRValue": "0x0084000122 ",
	2905	+ "MSRValue": "0x0084000122",
2906	2906	"Counter": "0,1,2,3",
2907	2907	"UMask": "0x1",
2908	2908	"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
2909		- "MSRIndex": "0x1a6,0x1a7",
	2909	+ "MSRIndex": "0x1a6, 0x1a7",
2910	2910	"SampleAfterValue": "100003",
2911		- "BriefDescription": "ALL_RFO & L3_MISS_LOCAL_DRAM & SNOOP_NONE",
	2911	+ "BriefDescription": "Counts all demand & prefetch RFOs",
2912	2912	"Offcore": "1",
2913	2913	"CounterHTOff": "0,1,2,3"
2914	2914	},
2915	2915	{
2916		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2916	+ "PublicDescription": "Counts all demand & prefetch RFOs",
2917	2917	"EventCode": "0xB7, 0xBB",
2918		- "MSRValue": "0x0104000122 ",
	2918	+ "MSRValue": "0x0104000122",
2919	2919	"Counter": "0,1,2,3",
2920	2920	"UMask": "0x1",
2921	2921	"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",
2922		- "MSRIndex": "0x1a6,0x1a7",
	2922	+ "MSRIndex": "0x1a6, 0x1a7",
2923	2923	"SampleAfterValue": "100003",
2924		- "BriefDescription": "ALL_RFO & L3_MISS_LOCAL_DRAM & SNOOP_NOT_NEEDED",
	2924	+ "BriefDescription": "Counts all demand & prefetch RFOs",
2925	2925	"Offcore": "1",
2926	2926	"CounterHTOff": "0,1,2,3"
2927	2927	},
2928	2928	{
2929		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2929	+ "PublicDescription": "Counts all demand & prefetch RFOs",
2930	2930	"EventCode": "0xB7, 0xBB",
2931		- "MSRValue": "0x0204000122 ",
	2931	+ "MSRValue": "0x0204000122",
2932	2932	"Counter": "0,1,2,3",
2933	2933	"UMask": "0x1",
2934	2934	"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
2935		- "MSRIndex": "0x1a6,0x1a7",
	2935	+ "MSRIndex": "0x1a6, 0x1a7",
2936	2936	"SampleAfterValue": "100003",
2937		- "BriefDescription": "ALL_RFO & L3_MISS_LOCAL_DRAM & SNOOP_MISS",
	2937	+ "BriefDescription": "Counts all demand & prefetch RFOs",
2938	2938	"Offcore": "1",
2939	2939	"CounterHTOff": "0,1,2,3"
2940	2940	},
2941	2941	{
2942		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2942	+ "PublicDescription": "Counts all demand & prefetch RFOs",
2943	2943	"EventCode": "0xB7, 0xBB",
2944		- "MSRValue": "0x0404000122 ",
	2944	+ "MSRValue": "0x0404000122",
2945	2945	"Counter": "0,1,2,3",
2946	2946	"UMask": "0x1",
2947	2947	"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",
2948		- "MSRIndex": "0x1a6,0x1a7",
	2948	+ "MSRIndex": "0x1a6, 0x1a7",
2949	2949	"SampleAfterValue": "100003",
2950		- "BriefDescription": "ALL_RFO & L3_MISS_LOCAL_DRAM & SNOOP_HIT_NO_FWD",
	2950	+ "BriefDescription": "Counts all demand & prefetch RFOs",
2951	2951	"Offcore": "1",
2952	2952	"CounterHTOff": "0,1,2,3"
2953	2953	},
2954	2954	{
2955		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2955	+ "PublicDescription": "Counts all demand & prefetch RFOs",
2956	2956	"EventCode": "0xB7, 0xBB",
2957		- "MSRValue": "0x1004000122 ",
	2957	+ "MSRValue": "0x1004000122",
2958	2958	"Counter": "0,1,2,3",
2959	2959	"UMask": "0x1",
2960	2960	"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HITM",
2961		- "MSRIndex": "0x1a6,0x1a7",
	2961	+ "MSRIndex": "0x1a6, 0x1a7",
2962	2962	"SampleAfterValue": "100003",
2963		- "BriefDescription": "ALL_RFO & L3_MISS_LOCAL_DRAM & SNOOP_HITM",
	2963	+ "BriefDescription": "Counts all demand & prefetch RFOs",
2964	2964	"Offcore": "1",
2965	2965	"CounterHTOff": "0,1,2,3"
2966	2966	},
2967	2967	{
2968		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2968	+ "PublicDescription": "Counts all demand & prefetch RFOs",
2969	2969	"EventCode": "0xB7, 0xBB",
2970		- "MSRValue": "0x2004000122 ",
	2970	+ "MSRValue": "0x2004000122",
2971	2971	"Counter": "0,1,2,3",
2972	2972	"UMask": "0x1",
2973	2973	"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",
2974		- "MSRIndex": "0x1a6,0x1a7",
	2974	+ "MSRIndex": "0x1a6, 0x1a7",
2975	2975	"SampleAfterValue": "100003",
2976		- "BriefDescription": "ALL_RFO & L3_MISS_LOCAL_DRAM & SNOOP_NON_DRAM",
	2976	+ "BriefDescription": "Counts all demand & prefetch RFOs",
2977	2977	"Offcore": "1",
2978	2978	"CounterHTOff": "0,1,2,3"
2979	2979	},
2980	2980	{
2981		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2981	+ "PublicDescription": "Counts all demand & prefetch RFOs",
2982	2982	"EventCode": "0xB7, 0xBB",
2983		- "MSRValue": "0x3f84000122 ",
	2983	+ "MSRValue": "0x3F84000122",
2984	2984	"Counter": "0,1,2,3",
2985	2985	"UMask": "0x1",
2986	2986	"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
2987		- "MSRIndex": "0x1a6,0x1a7",
	2987	+ "MSRIndex": "0x1a6, 0x1a7",
2988	2988	"SampleAfterValue": "100003",
2989		- "BriefDescription": "ALL_RFO & L3_MISS_LOCAL_DRAM & ANY_SNOOP",
	2989	+ "BriefDescription": "Counts all demand & prefetch RFOs",
2990	2990	"Offcore": "1",
2991	2991	"CounterHTOff": "0,1,2,3"
2992	2992	},
2993	2993	{
2994		- "PublicDescription": "Counts all demand & prefetch RFOs that miss the L3 with no details on snoop-related information. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	2994	+ "PublicDescription": "Counts all demand & prefetch RFOs",
2995	2995	"EventCode": "0xB7, 0xBB",
2996		- "MSRValue": "0x00bc000122 ",
	2996	+ "MSRValue": "0x00BC000122",
2997	2997	"Counter": "0,1,2,3",
2998	2998	"UMask": "0x1",
2999	2999	"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.SNOOP_NONE",
3000		- "MSRIndex": "0x1a6,0x1a7",
	3000	+ "MSRIndex": "0x1a6, 0x1a7",
3001	3001	"SampleAfterValue": "100003",
3002		- "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 with no details on snoop-related information.",
	3002	+ "BriefDescription": "Counts all demand & prefetch RFOs",
3003	3003	"Offcore": "1",
3004	3004	"CounterHTOff": "0,1,2,3"
3005	3005	},
3006	3006	{
3007		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	3007	+ "PublicDescription": "Counts all demand & prefetch RFOs",
3008	3008	"EventCode": "0xB7, 0xBB",
3009		- "MSRValue": "0x013c000122 ",
	3009	+ "MSRValue": "0x013C000122",
3010	3010	"Counter": "0,1,2,3",
3011	3011	"UMask": "0x1",
3012	3012	"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.SNOOP_NOT_NEEDED",
3013		- "MSRIndex": "0x1a6,0x1a7",
	3013	+ "MSRIndex": "0x1a6, 0x1a7",
3014	3014	"SampleAfterValue": "100003",
3015		- "BriefDescription": "ALL_RFO & L3_MISS & SNOOP_NOT_NEEDED",
	3015	+ "BriefDescription": "Counts all demand & prefetch RFOs",
3016	3016	"Offcore": "1",
3017	3017	"CounterHTOff": "0,1,2,3"
3018	3018	},
3019	3019	{
3020		- "PublicDescription": "Counts all demand & prefetch RFOs that miss the L3 with a snoop miss response. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	3020	+ "PublicDescription": "Counts all demand & prefetch RFOs",
3021	3021	"EventCode": "0xB7, 0xBB",
3022		- "MSRValue": "0x023c000122 ",
	3022	+ "MSRValue": "0x023C000122",
3023	3023	"Counter": "0,1,2,3",
3024	3024	"UMask": "0x1",
3025	3025	"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.SNOOP_MISS",
3026		- "MSRIndex": "0x1a6,0x1a7",
	3026	+ "MSRIndex": "0x1a6, 0x1a7",
3027	3027	"SampleAfterValue": "100003",
3028		- "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 with a snoop miss response.",
	3028	+ "BriefDescription": "Counts all demand & prefetch RFOs",
3029	3029	"Offcore": "1",
3030	3030	"CounterHTOff": "0,1,2,3"
3031	3031	},
3032	3032	{
3033		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	3033	+ "PublicDescription": "Counts all demand & prefetch RFOs",
3034	3034	"EventCode": "0xB7, 0xBB",
3035		- "MSRValue": "0x043c000122 ",
	3035	+ "MSRValue": "0x043C000122",
3036	3036	"Counter": "0,1,2,3",
3037	3037	"UMask": "0x1",
3038	3038	"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.SNOOP_HIT_NO_FWD",
3039		- "MSRIndex": "0x1a6,0x1a7",
	3039	+ "MSRIndex": "0x1a6, 0x1a7",
3040	3040	"SampleAfterValue": "100003",
3041		- "BriefDescription": "ALL_RFO & L3_MISS & SNOOP_HIT_NO_FWD",
	3041	+ "BriefDescription": "Counts all demand & prefetch RFOs",
3042	3042	"Offcore": "1",
3043	3043	"CounterHTOff": "0,1,2,3"
3044	3044	}